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fix(hal): functions that may generate invalid load/store byte/half-word instructions

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because the APB regsiters can't behave correctly on these instructions
This commit is contained in:
morris 2024-06-14 16:57:48 +08:00
parent dd46392a66
commit 4f03604b2e
16 changed files with 59 additions and 56 deletions
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3
components/hal/esp32/include/hal/sdio_slave_ll.h
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@ -17,6 +17,7 @@
#pragma once
#include "hal/sdio_slave_types.h"
#include "hal/misc.h"
#include "soc/slc_struct.h"
#include "soc/slc_reg.h"
#include "soc/host_struct.h"
@ -514,7 +515,7 @@ static inline void sdio_slave_ll_host_send_int(slc_dev_t *slc, const sdio_slave_
{
//use registers in SLC to trigger, rather than write HOST registers directly
//other interrupts than tohost interrupts are not supported yet
slc->intvec_tohost.slc0_intvec = (*mask);
HAL_FORCE_MODIFY_U32_REG_FIELD(slc->intvec_tohost, slc0_intvec, *mask);
}
/**

6
components/hal/esp32c6/include/hal/etm_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -98,7 +98,7 @@ static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan)
*/
static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event)
{
hw->channel[chan].evt_id.evt_id = event;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, evt_id, event);
}
/**
@ -110,7 +110,7 @@ static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, ui
*/
static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task)
{
hw->channel[chan].task_id.task_id = task;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, task_id, task);
}
#define etm_ll_is_lpcore_wakeup_triggered() lp_aon_ll_get_lpcore_etm_wakeup_flag()

3
components/hal/esp32c6/include/hal/sdio_slave_ll.h
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@ -17,6 +17,7 @@
#pragma once
#include "hal/sdio_slave_types.h"
#include "hal/misc.h"
#include "soc/slc_struct.h"
#include "soc/slc_reg.h"
#include "soc/host_struct.h"
@ -503,7 +504,7 @@ static inline void sdio_slave_ll_host_send_int(slc_dev_t *slc, const sdio_slave_
{
//use registers in SLC to trigger, rather than write HOST registers directly
//other interrupts than tohost interrupts are not supported yet
slc->slcintvec_tohost.slc0_tohost_intvec = (*mask);
HAL_FORCE_MODIFY_U32_REG_FIELD(slc->slcintvec_tohost, slc0_tohost_intvec, *mask);
}
/**

4
components/hal/esp32h2/include/hal/etm_ll.h
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@ -97,7 +97,7 @@ static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan)
*/
static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event)
{
hw->channel[chan].evt_id.evt_id = event;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, evt_id, event);
}
/**
@ -109,7 +109,7 @@ static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, ui
*/
static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task)
{
hw->channel[chan].task_id.task_id = task;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, task_id, task);
}
#ifdef __cplusplus

8
components/hal/esp32h2/include/hal/parlio_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -326,7 +326,7 @@ static inline void parlio_ll_rx_treat_data_line_as_en(parl_io_dev_t *dev, uint32
}
/**
* @brief Wether to enable the RX clock gating
* @brief Whether to enable the RX clock gating
*
* @param dev Parallel IO register base address
* @param en True to enable, False to disable
@ -457,7 +457,7 @@ static inline void parlio_ll_tx_set_trans_bit_len(parl_io_dev_t *dev, uint32_t b
}
/**
* @brief Wether to enable the TX clock gating
* @brief Whether to enable the TX clock gating
*
* @note The MSB of TXD will be taken as the gating enable signal
*
@ -571,7 +571,7 @@ static inline void parlio_ll_tx_reset_fifo(parl_io_dev_t *dev)
__attribute__((always_inline))
static inline void parlio_ll_tx_set_idle_data_value(parl_io_dev_t *dev, uint32_t value)
{
dev->tx_genrl_cfg.tx_idle_value = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_genrl_cfg, tx_idle_value, value);
}
/**

9
components/hal/esp32p4/include/hal/cpu_utility_ll.h
View File

@ -11,6 +11,7 @@
#include "soc/pmu_struct.h"
#include "soc/hp_system_reg.h"
#include "esp_attr.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -29,18 +30,18 @@ FORCE_INLINE_ATTR void cpu_utility_ll_reset_cpu(uint32_t cpu_no)
FORCE_INLINE_ATTR void cpu_utility_ll_stall_cpu(uint32_t cpu_no)
{
if (cpu_no == 0) {
PMU.cpu_sw_stall.hpcore0_stall_code = 0x86;
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore0_stall_code, 0x86);
} else {
PMU.cpu_sw_stall.hpcore1_stall_code = 0x86;
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore1_stall_code, 0x86);
}
}
FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
{
if (cpu_no == 0) {
PMU.cpu_sw_stall.hpcore0_stall_code = 0xFF;
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore0_stall_code, 0xFF);
} else {
PMU.cpu_sw_stall.hpcore1_stall_code = 0xFF;
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore1_stall_code, 0xFF);
}
}
#endif // SOC_CPU_CORES_NUM > 1

4
components/hal/esp32p4/include/hal/dw_gdma_ll.h
View File

@ -1112,7 +1112,7 @@ __attribute__((always_inline))
static inline void dw_gdma_ll_lli_set_src_burst_len(dw_gdma_link_list_item_t *lli, uint8_t len)
{
lli->ctrl_hi.arlen_en = len > 0;
lli->ctrl_hi.arlen = len;
HAL_FORCE_MODIFY_U32_REG_FIELD(lli->ctrl_hi, arlen, len);
}
/**
@ -1125,7 +1125,7 @@ __attribute__((always_inline))
static inline void dw_gdma_ll_lli_set_dst_burst_len(dw_gdma_link_list_item_t *lli, uint8_t len)
{
lli->ctrl_hi.awlen_en = len > 0;
lli->ctrl_hi.awlen = len;
HAL_FORCE_MODIFY_U32_REG_FIELD(lli->ctrl_hi, awlen, len);
}
/**

12
components/hal/esp32p4/include/hal/emac_ll.h
View File

@ -628,11 +628,11 @@ static inline void emac_ll_clock_enable_mii(void *ext_regs)
HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rx_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rx_clk_src_sel = 1; // 0-pad_emac_txrx_clk, 1-pad_emac_rx_clk
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_rx_clk_div_num = 0; // 25MHz
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_rx_clk_div_num, 0); // 25MHz
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_src_sel = 1; // 0-pad_emac_txrx_clk, 1-pad_emac_tx_clk
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_div_num = 0; // 25MHz
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_tx_clk_div_num, 0); // 25MHz
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_emac_tx_clk_en = 1;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_emac_rx_clk_en = 1;
@ -653,11 +653,11 @@ static inline void emac_ll_clock_enable_rmii_input(void *ext_regs)
HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rx_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rx_clk_src_sel = 0; // 0-pad_emac_txrx_clk, 1-pad_emac_rx_clk
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_rx_clk_div_num = 1; // set default divider
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_rx_clk_div_num, 1); // set default divider
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_src_sel = 0; // 0-pad_emac_txrx_clk, 1-pad_emac_tx_clk
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_div_num = 1; // set default divider
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_tx_clk_div_num, 1); // set default divider
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_emac_tx_clk_en = 0;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_emac_rx_clk_en = 0;
@ -670,8 +670,8 @@ static inline void emac_ll_clock_enable_rmii_input(void *ext_regs)
static inline void emac_ll_clock_rmii_rx_tx_div(void *ext_regs, int div)
{
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_rx_clk_div_num = div;
HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_div_num = div;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_rx_clk_div_num, div);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_tx_clk_div_num, div);
}
/// use a macro to wrap the function, force the caller to use it in a critical section

4
components/hal/esp32p4/include/hal/etm_ll.h
View File

@ -106,7 +106,7 @@ static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan)
*/
static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event)
{
hw->channel[chan].evt_id.evt_id = event;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, evt_id, event);
}
/**
@ -118,7 +118,7 @@ static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, ui
*/
static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task)
{
hw->channel[chan].task_id.task_id = task;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, task_id, task);
}
/**

2
components/hal/esp32p4/include/hal/parlio_ll.h
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@ -636,7 +636,7 @@ static inline void parlio_ll_tx_reset_fifo(parl_io_dev_t *dev)
__attribute__((always_inline))
static inline void parlio_ll_tx_set_idle_data_value(parl_io_dev_t *dev, uint32_t value)
{
dev->tx_genrl_cfg.tx_idle_value = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_genrl_cfg, tx_idle_value, value);
}
/**

36
components/hal/esp32p4/include/hal/ppa_ll.h
View File

@ -660,9 +660,9 @@ static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, color_pi
*/
static inline void ppa_ll_blend_set_rx_fg_fix_rgb(ppa_dev_t *dev, color_pixel_rgb888_data_t *rgb)
{
dev->blend_rgb.blend1_rx_b = rgb->b;
dev->blend_rgb.blend1_rx_g = rgb->g;
dev->blend_rgb.blend1_rx_r = rgb->r;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->blend_rgb, blend1_rx_b, rgb->b);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->blend_rgb, blend1_rx_g, rgb->g);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->blend_rgb, blend1_rx_r, rgb->r);
}
/*
@ -682,13 +682,13 @@ static inline void ppa_ll_blend_set_rx_fg_fix_rgb(ppa_dev_t *dev, color_pixel_rg
*/
static inline void ppa_ll_blend_configure_rx_bg_ck_range(ppa_dev_t *dev, color_pixel_rgb888_data_t *rgb_thres_low, color_pixel_rgb888_data_t *rgb_thres_high)
{
dev->ck_bg_low.colorkey_bg_b_low = rgb_thres_low->b;
dev->ck_bg_low.colorkey_bg_g_low = rgb_thres_low->g;
dev->ck_bg_low.colorkey_bg_r_low = rgb_thres_low->r;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_low, colorkey_bg_b_low, rgb_thres_low->b);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_low, colorkey_bg_g_low, rgb_thres_low->g);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_low, colorkey_bg_r_low, rgb_thres_low->r);
dev->ck_bg_high.colorkey_bg_b_high = rgb_thres_high->b;
dev->ck_bg_high.colorkey_bg_g_high = rgb_thres_high->g;
dev->ck_bg_high.colorkey_bg_r_high = rgb_thres_high->r;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_high, colorkey_bg_b_high, rgb_thres_high->b);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_high, colorkey_bg_g_high, rgb_thres_high->g);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_bg_high, colorkey_bg_r_high, rgb_thres_high->r);
}
/**
@ -700,13 +700,13 @@ static inline void ppa_ll_blend_configure_rx_bg_ck_range(ppa_dev_t *dev, color_p
*/
static inline void ppa_ll_blend_configure_rx_fg_ck_range(ppa_dev_t *dev, color_pixel_rgb888_data_t *rgb_thres_low, color_pixel_rgb888_data_t *rgb_thres_high)
{
dev->ck_fg_low.colorkey_fg_b_low = rgb_thres_low->b;
dev->ck_fg_low.colorkey_fg_g_low = rgb_thres_low->g;
dev->ck_fg_low.colorkey_fg_r_low = rgb_thres_low->r;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_low, colorkey_fg_b_low, rgb_thres_low->b);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_low, colorkey_fg_g_low, rgb_thres_low->g);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_low, colorkey_fg_r_low, rgb_thres_low->r);
dev->ck_fg_high.colorkey_fg_b_high = rgb_thres_high->b;
dev->ck_fg_high.colorkey_fg_g_high = rgb_thres_high->g;
dev->ck_fg_high.colorkey_fg_r_high = rgb_thres_high->r;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_high, colorkey_fg_b_high, rgb_thres_high->b);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_high, colorkey_fg_g_high, rgb_thres_high->g);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_fg_high, colorkey_fg_r_high, rgb_thres_high->r);
}
/**
@ -717,9 +717,9 @@ static inline void ppa_ll_blend_configure_rx_fg_ck_range(ppa_dev_t *dev, color_p
*/
static inline void ppa_ll_blend_set_ck_default_rgb(ppa_dev_t *dev, color_pixel_rgb888_data_t *rgb)
{
dev->ck_default.colorkey_default_b = rgb->b;
dev->ck_default.colorkey_default_g = rgb->g;
dev->ck_default.colorkey_default_r = rgb->r;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_default, colorkey_default_b, rgb->b);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_default, colorkey_default_g, rgb->g);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ck_default, colorkey_default_r, rgb->r);
}
/**

8
components/hal/esp32p4/include/hal/psram_ctrlr_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -53,7 +53,7 @@ static inline void psram_ctrlr_ll_set_wr_cmd(uint32_t mspi_id, uint32_t cmd_bitl
HAL_ASSERT(cmd_bitlen > 0);
SPIMEM2.mem_cache_sctrl.mem_cache_sram_usr_wcmd = 1;
SPIMEM2.mem_sram_dwr_cmd.mem_cache_sram_usr_wr_cmd_bitlen = cmd_bitlen - 1;
SPIMEM2.mem_sram_dwr_cmd.mem_cache_sram_usr_wr_cmd_value = cmd_val;
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM2.mem_sram_dwr_cmd, mem_cache_sram_usr_wr_cmd_value, cmd_val);
}
/**
@ -70,7 +70,7 @@ static inline void psram_ctrlr_ll_set_rd_cmd(uint32_t mspi_id, uint32_t cmd_bitl
HAL_ASSERT(cmd_bitlen > 0);
SPIMEM2.mem_cache_sctrl.mem_cache_sram_usr_rcmd = 1;
SPIMEM2.mem_sram_drd_cmd.mem_cache_sram_usr_rd_cmd_bitlen = cmd_bitlen - 1;
SPIMEM2.mem_sram_drd_cmd.mem_cache_sram_usr_rd_cmd_value = cmd_val;
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM2.mem_sram_drd_cmd, mem_cache_sram_usr_rd_cmd_value, cmd_val);
}
/**
@ -501,7 +501,7 @@ static inline void psram_ctrlr_ll_enable_skip_page_corner(uint32_t mspi_id, bool
}
/**
* @brief Enable spliting transactions
* @brief Enable splitting transactions
*
* @param mspi_id mspi_id
* @param en enable / disable

2
components/hal/esp32p4/include/hal/spimem_flash_ll.h
View File

@ -570,7 +570,7 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
{
dev->cache_fctrl.cache_usr_addr_4byte = 0;
dev->rd_status.wb_mode = extra_addr;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rd_status, wb_mode, extra_addr);
}
/**

4
components/soc/esp32c6/include/soc/soc_etm_struct.h
View File

@ -735,8 +735,8 @@ typedef struct soc_etm_dev_t {
volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
volatile struct {
soc_etm_chn_evt_id_reg_t evt_id;
soc_etm_chn_task_id_reg_t task_id;
soc_etm_chn_evt_id_reg_t eid;
soc_etm_chn_task_id_reg_t tid;
} channel[50];
volatile soc_etm_clk_en_reg_t clk_en;
volatile soc_etm_date_reg_t date;

4
components/soc/esp32h2/include/soc/soc_etm_struct.h
View File

@ -735,8 +735,8 @@ typedef struct soc_etm_dev_t {
volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
volatile struct {
soc_etm_chn_evt_id_reg_t evt_id;
soc_etm_chn_task_id_reg_t task_id;
soc_etm_chn_evt_id_reg_t eid;
soc_etm_chn_task_id_reg_t tid;
} channel[50];
volatile soc_etm_clk_en_reg_t clk_en;
volatile soc_etm_date_reg_t date;

4
components/soc/esp32p4/include/soc/soc_etm_struct.h
View File

@ -5084,8 +5084,8 @@ typedef struct soc_etm_dev_t {
volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
volatile struct {
soc_etm_chn_evt_id_reg_t evt_id;
soc_etm_chn_task_id_reg_t task_id;
soc_etm_chn_evt_id_reg_t eid;
soc_etm_chn_task_id_reg_t tid;
} channel[50];
volatile soc_etm_evt_st0_reg_t evt_st0;
volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr;