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Reorganize the memory to maximize contiguous DRAM

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1. Fix bug for variable sdkconfig_header in CMakeLists.txt
2. Modify the load address of bootloader
3. Modify the load address of application program
This commit is contained in:
jiangguangming 2019-09-06 11:15:53 +08:00
parent c057c141eb
commit 4ef4b29c74
3 changed files with 35 additions and 17 deletions
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7
components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld
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@ -13,10 +13,9 @@ MEMORY
{
/* I/O */
dport0_seg (RW) : org = 0x3FF00000, len = 0x10
/* IRAM POOL1, used for APP CPU cache. Bootloader runs from here during the final stage of loading the app because APP CPU is still held in reset, the main app enables APP CPU cache */
iram_loader_seg (RWX) : org = 0x40022000, len = 0x2000 /* 8KB, APP CPU cache */
iram_seg (RWX) : org = 0x40024000, len = 0x4000 /* 16KB, IRAM */
/* 16k at the end of DRAM, after ROM bootloader stack */
iram_loader_seg (RWX) : org = 0x40062000, len = 0x2000 /* 8KB, IRAM */
iram_seg (RWX) : org = 0x40064000, len = 0x4000 /* 16KB, IRAM */
/* 16k at the end of DRAM, before ROM data & stack */
dram_seg (RW) : org = 0x3FFF8000, len = 0x4000
}

1
components/esp32s2beta/CMakeLists.txt
View File

@ -1,4 +1,5 @@
idf_build_get_property(target IDF_TARGET)
idf_build_get_property(sdkconfig_header SDKCONFIG_HEADER)
if(NOT "${target}" STREQUAL "esp32s2beta")
return()
endif()

44
components/esp32s2beta/ld/esp32s2beta.ld
View File

@ -1,4 +1,4 @@
/* ESP32 Linker Script Memory Layout
/* ESP32S2Beta Linker Script Memory Layout
This file describes the memory layout (memory blocks) as virtual
memory addresses.
@ -16,19 +16,42 @@
*/
#include "sdkconfig.h"
/* If BT is not built at all */
#ifndef CONFIG_BT_RESERVE_DRAM
#define CONFIG_BT_RESERVE_DRAM 0
#ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x2000
#else
#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x4000
#endif
#ifdef CONFIG_ESP32S2_DATA_CACHE_0KB
#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0
#elif defined CONFIG_ESP32S2_DATA_CACHE_8KB
#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x2000
#else
#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x4000
#endif
#define RAM_IRAM_START 0x40020000
#define RAM_DRAM_START 0x3FFB0000
#define DATA_RAM_END 0x3FFF2000 /* start address of bootloader */
#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
#define IRAM_SIZE 0x18000
#define DRAM_ORG (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
+ CONFIG_ESP32S2_DATA_CACHE_SIZE \
+ IRAM_SIZE)
#define DRAM_SIZE DATA_RAM_END - DRAM_ORG
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_0_seg (RX) : org = 0x40028000, len = 0x18000
/* IRAM for CPU.*/
iram0_0_seg (RX) : org = IRAM_ORG, len = IRAM_SIZE
/* Even though the segment name is iram, it is actually mapped to flash
*/
@ -41,17 +64,12 @@ MEMORY
*/
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
/* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack.
Enabling Bluetooth & Trace Memory features in menuconfig will decrease
the amount of RAM available.
Note: Length of this section *should* be 0x50000, and this extra DRAM is available
in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
additional static memory temporarily cannot be used.
*/
dram0_0_seg (RW) : org = 0x3FFD0000 + CONFIG_BT_RESERVE_DRAM,
len = 0x28000 - CONFIG_BT_RESERVE_DRAM
dram0_0_seg (RW) : org = DRAM_ORG, len = DRAM_SIZE
/* Flash mapped constant data */
drom0_0_seg (R) : org = 0x3F000018, len = 0x3f0000-0x18