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Merge branch 'bugfix/bod_glitch_reset_c6' into 'master'

Browse Source 
bootloader: fix BOD and glitch reset on C6 and H2

Closes IDF-5990

See merge request espressif/esp-idf!22616
This commit is contained in:
Jiang Jiang Jian 2023-04-11 19:31:02 +08:00
commit 4e3a32bc1b
21 changed files with 93 additions and 123 deletions
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12
components/bootloader_support/src/esp32/bootloader_soc.c
View File

@ -3,18 +3,10 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
void bootloader_ana_super_wdt_reset_config(bool enable)
{
(void)enable;
}
void bootloader_ana_bod_reset_config(bool enable)
{
(void)enable;
}
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
(void)enable;

10
components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
View File

@ -34,6 +34,7 @@
#include "bootloader_mem.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "bootloader_soc.h"
#include "esp_private/bootloader_flash_internal.h"
#include "esp_efuse.h"
#include "hal/mmu_hal.h"
@ -78,10 +79,19 @@ static void bootloader_super_wdt_auto_feed(void)
REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
}
static inline void bootloader_ana_reset_config(void)
{
//Enable super WDT reset.
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD reset
bootloader_ana_bod_reset_config(true);
}
esp_err_t bootloader_init(void)
{
esp_err_t ret = ESP_OK;
bootloader_ana_reset_config();
bootloader_super_wdt_auto_feed();
// In RAM_APP, memory will be initialized in `call_start_cpu0`

21
components/bootloader_support/src/esp32c2/bootloader_soc.c
View File

@ -3,19 +3,34 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include "soc/rtc_cntl_reg.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
(void)enable; // ESP32-C2 has none of these features.
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
}
}
void bootloader_ana_bod_reset_config(bool enable)
{
(void)enable; // ESP32-C2 has none of these features.
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
} else {
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
}
}
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
(void)enable; // ESP32-C2 has none of these features.
(void)enable;
}

18
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
View File

@ -96,29 +96,29 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void)
{
//Enable super WDT reset.
bootloader_ana_super_wdt_reset_config(true);
/*
For origin chip & ECO1: only support swt reset;
For ECO2: fix brownout reset bug, support swt & brownout reset;
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
For origin chip & ECO1: brownout & clock glitch reset not available
For ECO2: fix brownout reset bug
For ECO3: fix clock glitch reset bug
*/
switch (efuse_hal_chip_revision()) {
case 0:
case 1:
//Enable WDT reset. Disable BOR and GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
//Disable BOD and GLITCH reset
bootloader_ana_bod_reset_config(false);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 2:
//Enable WDT and BOR reset. Disable GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD reset. Disable GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 3:
default:
//Enable WDT, BOR, and GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD, and GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);
break;

6
components/bootloader_support/src/esp32c3/bootloader_soc.c
View File

@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
}
}
void bootloader_ana_bod_reset_config(bool enable)
{
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST);
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);

31
components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
View File

@ -103,33 +103,10 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void)
{
// TODO: IDF-5990 copied from C3, need update
// Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back
/*
For origin chip & ECO1: only support swt reset;
For ECO2: fix brownout reset bug, support swt & brownout reset;
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
*/
uint8_t chip_version = efuse_hal_get_minor_chip_version();
switch (chip_version) {
case 0:
case 1:
//Disable BOR and GLITCH reset
bootloader_ana_bod_reset_config(false);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 2:
//Enable BOR reset. Disable GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 3:
default:
//Enable BOR, and GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);
break;
}
//Enable super WDT reset.
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD reset
bootloader_ana_bod_reset_config(true);
}
esp_err_t bootloader_init(void)

21
components/bootloader_support/src/esp32c6/bootloader_soc.c
View File

@ -1,15 +1,24 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include <assert.h>
#include "soc/soc.h"
#include "soc/lp_analog_peri_reg.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
//C6 doesn't support bypass super WDT reset
assert(enable);
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
}
void bootloader_ana_bod_reset_config(bool enable)
{
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST);
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
} else {
@ -17,12 +26,8 @@ void bootloader_ana_bod_reset_config(bool enable)
}
}
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST);
if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
} else {
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
}
(void)enable;
}

31
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
View File

@ -93,33 +93,10 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void)
{
// TODO: IDF-5990 copied from C6, need update
// Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back
/*
For origin chip & ECO1: only support swt reset;
For ECO2: fix brownout reset bug, support swt & brownout reset;
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
*/
uint8_t chip_version = efuse_hal_get_minor_chip_version();
switch (chip_version) {
case 0:
case 1:
//Disable BOR and GLITCH reset
bootloader_ana_bod_reset_config(false);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 2:
//Enable BOR reset. Disable GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 3:
default:
//Enable BOR, and GLITCH reset
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);
break;
}
//Enable super WDT reset.
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD reset
bootloader_ana_bod_reset_config(true);
}
esp_err_t bootloader_init(void)

18
components/bootloader_support/src/esp32h2/bootloader_soc.c
View File

@ -1,20 +1,22 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_analog_peri_reg.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
// ESP32H2 has removed the super wdt
//H2 doesn't support bypass super WDT reset
assert(enable);
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
}
void bootloader_ana_bod_reset_config(bool enable)
{
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST);
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
} else {
@ -22,12 +24,8 @@ void bootloader_ana_bod_reset_config(bool enable)
}
}
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST);
if (enable) {
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
} else {
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
}
(void)enable;
}

2
components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
View File

@ -85,7 +85,7 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void)
{
//Enable WDT, BOR, and GLITCH reset
//Enable WDT, BOD, and GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);

6
components/bootloader_support/src/esp32h4/bootloader_soc.c
View File

@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
}
}
void bootloader_ana_bod_reset_config(bool enable)
{
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST);
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);

12
components/bootloader_support/src/esp32s2/bootloader_soc.c
View File

@ -3,18 +3,10 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
void bootloader_ana_super_wdt_reset_config(bool enable)
{
(void)enable;
}
void bootloader_ana_bod_reset_config(bool enable)
{
(void)enable;
}
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
(void)enable;

2
components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
View File

@ -130,7 +130,7 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_ana_reset_config(void)
{
//Enable WDT, BOR, and GLITCH reset
//Enable WDT, BOD, and GLITCH reset
bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true);

6
components/bootloader_support/src/esp32s3/bootloader_soc.c
View File

@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
}
}
void bootloader_ana_bod_reset_config(bool enable)
{
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST);
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);

4
components/soc/esp32c2/include/soc/rtc_cntl_reg.h
View File

@ -1678,6 +1678,10 @@ RO CPU.*/
#define RTC_CNTL_FIB_SEL_V 0x7
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0xFC)
/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : ;bitpos:[31] ;default: 1'b0 ; */
/*description: Need add desc.*/

2
components/soc/esp32c3/include/soc/rtc_cntl_reg.h
View File

@ -2353,7 +2353,7 @@ extern "C" {
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1)
#define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110)

4
components/soc/esp32c6/include/soc/lp_analog_peri_reg.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -109,7 +109,7 @@ extern "C" {
#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0
#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0)
#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1)
#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1)
#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2)
/** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register

4
components/soc/esp32h2/include/soc/lp_analog_peri_reg.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -234,7 +234,7 @@ extern "C" {
#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0
#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0)
#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1)
#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1)
#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2)
/** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register

2
components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h
View File

@ -2727,7 +2727,7 @@ extern "C" {
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1)
#define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x013C)

2
components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h
View File

@ -3475,7 +3475,7 @@ extern "C" {
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1)
#define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
/** RTC_CNTL_GPIO_WAKEUP_REG register

2
components/soc/esp32s3/include/soc/rtc_cntl_reg.h
View File

@ -3571,7 +3571,7 @@ ork.*/
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1)
#define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C)