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fix(ledc): clear ledc_mem_force_pd when LEDC peripheral is in use

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And enable target test for C5 and P4
This commit is contained in:
Song Ruo Jing 2024-07-01 19:43:40 +08:00
parent f978dd0af9
commit 4cd74f51db
13 changed files with 144 additions and 49 deletions
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8
components/esp_driver_ledc/src/ledc.c
View File

@ -304,16 +304,16 @@ static bool ledc_speed_mode_ctx_create(ledc_mode_t speed_mode)
ledc_obj_t *ledc_new_mode_obj = (ledc_obj_t *) heap_caps_calloc(1, sizeof(ledc_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
if (ledc_new_mode_obj) {
new_ctx = true;
LEDC_BUS_CLOCK_ATOMIC() {
ledc_ll_enable_bus_clock(true);
ledc_ll_enable_reset_reg(false);
}
ledc_hal_init(&(ledc_new_mode_obj->ledc_hal), speed_mode);
ledc_new_mode_obj->glb_clk = LEDC_SLOW_CLK_UNINIT;
#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
memset(ledc_new_mode_obj->timer_specific_clk, LEDC_TIMER_SPECIFIC_CLK_UNINIT, sizeof(ledc_clk_src_t) * LEDC_TIMER_MAX);
#endif
p_ledc_obj[speed_mode] = ledc_new_mode_obj;
LEDC_BUS_CLOCK_ATOMIC() {
ledc_ll_enable_bus_clock(true);
ledc_ll_enable_reset_reg(false);
}
}
}
_lock_release(&s_ledc_mutex[speed_mode]);

4
components/esp_driver_ledc/test_apps/.build-test-rules.yml
View File

@ -3,9 +3,5 @@
components/esp_driver_ledc/test_apps/ledc:
disable:
- if: SOC_LEDC_SUPPORTED != 1
disable_test:
- if: IDF_TARGET in ["esp32p4", "esp32c5"]
temporary: true
reason: test not pass, should be re-enable # TODO: [ESP32P4] IDF-8969, [ESP32C5] IDF-10333
depends_components:
- esp_driver_ledc

5
components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py
View File

@ -5,9 +5,8 @@ from pytest_embedded_idf import IdfDut
@pytest.mark.supported_targets
# TODO: [ESP32P4] IDF-8969, [ESP32C5] IDF-10333
@pytest.mark.temp_skip_ci(targets=['esp32s3', 'esp32p4', 'esp32c5'],
reason='skip due to duplication with test_ledc_psram, p4 TBD, c5 test failed')
@pytest.mark.temp_skip_ci(targets=['esp32s3'],
reason='skip due to duplication with test_ledc_psram')
@pytest.mark.generic
@pytest.mark.parametrize(
'config',

19
components/hal/esp32/include/hal/ledc_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -46,7 +46,8 @@ extern "C" {
*
* @param enable Enable/Disable
*/
static inline void ledc_ll_enable_bus_clock(bool enable) {
static inline void ledc_ll_enable_bus_clock(bool enable)
{
if (enable) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN);
} else {
@ -61,7 +62,8 @@ static inline void ledc_ll_enable_bus_clock(bool enable) {
/**
* @brief Reset whole peripheral register to init value defined by HW design
*/
static inline void ledc_ll_enable_reset_reg(bool enable) {
static inline void ledc_ll_enable_reset_reg(bool enable)
{
if (enable) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST);
} else {
@ -73,6 +75,14 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__)
/**
* @brief Enable the power for LEDC memory block
*/
static inline void ledc_ll_enable_mem_power(bool enable)
{
// No LEDC mem block on ESP32
}
/**
* @brief Enable LEDC function clock
*
@ -81,7 +91,8 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
*
* @return None
*/
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) {
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en)
{
//resolve for compatibility
}

19
components/hal/esp32c2/include/hal/ledc_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -40,7 +40,8 @@ extern "C" {
*
* @param enable Enable/Disable
*/
static inline void ledc_ll_enable_bus_clock(bool enable) {
static inline void ledc_ll_enable_bus_clock(bool enable)
{
SYSTEM.perip_clk_en0.ledc_clk_en = enable;
}
@ -51,7 +52,8 @@ static inline void ledc_ll_enable_bus_clock(bool enable) {
/**
* @brief Reset whole peripheral register to init value defined by HW design
*/
static inline void ledc_ll_enable_reset_reg(bool enable) {
static inline void ledc_ll_enable_reset_reg(bool enable)
{
SYSTEM.perip_rst_en0.ledc_rst = enable;
}
@ -59,6 +61,14 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__)
/**
* @brief Enable the power for LEDC memory block
*/
static inline void ledc_ll_enable_mem_power(bool enable)
{
// No LEDC mem block on C2
}
/**
* @brief Enable LEDC function clock
*
@ -67,7 +77,8 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
*
* @return None
*/
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) {
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en)
{
//resolve for compatibility
}

19
components/hal/esp32c3/include/hal/ledc_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -41,7 +41,8 @@ extern "C" {
*
* @param enable Enable/Disable
*/
static inline void ledc_ll_enable_bus_clock(bool enable) {
static inline void ledc_ll_enable_bus_clock(bool enable)
{
SYSTEM.perip_clk_en0.reg_ledc_clk_en = enable;
}
@ -52,7 +53,8 @@ static inline void ledc_ll_enable_bus_clock(bool enable) {
/**
* @brief Reset whole peripheral register to init value defined by HW design
*/
static inline void ledc_ll_enable_reset_reg(bool enable) {
static inline void ledc_ll_enable_reset_reg(bool enable)
{
SYSTEM.perip_rst_en0.reg_ledc_rst = enable;
}
@ -60,6 +62,14 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__)
/**
* @brief Enable the power for LEDC memory block
*/
static inline void ledc_ll_enable_mem_power(bool enable)
{
// No LEDC mem block on C3
}
/**
* @brief Enable LEDC function clock
*
@ -68,7 +78,8 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
*
* @return None
*/
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) {
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en)
{
//resolve for compatibility
}

19
components/hal/esp32c5/include/hal/ledc_ll.h
View File

@ -35,17 +35,29 @@ extern "C" {
*
* @param enable Enable/Disable
*/
static inline void ledc_ll_enable_bus_clock(bool enable) {
static inline void ledc_ll_enable_bus_clock(bool enable)
{
PCR.ledc_conf.ledc_clk_en = enable;
}
/**
* @brief Reset whole peripheral register to init value defined by HW design
*/
static inline void ledc_ll_enable_reset_reg(bool enable) {
static inline void ledc_ll_enable_reset_reg(bool enable)
{
PCR.ledc_conf.ledc_rst_en = enable;
}
/**
* @brief Enable the power for LEDC memory block
*
* Note. This function cannot overwrite the power control of the mem block in sleep mode
*/
static inline void ledc_ll_enable_mem_power(bool enable)
{
PCR.ledc_pd_ctrl.ledc_mem_force_pd = !enable;
}
/**
* @brief Enable LEDC function clock
*
@ -54,7 +66,8 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
*
* @return None
*/
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) {
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en)
{
(void)hw;
PCR.ledc_sclk_conf.ledc_sclk_en = en;
}

18
components/hal/esp32c6/include/hal/ledc_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -38,17 +38,27 @@ extern "C" {
*
* @param enable Enable/Disable
*/
static inline void ledc_ll_enable_bus_clock(bool enable) {
static inline void ledc_ll_enable_bus_clock(bool enable)
{
PCR.ledc_conf.ledc_clk_en = enable;
}
/**
* @brief Reset whole peripheral register to init value defined by HW design
*/
static inline void ledc_ll_enable_reset_reg(bool enable) {
static inline void ledc_ll_enable_reset_reg(bool enable)
{
PCR.ledc_conf.ledc_rst_en = enable;
}
/**
* @brief Enable the power for LEDC memory block
*/
static inline void ledc_ll_enable_mem_power(bool enable)
{
// No register to control the power for LEDC memory block on C6
}
/**
* @brief Enable LEDC function clock
*
@ -539,7 +549,7 @@ static inline void ledc_ll_get_fade_param(ledc_dev_t *hw, ledc_mode_t speed_mode
static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step)
{
// On ESP32C6/H2, gamma ram read/write has the APB and LEDC clock domain sync issue
// To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure syncronization
// To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure synchronization
ledc_ll_set_duty_range_rd_addr(hw, speed_mode, channel_num, range);
esp_rom_delay_us(5);
ledc_ll_get_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step);

18
components/hal/esp32h2/include/hal/ledc_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -36,17 +36,27 @@ extern "C" {
*
* @param enable Enable/Disable
*/
static inline void ledc_ll_enable_bus_clock(bool enable) {
static inline void ledc_ll_enable_bus_clock(bool enable)
{
PCR.ledc_conf.ledc_clk_en = enable;
}
/**
* @brief Reset whole peripheral register to init value defined by HW design
*/
static inline void ledc_ll_enable_reset_reg(bool enable) {
static inline void ledc_ll_enable_reset_reg(bool enable)
{
PCR.ledc_conf.ledc_rst_en = enable;
}
/**
* @brief Enable the power for LEDC memory block
*/
static inline void ledc_ll_enable_mem_power(bool enable)
{
// No register to control the power for LEDC memory block on H2
}
/**
* @brief Enable LEDC function clock
*
@ -537,7 +547,7 @@ static inline void ledc_ll_get_fade_param(ledc_dev_t *hw, ledc_mode_t speed_mode
static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step)
{
// On ESP32C6/H2, gamma ram read/write has the APB and LEDC clock domain sync issue
// To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure syncronization
// To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure synchronization
ledc_ll_set_duty_range_rd_addr(hw, speed_mode, channel_num, range);
esp_rom_delay_us(5);
ledc_ll_get_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step);

19
components/hal/esp32p4/include/hal/ledc_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -35,7 +35,8 @@ extern "C" {
*
* @param enable Enable/Disable
*/
static inline void ledc_ll_enable_bus_clock(bool enable) {
static inline void ledc_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.soc_clk_ctrl3.reg_ledc_apb_clk_en = enable;
}
@ -46,7 +47,8 @@ static inline void ledc_ll_enable_bus_clock(bool enable) {
/**
* @brief Reset whole peripheral register to init value defined by HW design
*/
static inline void ledc_ll_enable_reset_reg(bool enable) {
static inline void ledc_ll_enable_reset_reg(bool enable)
{
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_ledc = enable;
}
@ -54,6 +56,14 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__)
/**
* @brief Enable the power for LEDC memory block
*/
static inline void ledc_ll_enable_mem_power(bool enable)
{
// No register to control the power for LEDC memory block on P4
}
/**
* @brief Enable LEDC function clock
*
@ -62,7 +72,8 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
*
* @return None
*/
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) {
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en)
{
(void)hw;
HP_SYS_CLKRST.peri_clk_ctrl22.reg_ledc_clk_en = en;
}

19
components/hal/esp32s2/include/hal/ledc_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -46,7 +46,8 @@ extern "C" {
*
* @param enable Enable/Disable
*/
static inline void ledc_ll_enable_bus_clock(bool enable) {
static inline void ledc_ll_enable_bus_clock(bool enable)
{
if (enable) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN);
} else {
@ -61,7 +62,8 @@ static inline void ledc_ll_enable_bus_clock(bool enable) {
/**
* @brief Reset whole peripheral register to init value defined by HW design
*/
static inline void ledc_ll_enable_reset_reg(bool enable) {
static inline void ledc_ll_enable_reset_reg(bool enable)
{
if (enable) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST);
} else {
@ -73,6 +75,14 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__)
/**
* @brief Enable the power for LEDC memory block
*/
static inline void ledc_ll_enable_mem_power(bool enable)
{
// No LEDC mem block on S2
}
/**
* @brief Enable LEDC function clock
*
@ -81,7 +91,8 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
*
* @return None
*/
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) {
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en)
{
//resolve for compatibility
}

19
components/hal/esp32s3/include/hal/ledc_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -41,7 +41,8 @@ extern "C" {
*
* @param enable Enable/Disable
*/
static inline void ledc_ll_enable_bus_clock(bool enable) {
static inline void ledc_ll_enable_bus_clock(bool enable)
{
SYSTEM.perip_clk_en0.ledc_clk_en = enable;
}
@ -52,7 +53,8 @@ static inline void ledc_ll_enable_bus_clock(bool enable) {
/**
* @brief Reset whole peripheral register to init value defined by HW design
*/
static inline void ledc_ll_enable_reset_reg(bool enable) {
static inline void ledc_ll_enable_reset_reg(bool enable)
{
SYSTEM.perip_rst_en0.ledc_rst = enable;
}
@ -60,6 +62,14 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__)
/**
* @brief Enable the power for LEDC memory block
*/
static inline void ledc_ll_enable_mem_power(bool enable)
{
// No LEDC mem block on S3
}
/**
* @brief Enable LEDC function clock
*
@ -68,7 +78,8 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
*
* @return None
*/
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) {
static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en)
{
//resolve for compatibility
}

7
components/hal/ledc_hal.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -14,6 +14,7 @@ void ledc_hal_init(ledc_hal_context_t *hal, ledc_mode_t speed_mode)
//Get hardware instance.
hal->dev = LEDC_LL_GET_HW();
hal->speed_mode = speed_mode;
ledc_ll_enable_mem_power(true);
}
void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_clk_cfg_t *clk_cfg)
@ -34,9 +35,9 @@ void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_
#endif
{
/* If the timer-specific mux is not set to REF_TICK, it either means that:
* - The controler is in fast mode, and thus using APB clock (driver_clk
* - The controller is in fast mode, and thus using APB clock (driver_clk
* variable's default value)
* - The controler is in slow mode and so, using a global clock,
* - The controller is in slow mode and so, using a global clock,
* so we have to retrieve that clock here.
*/
if (hal->speed_mode == LEDC_LOW_SPEED_MODE) {