mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-21 06:56:11 -04:00
feat(pm/deepsleep): Support deep_sleep example and deep_sleep_wake_stub example for esp32h2
This commit is contained in:
parent
602d021263
commit
4bc5e24f82
@ -114,12 +114,6 @@ if(NOT BOOTLOADER_BUILD)
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if(CONFIG_SOC_RTC_FAST_MEM_SUPPORTED)
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if(CONFIG_SOC_RTC_FAST_MEM_SUPPORTED)
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list(APPEND srcs "sleep_wake_stub.c")
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list(APPEND srcs "sleep_wake_stub.c")
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endif()
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endif()
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if(CONFIG_IDF_TARGET_ESP32H2)
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list(REMOVE_ITEM srcs
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"sleep_wake_stub.c" # TODO: IDF-6268
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)
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endif()
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else()
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else()
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# Requires "_esp_error_check_failed()" function
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# Requires "_esp_error_check_failed()" function
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list(APPEND priv_requires "esp_system")
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list(APPEND priv_requires "esp_system")
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@ -14,6 +14,7 @@
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#include "soc/soc.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc.h"
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#include "soc/pmu_struct.h"
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#include "soc/pmu_struct.h"
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#include "hal/lp_aon_hal.h"
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#include "esp_private/esp_pmu.h"
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#include "esp_private/esp_pmu.h"
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#define HP(state) (PMU_MODE_HP_ ## state)
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#define HP(state) (PMU_MODE_HP_ ## state)
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@ -218,6 +219,8 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
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{
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{
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assert(PMU_instance()->hal);
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assert(PMU_instance()->hal);
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lp_aon_hal_inform_wakeup_type(dslp);
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pmu_ll_hp_set_wakeup_enable(PMU_instance()->hal->dev, wakeup_opt);
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pmu_ll_hp_set_wakeup_enable(PMU_instance()->hal->dev, wakeup_opt);
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pmu_ll_hp_set_reject_enable(PMU_instance()->hal->dev, reject_opt);
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pmu_ll_hp_set_reject_enable(PMU_instance()->hal->dev, reject_opt);
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@ -262,7 +262,6 @@ static void touch_wakeup_prepare(void);
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static void gpio_deep_sleep_wakeup_prepare(void);
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static void gpio_deep_sleep_wakeup_prepare(void);
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#endif
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#endif
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#if !CONFIG_IDF_TARGET_ESP32H2
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#if SOC_RTC_FAST_MEM_SUPPORTED
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#if SOC_RTC_FAST_MEM_SUPPORTED
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#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
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#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
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static RTC_FAST_ATTR esp_deep_sleep_wake_stub_fn_t wake_stub_fn_handler = NULL;
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static RTC_FAST_ATTR esp_deep_sleep_wake_stub_fn_t wake_stub_fn_handler = NULL;
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@ -368,7 +367,6 @@ void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void)
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void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);
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void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);
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#endif // SOC_RTC_FAST_MEM_SUPPORTED
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#endif // SOC_RTC_FAST_MEM_SUPPORTED
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#endif // !CONFIG_IDF_TARGET_ESP32H2
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void esp_deep_sleep(uint64_t time_in_us)
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void esp_deep_sleep(uint64_t time_in_us)
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{
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{
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@ -626,7 +624,6 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
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#endif
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#endif
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}
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}
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#endif
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#endif
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misc_modules_sleep_prepare(deep_sleep);
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misc_modules_sleep_prepare(deep_sleep);
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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@ -666,7 +663,6 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
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if (periph_using_8m) {
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if (periph_using_8m) {
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sleep_flags |= RTC_SLEEP_DIG_USE_8M;
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sleep_flags |= RTC_SLEEP_DIG_USE_8M;
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}
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}
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// Enter sleep
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// Enter sleep
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esp_err_t result;
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esp_err_t result;
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#if SOC_PMU_SUPPORTED
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#if SOC_PMU_SUPPORTED
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@ -706,7 +702,6 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
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esp_sleep_isolate_digital_gpio();
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esp_sleep_isolate_digital_gpio();
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#endif
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#endif
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#if !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-6268
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#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
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#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
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esp_set_deep_sleep_wake_stub_default_entry();
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esp_set_deep_sleep_wake_stub_default_entry();
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// Enter Deep Sleep
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// Enter Deep Sleep
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@ -727,9 +722,6 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
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result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
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result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
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#endif
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#endif
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#endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
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#endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
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#else // !CONFIG_IDF_TARGET_ESP32H2
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result = ESP_OK;
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#endif // !CONFIG_IDF_TARGET_ESP32H2
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} else {
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} else {
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/* Wait cache idle in cache suspend to avoid cache load wrong data after spi io isolation */
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/* Wait cache idle in cache suspend to avoid cache load wrong data after spi io isolation */
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cache_hal_suspend(CACHE_TYPE_ALL);
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cache_hal_suspend(CACHE_TYPE_ALL);
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@ -840,6 +832,8 @@ void IRAM_ATTR esp_deep_sleep_start(void)
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if (esp_get_deep_sleep_wake_stub() == NULL) {
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if (esp_get_deep_sleep_wake_stub() == NULL) {
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esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
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esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
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}
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}
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// assert(0);
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#endif // SOC_RTC_FAST_MEM_SUPPORTED
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#endif // SOC_RTC_FAST_MEM_SUPPORTED
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// Decide which power domains can be powered down
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// Decide which power domains can be powered down
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@ -51,6 +51,7 @@ extern "C" {
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* LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY
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* LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY
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* LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC
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* LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC
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* LP_AON_STORE8_REG Store light sleep wake stub addr
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* LP_AON_STORE8_REG Store light sleep wake stub addr
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* LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
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*************************************************************************************
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*************************************************************************************
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*/
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*/
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@ -63,6 +64,7 @@ extern "C" {
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#define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG
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#define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG
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#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG
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#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG
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#define LIGHT_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG
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#define LIGHT_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG
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#define SLEEP_MODE_REG LP_AON_STORE9_REG
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#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
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#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
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@ -17,6 +17,8 @@ SECTIONS
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{
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{
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. = ALIGN(4);
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. = ALIGN(4);
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_rtc_fast_start = ABSOLUTE(.);
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_rtc_fast_start = ABSOLUTE(.);
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_rtc_text_start = ABSOLUTE(.);
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*(.rtc.entry.text)
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mapping[rtc_text]
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mapping[rtc_text]
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24
components/hal/esp32h2/include/hal/lp_aon_hal.h
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24
components/hal/esp32h2/include/hal/lp_aon_hal.h
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@ -0,0 +1,24 @@
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/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "hal/lp_aon_ll.h"
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#define rtc_hal_ext1_get_wakeup_status() lp_aon_hal_ext1_get_wakeup_status()
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#define rtc_hal_ext1_clear_wakeup_status() lp_aon_hal_ext1_clear_wakeup_status()
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#define rtc_hal_ext1_set_wakeup_pins(mask, mode) lp_aon_hal_ext1_set_wakeup_pins(mask, mode)
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#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_hal_ext1_clear_wakeup_pins()
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#define rtc_hal_ext1_get_wakeup_pins() lp_aon_hal_ext1_get_wakeup_pins()
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#define lp_aon_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
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#define lp_aon_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
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#define lp_aon_hal_ext1_set_wakeup_pins(mask, mode) lp_aon_ll_ext1_set_wakeup_pins(mask, mode)
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#define lp_aon_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
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#define lp_aon_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
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#define lp_aon_hal_inform_wakeup_type(dslp) lp_aon_ll_inform_wakeup_type(dslp)
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97
components/hal/esp32h2/include/hal/lp_aon_ll.h
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97
components/hal/esp32h2/include/hal/lp_aon_ll.h
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@ -0,0 +1,97 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for ESP32-C6 LP_AON register operations
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#pragma once
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#include <stdlib.h>
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#include "soc/soc.h"
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#include "soc/lp_aon_struct.h"
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#include "hal/misc.h"
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#include "esp32h2/rom/rtc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Get ext1 wakeup source status
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* @return The lower 8 bits of the returned value are the bitmap of
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* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
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*/
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static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
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{
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return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
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}
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/**
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* @brief Clear the ext1 wakeup source status
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*/
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static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
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}
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/**
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* @brief Set the wake-up LP_IO of the ext1 wake-up source
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* @param mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
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* @param mode 0: Wake the chip when all selected GPIOs go low
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* 1: Wake the chip when any of the selected GPIOs go high
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*/
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static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t mask, int mode)
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{
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uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
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wakeup_sel_mask |= mask;
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
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uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
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if (mode) {
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wakeup_level_mask |= mask;
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} else {
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wakeup_level_mask &= ~mask;
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
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}
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/**
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* @brief Clear all ext1 wakup-source setting
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*/
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static inline void lp_aon_ll_ext1_clear_wakeup_pins(void)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
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}
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/**
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* @brief Get ext1 wakeup source setting
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* @return The lower 8 bits of the returned value are the bitmap of
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* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
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*/
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static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
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{
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return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
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}
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/**
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* @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0].
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* Set the flag to inform
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* @param true: deepsleep false: lightsleep
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*/
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static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
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{
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if (dslp) {
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REG_SET_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
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} else {
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REG_CLR_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
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}
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}
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#ifdef __cplusplus
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}
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#endif
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@ -1075,6 +1075,10 @@ config SOC_PHY_DIG_REGS_MEM_SIZE
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int
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int
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default 21
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default 21
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config SOC_PM_SUPPORT_EXT1_WAKEUP
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bool
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default n
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config SOC_PM_SUPPORT_BT_WAKEUP
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config SOC_PM_SUPPORT_BT_WAKEUP
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bool
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bool
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default y
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default y
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#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
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#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
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/*-------------------------- Power Management CAPS ----------------------------*/
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/*-------------------------- Power Management CAPS ----------------------------*/
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#define SOC_PM_SUPPORT_EXT1_WAKEUP (0)
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#define SOC_PM_SUPPORT_BT_WAKEUP (1)
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#define SOC_PM_SUPPORT_BT_WAKEUP (1)
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#define SOC_PM_SUPPORT_CPU_PD (1)
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#define SOC_PM_SUPPORT_CPU_PD (1)
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#define SOC_PM_SUPPORT_MODEM_PD (1) /*!<modem includes BLE and 15.4 */
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#define SOC_PM_SUPPORT_MODEM_PD (1) /*!<modem includes BLE and 15.4 */
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