From 190ea15839d468901e4c12778808f4cf65ebf1bb Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 5 Aug 2024 15:02:35 +0800 Subject: [PATCH 1/3] feat(cache): supported cache panic on c5 --- .../port/soc/esp32c5/cache_err_int.c | 4 ++- components/hal/esp32c5/include/hal/cache_ll.h | 33 ++++++++++++------- .../mspi_test/main/test_cache_disabled.c | 2 +- 3 files changed, 25 insertions(+), 14 deletions(-) diff --git a/components/esp_system/port/soc/esp32c5/cache_err_int.c b/components/esp_system/port/soc/esp32c5/cache_err_int.c index a2d4320741..3f5eccb7a3 100644 --- a/components/esp_system/port/soc/esp32c5/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c5/cache_err_int.c @@ -61,10 +61,12 @@ void esp_cache_err_int_init(void) esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); - /* On the hardware side, start by clearing all the bits reponsible for cache access error */ + /* On the hardware side, start by clearing all the bits responsible for cache access error */ cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); /* Then enable cache access error interrupts. */ cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + /* Enable the fail tracer */ + cache_ll_l1_enable_fail_tracer(0, true); /* Enable the interrupts for cache error. */ ESP_INTR_ENABLE(ETS_CACHEERR_INUM); diff --git a/components/hal/esp32c5/include/hal/cache_ll.h b/components/hal/esp32c5/include/hal/cache_ll.h index 179a335988..01b0a0097a 100644 --- a/components/hal/esp32c5/include/hal/cache_ll.h +++ b/components/hal/esp32c5/include/hal/cache_ll.h @@ -10,6 +10,7 @@ #include #include "soc/cache_reg.h" +#include "soc/cache_struct.h" #include "soc/ext_mem_defs.h" #include "rom/cache.h" #include "hal/cache_types.h" @@ -24,9 +25,6 @@ extern "C" { #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 -#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4) -#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4) - #define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID #define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem #define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem @@ -34,6 +32,9 @@ extern "C" { #define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels #define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0) +#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x1f) + + /** * @brief Check if Cache auto preload is enabled or not. * @@ -290,45 +291,53 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32 return valid; } +/** + * Enable the Cache fail tracer + * + * @param cache_id cache ID + * @param en enable / disable + */ +static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en) +{ + CACHE.trace_ena.l1_cache_trace_ena = en; +} + /*------------------------------------------------------------------------------ * Interrupt *----------------------------------------------------------------------------*/ /** * @brief Enable Cache access error interrupt * - * @param cache_id Cache ID, not used on C3. For compabitlity + * @param cache_id Cache ID * @param mask Interrupt mask */ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) { - // TODO: [ESP32C5] IDF-8646 (inherit from C6) - SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask); + CACHE.l1_cache_acs_fail_int_ena.val |= mask; } /** * @brief Clear Cache access error interrupt status * - * @param cache_id Cache ID, not used on C3. For compabitlity + * @param cache_id Cache ID * @param mask Interrupt mask */ static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) { - // TODO: [ESP32C5] IDF-8646 (inherit from C6) - SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask); + CACHE.l1_cache_acs_fail_int_clr.val = mask; } /** * @brief Get Cache access error interrupt status * - * @param cache_id Cache ID, not used on C3. For compabitlity + * @param cache_id Cache ID * @param mask Interrupt mask * * @return Status mask */ static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) { - // TODO: [ESP32C5] IDF-8646 (inherit from C6) - return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask); + return CACHE.l1_cache_acs_fail_int_st.val & mask; } #ifdef __cplusplus diff --git a/components/spi_flash/test_apps/mspi_test/main/test_cache_disabled.c b/components/spi_flash/test_apps/mspi_test/main/test_cache_disabled.c index 649cc9a162..d92b876234 100644 --- a/components/spi_flash/test_apps/mspi_test/main/test_cache_disabled.c +++ b/components/spi_flash/test_apps/mspi_test/main/test_cache_disabled.c @@ -96,7 +96,7 @@ static void IRAM_ATTR cache_access_test_func(void* arg) #define CACHE_ERROR_REASON "Cache error,RTC_SW_CPU_RST" #elif CONFIG_IDF_TARGET_ESP32S3 #define CACHE_ERROR_REASON "Cache disabled,RTC_SW_CPU_RST" -#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#else #define CACHE_ERROR_REASON "Cache error,SW_CPU" #endif From 7231a6388b4b238977773b2163b6f1a1afa93b5f Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 5 Aug 2024 15:03:10 +0800 Subject: [PATCH 2/3] feat(cache): supported cache panic on c61 --- .../port/soc/esp32c61/cache_err_int.c | 4 ++- .../hal/esp32c61/include/hal/cache_ll.h | 33 ++++++++++++------- tools/test_apps/system/panic/pytest_panic.py | 8 ++--- 3 files changed, 28 insertions(+), 17 deletions(-) diff --git a/components/esp_system/port/soc/esp32c61/cache_err_int.c b/components/esp_system/port/soc/esp32c61/cache_err_int.c index d18659a58d..63b15acf28 100644 --- a/components/esp_system/port/soc/esp32c61/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c61/cache_err_int.c @@ -60,10 +60,12 @@ void esp_cache_err_int_init(void) esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); - /* On the hardware side, start by clearing all the bits reponsible for cache access error */ + /* On the hardware side, start by clearing all the bits responsible for cache access error */ cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); /* Then enable cache access error interrupts. */ cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + /* Enable the fail tracer */ + cache_ll_l1_enable_fail_tracer(0, true); /* Enable the interrupts for cache error. */ ESP_INTR_ENABLE(ETS_CACHEERR_INUM); diff --git a/components/hal/esp32c61/include/hal/cache_ll.h b/components/hal/esp32c61/include/hal/cache_ll.h index c321559495..b324b26792 100644 --- a/components/hal/esp32c61/include/hal/cache_ll.h +++ b/components/hal/esp32c61/include/hal/cache_ll.h @@ -10,6 +10,7 @@ #include #include "soc/cache_reg.h" +#include "soc/cache_struct.h" #include "soc/ext_mem_defs.h" #include "hal/cache_types.h" #include "hal/assert.h" @@ -23,9 +24,6 @@ extern "C" { #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 -#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4) -#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4) - #define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID #define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem #define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem @@ -33,6 +31,9 @@ extern "C" { #define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels #define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0) +#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x1f) + + /** * @brief Check if Cache auto preload is enabled or not. * @@ -289,45 +290,53 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32 return valid; } +/** + * Enable the Cache fail tracer + * + * @param cache_id cache ID + * @param en enable / disable + */ +static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en) +{ + CACHE.trace_ena.l1_cache_trace_ena = en; +} + /*------------------------------------------------------------------------------ * Interrupt *----------------------------------------------------------------------------*/ /** * @brief Enable Cache access error interrupt * - * @param cache_id Cache ID, not used on C3. For compabitlity + * @param cache_id Cache ID * @param mask Interrupt mask */ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) { - // TODO: [ESP32C61] IDF-9252 (inherit from C6) - SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask); + CACHE.l1_cache_acs_fail_int_ena.val |= mask; } /** * @brief Clear Cache access error interrupt status * - * @param cache_id Cache ID, not used on C3. For compabitlity + * @param cache_id Cache ID * @param mask Interrupt mask */ static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) { - // TODO: [ESP32C61] IDF-9252 (inherit from C6) - SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask); + CACHE.l1_cache_acs_fail_int_clr.val = mask; } /** * @brief Get Cache access error interrupt status * - * @param cache_id Cache ID, not used on C3. For compabitlity + * @param cache_id Cache ID * @param mask Interrupt mask * * @return Status mask */ static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) { - // TODO: [ESP32C61] IDF-9252 (inherit from C6) - return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask); + return CACHE.l1_cache_acs_fail_int_st.val & mask; } #ifdef __cplusplus diff --git a/tools/test_apps/system/panic/pytest_panic.py b/tools/test_apps/system/panic/pytest_panic.py index c6b26f3c98..1793c37719 100644 --- a/tools/test_apps/system/panic/pytest_panic.py +++ b/tools/test_apps/system/panic/pytest_panic.py @@ -299,14 +299,14 @@ def test_cache_error(dut: PanicTestDut, config: str, test_func_name: str) -> Non if dut.target in ['esp32c3', 'esp32c2']: dut.expect_gme('Cache error') dut.expect_exact('Cached memory region accessed while ibus or cache is disabled') - elif dut.target in ['esp32c6', 'esp32h2', 'esp32p4']: - dut.expect_gme('Cache error') - dut.expect_exact('Cache access error') elif dut.target in ['esp32s2']: # Cache error interrupt is not enabled, IDF-1558 dut.expect_gme('IllegalInstruction') - else: + elif dut.target in ['esp32', 'esp32s3']: dut.expect_gme('Cache disabled but cached memory region accessed') + else: + dut.expect_gme('Cache error') + dut.expect_exact('Cache access error') dut.expect_reg_dump(0) if dut.is_xtensa: dut.expect_backtrace() From 36f601b4596e44a95b43334e1d012ab6c37126f8 Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 8 Aug 2024 10:37:38 +0800 Subject: [PATCH 3/3] test(cache): cache panic test app --- .../test_apps/.build-test-rules.yml | 4 ++ .../test_apps/cache_panic/CMakeLists.txt | 8 +++ .../test_apps/cache_panic/README.md | 2 + .../test_apps/cache_panic/main/CMakeLists.txt | 6 ++ .../cache_panic/main/test_app_main.c | 55 +++++++++++++++++++ .../cache_panic}/main/test_cache_disabled.c | 34 +++++------- .../cache_panic/pytest_cache_panic_test.py | 10 ++++ .../test_apps/cache_panic/sdkconfig.defaults | 1 + .../test_apps/mspi_test/main/CMakeLists.txt | 3 +- 9 files changed, 100 insertions(+), 23 deletions(-) create mode 100644 components/esp_system/test_apps/cache_panic/CMakeLists.txt create mode 100644 components/esp_system/test_apps/cache_panic/README.md create mode 100644 components/esp_system/test_apps/cache_panic/main/CMakeLists.txt create mode 100644 components/esp_system/test_apps/cache_panic/main/test_app_main.c rename components/{spi_flash/test_apps/mspi_test => esp_system/test_apps/cache_panic}/main/test_cache_disabled.c (84%) create mode 100644 components/esp_system/test_apps/cache_panic/pytest_cache_panic_test.py create mode 100644 components/esp_system/test_apps/cache_panic/sdkconfig.defaults diff --git a/components/esp_system/test_apps/.build-test-rules.yml b/components/esp_system/test_apps/.build-test-rules.yml index 9985a538bd..27f3165dc1 100644 --- a/components/esp_system/test_apps/.build-test-rules.yml +++ b/components/esp_system/test_apps/.build-test-rules.yml @@ -1,5 +1,9 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps +components/esp_system/test_apps/cache_panic: + depends_components: + - spi_flash # esp_system is included by default + components/esp_system/test_apps/console: disable: - if: CONFIG_NAME == "serial_jtag_only" and SOC_USB_SERIAL_JTAG_SUPPORTED != 1 diff --git a/components/esp_system/test_apps/cache_panic/CMakeLists.txt b/components/esp_system/test_apps/cache_panic/CMakeLists.txt new file mode 100644 index 0000000000..fd5f8fb78a --- /dev/null +++ b/components/esp_system/test_apps/cache_panic/CMakeLists.txt @@ -0,0 +1,8 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +# "Trim" the build. Include the minimal set of components, main, and anything it depends on. +set(COMPONENTS main) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(cache_panic) diff --git a/components/esp_system/test_apps/cache_panic/README.md b/components/esp_system/test_apps/cache_panic/README.md new file mode 100644 index 0000000000..7b96141437 --- /dev/null +++ b/components/esp_system/test_apps/cache_panic/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_system/test_apps/cache_panic/main/CMakeLists.txt b/components/esp_system/test_apps/cache_panic/main/CMakeLists.txt new file mode 100644 index 0000000000..e0f128b847 --- /dev/null +++ b/components/esp_system/test_apps/cache_panic/main/CMakeLists.txt @@ -0,0 +1,6 @@ +set(srcs "test_cache_disabled.c" + "test_app_main.c") + +idf_component_register(SRCS ${srcs} + PRIV_REQUIRES unity spi_flash + WHOLE_ARCHIVE) diff --git a/components/esp_system/test_apps/cache_panic/main/test_app_main.c b/components/esp_system/test_apps/cache_panic/main/test_app_main.c new file mode 100644 index 0000000000..05944419cc --- /dev/null +++ b/components/esp_system/test_apps/cache_panic/main/test_app_main.c @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "esp_heap_caps.h" + +#define TEST_MEMORY_LEAK_THRESHOLD (-200) + +static size_t before_free_8bit; +static size_t before_free_32bit; + +static void check_leak(size_t before_free, size_t after_free, const char *type) +{ + ssize_t delta = after_free - before_free; + printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta); + TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak"); +} + +void setUp(void) +{ + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + +void tearDown(void) +{ + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + check_leak(before_free_8bit, after_free_8bit, "8BIT"); + check_leak(before_free_32bit, after_free_32bit, "32BIT"); +} + +void app_main(void) +{ + + // _____ _ _____ _ _______ _ + // / ____| | | | __ \ (_) |__ __| | | + // | | __ _ ___| |__ ___ | |__) |_ _ _ __ _ ___ | | ___ ___| |_ + // | | / _` |/ __| '_ \ / _ \ | ___/ _` | '_ \| |/ __| | |/ _ \/ __| __| + // | |___| (_| | (__| | | | __/ | | | (_| | | | | | (__ | | __/\__ \ |_ + // \_____\__,_|\___|_| |_|\___| |_| \__,_|_| |_|_|\___| |_|\___||___/\__| + + printf(" _____ _ _____ _ _______ _\n"); + printf(" / ____| | | | __ \\ (_) |__ __| | |\n"); + printf(" | | __ _ ___| |__ ___ | |__) |_ _ _ __ _ ___ | | ___ ___| |_\n"); + printf(" | | / _` |/ __| '_ \\ / _ \\ | ___/ _` | '_ \\| |/ __| | |/ _ \\/ __| __|\n"); + printf(" | |___| (_| | (__| | | | __/ | | | (_| | | | | | (__ | | __/\\__ \\ |_\n"); + printf(" \\_____\\__,_|\\___|_| |_|\\___| |_| \\__,_|_| |_|_|\\___| |_|\\___||___/\\__|\n"); + + unity_run_menu(); +} diff --git a/components/spi_flash/test_apps/mspi_test/main/test_cache_disabled.c b/components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c similarity index 84% rename from components/spi_flash/test_apps/mspi_test/main/test_cache_disabled.c rename to components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c index d92b876234..19fd6b9ef7 100644 --- a/components/spi_flash/test_apps/mspi_test/main/test_cache_disabled.c +++ b/components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c @@ -8,27 +8,21 @@ #include #include #include -#include -#include -#include - -#include -#include -#include -#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "unity.h" +#include "esp_attr.h" #include "esp_memory_utils.h" - #include "esp_private/cache_utils.h" -//TODO: IDF-6730, migrate this test to test_app - static QueueHandle_t result_queue; static IRAM_ATTR void cache_test_task(void *arg) { bool do_disable = (bool)arg; bool result; - if(do_disable) { + if (do_disable) { spi_flash_disable_interrupts_caches_and_other_cpu(); } result = spi_flash_cache_enabled(); @@ -36,7 +30,7 @@ static IRAM_ATTR void cache_test_task(void *arg) spi_flash_enable_interrupts_caches_and_other_cpu(); } - TEST_ASSERT( xQueueSendToBack(result_queue, &result, 0) ); + TEST_ASSERT(xQueueSendToBack(result_queue, &result, 0)); vTaskDelete(NULL); } @@ -44,16 +38,16 @@ TEST_CASE("spi_flash_cache_enabled() works on both CPUs", "[spi_flash][esp_flash { result_queue = xQueueCreate(1, sizeof(bool)); - for(int cpu = 0; cpu < CONFIG_FREERTOS_NUMBER_OF_CORES; cpu++) { - for(int disable = 0; disable <= 1; disable++) { + for (int cpu = 0; cpu < CONFIG_FREERTOS_NUMBER_OF_CORES; cpu++) { + for (int disable = 0; disable <= 1; disable++) { bool do_disable = disable; bool result; printf("Testing cpu %d disabled %d\n", cpu, do_disable); xTaskCreatePinnedToCore(cache_test_task, "cache_check_task", - 2048, (void *)do_disable, configMAX_PRIORITIES-1, NULL, cpu); + 2048, (void *)do_disable, configMAX_PRIORITIES - 1, NULL, cpu); - TEST_ASSERT( xQueueReceive(result_queue, &result, 2) ); + TEST_ASSERT(xQueueReceive(result_queue, &result, 2)); TEST_ASSERT_EQUAL(!do_disable, result); } } @@ -64,7 +58,6 @@ TEST_CASE("spi_flash_cache_enabled() works on both CPUs", "[spi_flash][esp_flash #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) - // This needs to sufficiently large array, otherwise it may end up in // DRAM (e.g. size <= 8 bytes && ARCH == RISCV) static const uint32_t s_in_rodata[8] = { 0x12345678, 0xfedcba98 }; @@ -100,13 +93,12 @@ static void IRAM_ATTR cache_access_test_func(void* arg) #define CACHE_ERROR_REASON "Cache error,SW_CPU" #endif - // These tests works properly if they resets the chip with the // "Cache disabled but cached memory region accessed" reason and the correct CPU is logged. static void invalid_access_to_cache_pro_cpu(void) { xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0); - vTaskDelay(1000/portTICK_PERIOD_MS); + vTaskDelay(1000 / portTICK_PERIOD_MS); } TEST_CASE_MULTIPLE_STAGES("invalid access to cache raises panic (PRO CPU)", "[spi_flash][reset="CACHE_ERROR_REASON"]", invalid_access_to_cache_pro_cpu, reset_after_invalid_cache); @@ -116,7 +108,7 @@ TEST_CASE_MULTIPLE_STAGES("invalid access to cache raises panic (PRO CPU)", "[sp static void invalid_access_to_cache_app_cpu(void) { xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 1); - vTaskDelay(1000/portTICK_PERIOD_MS); + vTaskDelay(1000 / portTICK_PERIOD_MS); } TEST_CASE_MULTIPLE_STAGES("invalid access to cache raises panic (APP CPU)", "[spi_flash][reset="CACHE_ERROR_REASON"]", invalid_access_to_cache_app_cpu, reset_after_invalid_cache); diff --git a/components/esp_system/test_apps/cache_panic/pytest_cache_panic_test.py b/components/esp_system/test_apps/cache_panic/pytest_cache_panic_test.py new file mode 100644 index 0000000000..f107e348a0 --- /dev/null +++ b/components/esp_system/test_apps/cache_panic/pytest_cache_panic_test.py @@ -0,0 +1,10 @@ +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import pytest +from pytest_embedded import Dut + + +@pytest.mark.supported_targets +@pytest.mark.generic +def test_cache_panic(dut: Dut) -> None: + dut.run_all_single_board_cases() diff --git a/components/esp_system/test_apps/cache_panic/sdkconfig.defaults b/components/esp_system/test_apps/cache_panic/sdkconfig.defaults new file mode 100644 index 0000000000..e4bfc208a5 --- /dev/null +++ b/components/esp_system/test_apps/cache_panic/sdkconfig.defaults @@ -0,0 +1 @@ +CONFIG_ESP_TASK_WDT_EN=n diff --git a/components/spi_flash/test_apps/mspi_test/main/CMakeLists.txt b/components/spi_flash/test_apps/mspi_test/main/CMakeLists.txt index 4e1e8bed59..10af23bbe6 100644 --- a/components/spi_flash/test_apps/mspi_test/main/CMakeLists.txt +++ b/components/spi_flash/test_apps/mspi_test/main/CMakeLists.txt @@ -1,5 +1,4 @@ -set(srcs "test_cache_disabled.c" - "test_out_of_bounds_write.c" +set(srcs "test_out_of_bounds_write.c" "test_read_write.c" "test_large_flash_writes.c" "test_app_main.c")