Merge branch 'feature/expose_rmt_channel_id' into 'master'

rmt: expose private API to get channel ID

Closes IDFGH-9206, IDF-6846, IDF-6810, and IDF-6783

See merge request espressif/esp-idf!22384
This commit is contained in:
morris 2023-02-16 16:54:46 +08:00
commit 4a604be7fd
14 changed files with 52 additions and 32 deletions

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@ -53,7 +53,7 @@ components/driver/test_apps/legacy_mcpwm_driver:
disable_test:
- if: IDF_TARGET in ["esp32h2"]
temporary: true
reason: cannot pass test, IDF-6812
reason: default group resolution changed, IDF-6812
components/driver/test_apps/legacy_pcnt_driver:
disable:
@ -78,10 +78,6 @@ components/driver/test_apps/legacy_timer_driver:
components/driver/test_apps/mcpwm:
disable:
- if: SOC_MCPWM_SUPPORTED != 1
disable_test:
- if: IDF_TARGET in ["esp32h2"]
temporary: true
reason: cannot pass test, IDF-6812
components/driver/test_apps/pulse_cnt:
disable:
@ -90,10 +86,6 @@ components/driver/test_apps/pulse_cnt:
components/driver/test_apps/rmt:
disable:
- if: SOC_RMT_SUPPORTED != 1
disable_test:
- if: IDF_TARGET in ["esp32h2"]
temporary: true
reason: cannot pass test, IDF-6810
components/driver/test_apps/rs485:
disable_test:

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@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// DO NOT USE THESE APIS IN YOUR APPLICATIONS
// The following APIs are for internal test.
#pragma once
#include "esp_err.h"
#include "driver/rmt_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Get the unique ID of RMT channel
*
* @param[in] channel RMT generic channel that created by `rmt_new_tx_channel()` or `rmt_new_rx_channel()`
* @param[out] ret_id The unique ID of RMT channel
* @return
* - ESP_OK: Get RMT channel ID successfully
* - ESP_ERR_INVALID_ARG: Get RMT channel ID failed because of invalid argument
* - ESP_FAIL: Get RMT channel ID failed because of other reasons
*/
esp_err_t rmt_get_channel_id(rmt_channel_handle_t channel, int *ret_id);
#ifdef __cplusplus
}
#endif

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@ -169,6 +169,13 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t
return ret;
}
esp_err_t rmt_get_channel_id(rmt_channel_handle_t channel, int *ret_id)
{
ESP_RETURN_ON_FALSE(channel && ret_id, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
*ret_id = channel->channel_id;
return ESP_OK;
}
esp_err_t rmt_apply_carrier(rmt_channel_handle_t channel, const rmt_carrier_config_t *config)
{
// specially, we allow config to be NULL, means to disable the carrier submodule

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@ -8,7 +8,7 @@ from pytest_embedded import Dut
@pytest.mark.esp32
@pytest.mark.esp32s3
@pytest.mark.esp32c6
# @pytest.mark.esp32h2 # IDF-6812
@pytest.mark.esp32h2
@pytest.mark.generic
@pytest.mark.parametrize(
'config',

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@ -1,2 +1,2 @@
CONFIG_FREERTOS_HZ=1000
CONFIG_ESP_TASK_WDT=n
CONFIG_ESP_TASK_WDT_INIT=n

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@ -465,7 +465,7 @@ static void test_rmt_multi_channels_trans(size_t channel0_mem_block_symbols, siz
{
#define TEST_RMT_CHANS 2
#define TEST_LED_NUM 1
#define TEST_STOP_TIME_NO_SYNCHRO_DELTA 250
#define TEST_STOP_TIME_NO_SYNCHRO_DELTA 300
#define TEST_STOP_TIME_SYNCHRO_DELTA 60
rmt_tx_channel_config_t tx_channel_cfg = {
.clk_src = RMT_CLK_SRC_DEFAULT,

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@ -10,7 +10,7 @@ from pytest_embedded import Dut
@pytest.mark.esp32s3
@pytest.mark.esp32c3
@pytest.mark.esp32c6
# @pytest.mark.esp32h2 IDF-6810
@pytest.mark.esp32h2
@pytest.mark.generic
@pytest.mark.parametrize(
'config',

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@ -1,6 +1,6 @@
choice ESP_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP_DEFAULT_CPU_FREQ_MHZ_64 if IDF_ENV_FPGA
default ESP_DEFAULT_CPU_FREQ_MHZ_32 if IDF_ENV_FPGA
default ESP_DEFAULT_CPU_FREQ_MHZ_96
help
CPU frequency to be set on application startup.

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@ -38,7 +38,6 @@ static void test_delay_task(void *p)
vTaskDelete(NULL);
}
#if !CONFIG_IDF_TARGET_ESP32H2 // IDF-6783
TEST_CASE("esp_rom_delay_us produces correct delay on CPUs", "[delay]")
{
int delay_ms = 50;
@ -61,7 +60,6 @@ TEST_CASE("esp_rom_delay_us produces correct delay on CPUs", "[delay]")
ref_clock_deinit();
vSemaphoreDelete(args.done);
}
#endif
TEST_CASE("vTaskDelay produces correct delay on CPUs", "[delay]")
{

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@ -142,9 +142,6 @@ examples/peripherals/rmt/onewire_ds18b20:
examples/peripherals/rmt/stepper_motor:
disable:
- if: SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP != 1
- if: IDF_TARGET == "esp32h2"
temporary: true
reason: wrong GPIO on esp32h2
examples/peripherals/sdio/host:
enable:
@ -213,12 +210,6 @@ examples/peripherals/timer_group:
disable:
- if: SOC_GPTIMER_SUPPORTED != 1
examples/peripherals/timer_group/gptimer:
disable_test:
- if: IDF_TARGET in ["esp32h2"]
temporary: true
reason: cannot pass target test IDF-6846
examples/peripherals/timer_group/gptimer_capture_hc_sr04:
disable:
- if: SOC_TIMER_SUPPORT_ETM != 1

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@ -1,5 +1,5 @@
| Supported Targets | ESP32-C6 | ESP32-S3 |
| ----------------- | -------- | -------- |
| Supported Targets | ESP32-C6 | ESP32-H2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- |
# RMT Based Stepper Motor Smooth Controller

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@ -12,9 +12,9 @@
#include "stepper_motor_encoder.h"
///////////////////////////////Change the following configurations according to your board//////////////////////////////
#define STEP_MOTOR_GPIO_EN 19
#define STEP_MOTOR_GPIO_DIR 20
#define STEP_MOTOR_GPIO_STEP 18
#define STEP_MOTOR_GPIO_EN 0
#define STEP_MOTOR_GPIO_DIR 2
#define STEP_MOTOR_GPIO_STEP 4
#define STEP_MOTOR_ENABLE_LEVEL 0 // DRV8825 is enabled on low level
#define STEP_MOTOR_SPIN_DIR_CLOCKWISE 0
#define STEP_MOTOR_SPIN_DIR_COUNTERCLOCKWISE !STEP_MOTOR_SPIN_DIR_CLOCKWISE

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@ -7,7 +7,7 @@ from pytest_embedded import Dut
@pytest.mark.esp32s3
@pytest.mark.esp32c6
# @pytest.mark.esp32h2 IDF-6808
@pytest.mark.esp32h2
@pytest.mark.generic
def test_stepper_motor_example(dut: Dut) -> None:
dut.expect_exact('example: Initialize EN + DIR GPIO')

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@ -6,7 +6,6 @@ from pytest_embedded import Dut
@pytest.mark.supported_targets
@pytest.mark.temp_skip_ci(targets=['esp32h2'], reason='test failed') # IDF-6846
@pytest.mark.generic
def test_gptimer_example(dut: Dut) -> None:
dut.expect_exact('Create timer handle', timeout=5)