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feat(esp_timer): Move esp_timer-related init steps into the component

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This commit is contained in:
Konstantin Kondrashov 2024-01-23 20:10:20 +02:00 committed by BOT
parent 10f14d5cca
commit 49ba674fb5
11 changed files with 80 additions and 50 deletions
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7
components/esp_system/startup_funcs.c
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@ -17,7 +17,6 @@
#include "spi_flash_mmap.h"
#include "esp_flash_internal.h"
#include "esp_newlib.h"
#include "esp_timer.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#include "esp_flash_encrypt.h"
@ -82,12 +81,6 @@ ESP_SYSTEM_INIT_FN(init_heap, CORE, BIT(0), 100)
return ESP_OK;
}
ESP_SYSTEM_INIT_FN(init_timer, CORE, BIT(0), 101)
{
esp_timer_early_init();
return ESP_OK;
}
ESP_SYSTEM_INIT_FN(init_psram_heap, CORE, BIT(0), 103)
{
#if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC)

6
components/esp_system/system_init_fn.txt
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@ -35,7 +35,7 @@ CORE: 100: init_heap in components/esp_system/startup_funcs.c on BIT(0)
# SEGGER_SYSVIEW relies on apptrace module
# apptrace module uses esp_timer_get_time to determine timeout conditions.
# esp_timer early initialization is required for esp_timer_get_time to work.
CORE: 101: init_timer in components/esp_system/startup_funcs.c on BIT(0)
CORE: 101: esp_timer_init_nonos in components/esp_timer/src/esp_timer_init.c on BIT(0)
CORE: 102: init_newlib in components/newlib/newlib_init.c on BIT(0)
CORE: 103: init_psram_heap in components/esp_system/startup_funcs.c on BIT(0)
@ -61,7 +61,7 @@ CORE: 170: init_xt_wdt in components/esp_system/startup_funcs.c on BIT(0)
########### SECONDARY startup stage ###########
# esp_timer has to be initialized early, since it is used by several other components
SECONDARY: 100: esp_timer_startup_init in components/esp_timer/src/esp_timer.c on ESP_TIMER_INIT_MASK
SECONDARY: 100: esp_timer_init_os in components/esp_timer/src/esp_timer.c on ESP_TIMER_INIT_MASK
# HW stack guard via assist-debug module.
SECONDARY: 101: esp_hw_stack_guard_init in components/esp_system/hw_stack_guard.c on ESP_SYSTEM_INIT_ALL_CORES
@ -89,7 +89,7 @@ SECONDARY: 204: init_coexist in components/esp_system/startup_funcs.c on BIT(0)
SECONDARY: 205: init_cxx_exceptions in components/esp_system/startup_funcs.c on BIT(0)
# usb_console needs to create an esp_timer at startup.
# This can be done only after esp_timer initialization (esp_timer_startup_init).
# This can be done only after esp_timer initialization (esp_timer_init_os).
SECONDARY: 220: esp_usb_console_init_restart_timer in components/esp_system/port/usb_console.c on BIT(0)
# usb_serial_jtag needs to create and acquire a PM lock at startup.

4
components/esp_timer/CMakeLists.txt
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@ -4,6 +4,7 @@ if(${target} STREQUAL "linux")
idf_component_register(INCLUDE_DIRS include)
else()
set(srcs "src/esp_timer.c"
"src/esp_timer_init.c"
"src/ets_timer_legacy.c"
"src/system_time.c"
"src/esp_timer_impl_common.c")
@ -21,4 +22,7 @@ else()
idf_component_register(SRCS "${srcs}"
INCLUDE_DIRS include
PRIV_INCLUDE_DIRS private_include)
# Forces the linker to include esp_timer_init.c
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_timer_init_include_func")
endif()

18
components/esp_timer/src/esp_timer.c
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@ -514,15 +514,6 @@ static IRAM_ATTR inline bool is_initialized(void)
return s_timer_task != NULL;
}
esp_err_t esp_timer_early_init(void)
{
esp_timer_impl_early_init();
#if CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER
esp_timer_impl_init_system_time();
#endif
return ESP_OK;
}
static esp_err_t init_timer_task(void)
{
esp_err_t err = ESP_OK;
@ -582,7 +573,14 @@ esp_err_t esp_timer_init(void)
#define ESP_TIMER_INIT_MASK ESP_SYSTEM_INIT_ALL_CORES
#endif // CONFIG_ESP_TIMER_ISR_AFFINITY_*
ESP_SYSTEM_INIT_FN(esp_timer_startup_init, SECONDARY, ESP_TIMER_INIT_MASK, 100)
/*
* This function initializes a task and ISR that esp_timer uses.
*
* We keep the esp_timer initialization function here to allow the linker
* to automatically include esp_timer_init_os if other components call esp_timer APIs.
* If no other code calls esp_timer APIs, then esp_timer_init_os will be skipped.
*/
ESP_SYSTEM_INIT_FN(esp_timer_init_os, SECONDARY, ESP_TIMER_INIT_MASK, 100)
{
return esp_timer_init();
}

35
components/esp_timer/src/esp_timer_init.c Normal file
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@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_private/startup_internal.h"
#include "esp_timer_impl.h"
#include "sdkconfig.h"
esp_err_t esp_timer_early_init(void)
{
esp_timer_impl_early_init();
#if CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER
esp_timer_impl_init_system_time();
#endif
return ESP_OK;
}
/*
* This function starts a timer, which is used by esp_timer
* to count time from the very start of the application.
*
* Another initialization function, esp_timer_init_nonos (which initializes ISR and task),
* is called only if other code calls the esp_timer API.
*/
ESP_SYSTEM_INIT_FN(esp_timer_init_nonos, CORE, BIT(0), 101)
{
return esp_timer_early_init();
}
void esp_timer_init_include_func(void)
{
// Hook to force the linker to include this file
}

10
tools/test_apps/system/esp_intr_dump/expected_output/esp32.txt
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@ -3,17 +3,17 @@ CPU 0 interrupt status:
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: RTC_CORE
3 1 Level Used: TG0_LACT_LEVEL
3 1 Level Used: FROM_CPU0
4 1 Level Reserved
5 1 Level Reserved
6 1 Level Reserved
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Used: FROM_CPU0
9 1 Level Used: TG0_WDT_LEVEL
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Used: TG0_WDT_LEVEL
13 1 Level Used: UART0
12 1 Level Used: UART0
13 1 Level Free
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
@ -66,5 +66,5 @@ CPU 1 interrupt status:
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
Interrupts available for general use: 17
Interrupts available for general use: 18
Shared interrupts: 0

12
tools/test_apps/system/esp_intr_dump/expected_output/esp32c3.txt
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@ -3,14 +3,14 @@ CPU 0 interrupt status:
0 * * Reserved
1 * * Reserved
2 1 Level Used: RTC_CORE
3 1 Level Used: SYSTIMER_TARGET2_EDGE
4 1 Level Used: FROM_CPU_INTR0
3 1 Level Used: FROM_CPU_INTR0
4 1 Level Used: SYSTIMER_TARGET0_EDGE
5 * * Reserved
6 * * Reserved
7 1 Level Used: SYSTIMER_TARGET0_EDGE
7 1 Level Used: TG0_WDT_LEVEL
8 * * Reserved
9 1 Level Used: TG0_WDT_LEVEL
10 1 Level Used: UART0
9 1 Level Used: UART0
10 * * Free
11 * * Free
12 * * Free
13 * * Free
@ -32,5 +32,5 @@ CPU 0 interrupt status:
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 17
Interrupts available for general use: 18
Shared interrupts: 0

12
tools/test_apps/system/esp_intr_dump/expected_output/esp32c6.txt
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@ -9,11 +9,11 @@ CPU 0 interrupt status:
6 * * Reserved
7 * * Reserved
8 * * Reserved
9 1 Level Used: SYSTIMER_TARGET2
10 1 Level Used: CPU_FROM_CPU_0
11 1 Level Used: SYSTIMER_TARGET0
12 1 Level Used: TG0_WDT
13 1 Level Used: UART0
9 1 Level Used: CPU_FROM_CPU_0
10 1 Level Used: SYSTIMER_TARGET0
11 1 Level Used: TG0_WDT
12 1 Level Used: UART0
13 * * Free
14 * * Free
15 * * Free
16 * * Free
@ -32,5 +32,5 @@ CPU 0 interrupt status:
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 15
Interrupts available for general use: 16
Shared interrupts: 0

12
tools/test_apps/system/esp_intr_dump/expected_output/esp32h2.txt
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@ -9,11 +9,11 @@ CPU 0 interrupt status:
6 * * Reserved
7 * * Reserved
8 * * Reserved
9 1 Level Used: SYSTIMER_TARGET2
10 1 Level Used: CPUFROM_CPU_0
11 1 Level Used: SYSTIMER_TARGET0
12 1 Level Used: TG0_WDT
13 1 Level Used: UART0
9 1 Level Used: CPUFROM_CPU_0
10 1 Level Used: SYSTIMER_TARGET0
11 1 Level Used: TG0_WDT
12 1 Level Used: UART0
13 * * Free
14 * * Free
15 * * Free
16 * * Free
@ -32,5 +32,5 @@ CPU 0 interrupt status:
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 15
Interrupts available for general use: 16
Shared interrupts: 0

2
tools/test_apps/system/esp_intr_dump/expected_output/esp32s2.txt
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@ -10,7 +10,7 @@ CPU 0 interrupt status:
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Used: TG0_WDT_LEVEL
10 1 Edge Used: SYSTIMER_TARGET2
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Used: UART0
13 1 Level Free

12
tools/test_apps/system/esp_intr_dump/expected_output/esp32s3.txt
View File

@ -3,21 +3,21 @@ CPU 0 interrupt status:
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: RTC_CORE
3 1 Level Used: SYSTIMER_TARGET2
3 1 Level Used: FROM_CPU_INTR0
4 1 Level Reserved
5 1 Level Reserved
6 1 Level CPU-internal
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Used: FROM_CPU_INTR0
9 1 Level Used: SYSTIMER_TARGET0
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Used: SYSTIMER_TARGET0
13 1 Level Used: TG0_WDT_LEVEL
12 1 Level Used: TG0_WDT_LEVEL
13 1 Level Used: UART0
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
17 1 Level Used: UART0
17 1 Level Free
18 1 Level Free
19 2 Level Free
20 2 Level Free
@ -66,5 +66,5 @@ CPU 1 interrupt status:
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
Interrupts available for general use: 15
Interrupts available for general use: 16
Shared interrupts: 0