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riscv: Adds support for returning from exception handler
This commit is contained in:
Alexey Gerenkov
parent
300d67411a
commit
46a98fb8d1
@ -23,37 +23,41 @@
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.equ panic_from_exception, xt_unhandled_exception
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.equ panic_from_isr, panicHandler
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.macro save_regs
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addi sp, sp, -CONTEXT_SIZE
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sw ra, RV_STK_RA(sp)
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sw tp, RV_STK_TP(sp)
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sw t0, RV_STK_T0(sp)
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sw t1, RV_STK_T1(sp)
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sw t2, RV_STK_T2(sp)
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sw s0, RV_STK_S0(sp)
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sw s1, RV_STK_S1(sp)
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sw a0, RV_STK_A0(sp)
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sw a1, RV_STK_A1(sp)
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sw a2, RV_STK_A2(sp)
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sw a3, RV_STK_A3(sp)
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sw a4, RV_STK_A4(sp)
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sw a5, RV_STK_A5(sp)
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sw a6, RV_STK_A6(sp)
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sw a7, RV_STK_A7(sp)
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sw s2, RV_STK_S2(sp)
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sw s3, RV_STK_S3(sp)
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sw s4, RV_STK_S4(sp)
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sw s5, RV_STK_S5(sp)
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sw s6, RV_STK_S6(sp)
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sw s7, RV_STK_S7(sp)
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sw s8, RV_STK_S8(sp)
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sw s9, RV_STK_S9(sp)
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sw s10, RV_STK_S10(sp)
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sw s11, RV_STK_S11(sp)
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sw t3, RV_STK_T3(sp)
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sw t4, RV_STK_T4(sp)
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sw t5, RV_STK_T5(sp)
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sw t6, RV_STK_T6(sp)
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/* Macro which first allocates space on the stack to save general
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* purpose registers, and then save them. GP register is excluded.
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* The default size allocated on the stack is CONTEXT_SIZE, but it
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* can be overridden. */
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.macro save_general_regs cxt_size=CONTEXT_SIZE
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addi sp, sp, -\cxt_size
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sw ra, RV_STK_RA(sp)
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sw tp, RV_STK_TP(sp)
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sw t0, RV_STK_T0(sp)
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sw t1, RV_STK_T1(sp)
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sw t2, RV_STK_T2(sp)
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sw s0, RV_STK_S0(sp)
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sw s1, RV_STK_S1(sp)
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sw a0, RV_STK_A0(sp)
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sw a1, RV_STK_A1(sp)
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sw a2, RV_STK_A2(sp)
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sw a3, RV_STK_A3(sp)
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sw a4, RV_STK_A4(sp)
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sw a5, RV_STK_A5(sp)
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sw a6, RV_STK_A6(sp)
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sw a7, RV_STK_A7(sp)
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sw s2, RV_STK_S2(sp)
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sw s3, RV_STK_S3(sp)
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sw s4, RV_STK_S4(sp)
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sw s5, RV_STK_S5(sp)
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sw s6, RV_STK_S6(sp)
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sw s7, RV_STK_S7(sp)
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sw s8, RV_STK_S8(sp)
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sw s9, RV_STK_S9(sp)
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sw s10, RV_STK_S10(sp)
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sw s11, RV_STK_S11(sp)
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sw t3, RV_STK_T3(sp)
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sw t4, RV_STK_T4(sp)
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sw t5, RV_STK_T5(sp)
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sw t6, RV_STK_T6(sp)
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.endm
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.macro save_mepc
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@ -61,37 +65,40 @@
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sw t0, RV_STK_MEPC(sp)
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.endm
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.macro restore_regs
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lw ra, RV_STK_RA(sp)
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lw tp, RV_STK_TP(sp)
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lw t0, RV_STK_T0(sp)
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lw t1, RV_STK_T1(sp)
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lw t2, RV_STK_T2(sp)
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lw s0, RV_STK_S0(sp)
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lw s1, RV_STK_S1(sp)
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lw a0, RV_STK_A0(sp)
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lw a1, RV_STK_A1(sp)
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lw a2, RV_STK_A2(sp)
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lw a3, RV_STK_A3(sp)
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lw a4, RV_STK_A4(sp)
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lw a5, RV_STK_A5(sp)
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lw a6, RV_STK_A6(sp)
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lw a7, RV_STK_A7(sp)
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lw s2, RV_STK_S2(sp)
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lw s3, RV_STK_S3(sp)
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lw s4, RV_STK_S4(sp)
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lw s5, RV_STK_S5(sp)
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lw s6, RV_STK_S6(sp)
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lw s7, RV_STK_S7(sp)
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lw s8, RV_STK_S8(sp)
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lw s9, RV_STK_S9(sp)
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lw s10, RV_STK_S10(sp)
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lw s11, RV_STK_S11(sp)
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lw t3, RV_STK_T3(sp)
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lw t4, RV_STK_T4(sp)
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lw t5, RV_STK_T5(sp)
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lw t6, RV_STK_T6(sp)
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addi sp, sp, CONTEXT_SIZE
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/* Restore the general purpose registers (excluding gp) from the context on
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* the stack. The context is then deallocated. The default size is CONTEXT_SIZE
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* but it can be overriden. */
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.macro restore_general_regs cxt_size=CONTEXT_SIZE
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lw ra, RV_STK_RA(sp)
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lw tp, RV_STK_TP(sp)
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lw t0, RV_STK_T0(sp)
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lw t1, RV_STK_T1(sp)
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lw t2, RV_STK_T2(sp)
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lw s0, RV_STK_S0(sp)
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lw s1, RV_STK_S1(sp)
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lw a0, RV_STK_A0(sp)
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lw a1, RV_STK_A1(sp)
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lw a2, RV_STK_A2(sp)
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lw a3, RV_STK_A3(sp)
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lw a4, RV_STK_A4(sp)
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lw a5, RV_STK_A5(sp)
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lw a6, RV_STK_A6(sp)
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lw a7, RV_STK_A7(sp)
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lw s2, RV_STK_S2(sp)
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lw s3, RV_STK_S3(sp)
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lw s4, RV_STK_S4(sp)
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lw s5, RV_STK_S5(sp)
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lw s6, RV_STK_S6(sp)
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lw s7, RV_STK_S7(sp)
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lw s8, RV_STK_S8(sp)
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lw s9, RV_STK_S9(sp)
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lw s10, RV_STK_S10(sp)
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lw s11, RV_STK_S11(sp)
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lw t3, RV_STK_T3(sp)
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lw t4, RV_STK_T4(sp)
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lw t5, RV_STK_T5(sp)
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lw t6, RV_STK_T6(sp)
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addi sp,sp, \cxt_size
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.endm
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.macro restore_mepc
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@ -141,40 +148,17 @@ _vector_table:
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/* Exception handler.*/
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.type _panic_handler, @function
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_panic_handler:
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addi sp, sp, -RV_STK_FRMSZ /* allocate space on stack to store necessary registers */
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/* save general registers */
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sw ra, RV_STK_RA(sp)
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sw gp, RV_STK_GP(sp)
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sw tp, RV_STK_TP(sp)
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sw t0, RV_STK_T0(sp)
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sw t1, RV_STK_T1(sp)
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sw t2, RV_STK_T2(sp)
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sw s0, RV_STK_S0(sp)
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sw s1, RV_STK_S1(sp)
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sw a0, RV_STK_A0(sp)
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sw a1, RV_STK_A1(sp)
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sw a2, RV_STK_A2(sp)
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sw a3, RV_STK_A3(sp)
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sw a4, RV_STK_A4(sp)
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sw a5, RV_STK_A5(sp)
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sw a6, RV_STK_A6(sp)
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sw a7, RV_STK_A7(sp)
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sw s2, RV_STK_S2(sp)
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sw s3, RV_STK_S3(sp)
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sw s4, RV_STK_S4(sp)
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sw s5, RV_STK_S5(sp)
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sw s6, RV_STK_S6(sp)
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sw s7, RV_STK_S7(sp)
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sw s8, RV_STK_S8(sp)
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sw s9, RV_STK_S9(sp)
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sw s10, RV_STK_S10(sp)
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sw s11, RV_STK_S11(sp)
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sw t3, RV_STK_T3(sp)
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sw t4, RV_STK_T4(sp)
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sw t5, RV_STK_T5(sp)
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sw t6, RV_STK_T6(sp)
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/* Allocate space on the stack and store general purpose registers */
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save_general_regs RV_STK_FRMSZ
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/* As gp register is not saved by the macro, save it here */
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sw gp, RV_STK_GP(sp)
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/* Same goes for the SP value before trapping */
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addi t0, sp, RV_STK_FRMSZ /* restore sp with the value when trap happened */
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sw t0, RV_STK_SP(sp)
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/* Save CSRs */
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csrr t0, mepc
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sw t0, RV_STK_MEPC(sp)
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csrr t0, mstatus
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@ -198,17 +182,31 @@ _panic_handler:
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li t0, 0x80000000
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bgeu a1, t0, _call_panic_handler
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sw a1, RV_STK_MCAUSE(sp)
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/* exception_from_panic never returns */
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j panic_from_exception
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jal panic_from_exception
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/* We arrive here if the exception handler has returned. */
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j _return_from_exception
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_call_panic_handler:
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/* Remove highest bit from mcause (a1) register and save it in the
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* structure */
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not t0, t0
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and a1, a1, t0
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sw a1, RV_STK_MCAUSE(sp)
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/* exception_from_isr never returns */
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j panic_from_isr
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.size panic_from_isr, .-panic_from_isr
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jal panic_from_isr
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/* We arrive here if the exception handler has returned. This means that
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* the exception was handled, and the execution flow should resume.
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* Restore the registers and return from the exception.
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*/
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_return_from_exception:
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restore_mepc
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/* MTVEC and SP are assumed to be unmodified.
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* MSTATUS, MHARTID, MTVAL are read-only and not restored.
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*/
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lw gp, RV_STK_GP(sp)
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restore_general_regs RV_STK_FRMSZ
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mret
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.size _panic_handler, .-_panic_handler
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/* This is the interrupt handler.
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* It saves the registers on the stack,
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@ -220,7 +218,7 @@ _call_panic_handler:
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.type _interrupt_handler, @function
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_interrupt_handler:
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/* entry */
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save_regs
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save_general_regs
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save_mepc
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/* Though it is not necessary we save GP and SP here.
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@ -306,7 +304,7 @@ _interrupt_handler:
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csrw mcause, s1
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csrw mstatus, s2
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restore_mepc
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restore_regs
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restore_general_regs
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/* exit, this will also re-enable the interrupts */
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mret
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