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feat(uart): add RCC atomic block to uart/lp-uart peripheral

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This commit is contained in:
gaoxu 2023-09-14 09:23:20 +08:00
parent c7afa0dcef
commit 4541ad134d
21 changed files with 643 additions and 168 deletions
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1
components/bootloader_support/src/bootloader_console.c
View File

@ -77,6 +77,7 @@ void bootloader_console_init(void)
#if ESP_ROM_UART_CLK_IS_XTAL
clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ; // From esp32-s3 on, UART clk source is selected to XTAL in ROM
#endif
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_ATOMIC_ENV
esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
}
#endif // CONFIG_ESP_CONSOLE_UART

35
components/driver/include/esp_private/uart_private.h Normal file
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@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "sdkconfig.h"
#include "esp_private/periph_ctrl.h"
#ifdef __cplusplus
extern "C" {
#endif
#if (SOC_UART_LP_NUM >= 1)
#define LP_UART_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#endif
#if CONFIG_IDF_TARGET_ESP32P4
#define UART_SCLK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define UART_SCLK_ATOMIC()
#endif
#if SOC_RCC_IS_INDEPENDENT
#define UART_CLK_ATOMIC()
#else
#define UART_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#endif
#ifdef __cplusplus
}
#endif

62
components/driver/uart/uart.c
View File

@ -26,6 +26,7 @@
#include "driver/gpio.h"
#include "driver/rtc_io.h"
#include "driver/uart_select.h"
#include "esp_private/uart_private.h"
#include "esp_private/periph_ctrl.h"
#include "esp_clk_tree.h"
#include "sdkconfig.h"
@ -177,22 +178,32 @@ static void uart_module_enable(uart_port_t uart_num)
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
if (uart_context[uart_num].hw_enabled != true) {
if (uart_num < SOC_UART_HP_NUM) {
periph_module_enable(uart_periph_signal[uart_num].module);
UART_CLK_ATOMIC() {
uart_ll_enable_bus_clock(uart_num, true);
}
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
// Workaround for ESP32C3/S3: enable core reset before enabling uart module clock to prevent uart output
// garbage value.
#if SOC_UART_REQUIRE_CORE_RESET
uart_hal_set_reset_core(&(uart_context[uart_num].hal), true);
periph_module_reset(uart_periph_signal[uart_num].module);
uart_hal_set_reset_core(&(uart_context[uart_num].hal), false);
UART_SCLK_ATOMIC(){
uart_hal_set_reset_core(&(uart_context[uart_num].hal), true);
}
UART_CLK_ATOMIC() {
uart_ll_reset_register(uart_num);
}
UART_SCLK_ATOMIC(){
uart_hal_set_reset_core(&(uart_context[uart_num].hal), false);
}
#else
periph_module_reset(uart_periph_signal[uart_num].module);
UART_CLK_ATOMIC() {
uart_ll_reset_register(uart_num);
}
#endif
}
}
#if (SOC_UART_LP_NUM >= 1)
else {
PERIPH_RCC_ATOMIC() {
LP_UART_CLK_ATOMIC() {
lp_uart_ll_enable_bus_clock(uart_num - SOC_UART_HP_NUM, true);
lp_uart_ll_reset_register(uart_num - SOC_UART_HP_NUM);
}
@ -208,11 +219,13 @@ static void uart_module_disable(uart_port_t uart_num)
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
if (uart_context[uart_num].hw_enabled != false) {
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) {
periph_module_disable(uart_periph_signal[uart_num].module);
UART_CLK_ATOMIC() {
uart_ll_enable_bus_clock(uart_num, false);
}
}
#if (SOC_UART_LP_NUM >= 1)
else if (uart_num >= SOC_UART_HP_NUM) {
PERIPH_RCC_ATOMIC() {
LP_UART_CLK_ATOMIC() {
lp_uart_ll_enable_bus_clock(uart_num - SOC_UART_HP_NUM, false);
}
}
@ -292,7 +305,9 @@ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate)
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(src_clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "Invalid src_clk");
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq);
UART_SCLK_ATOMIC() {
uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq);
}
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
return ESP_OK;
}
@ -649,13 +664,20 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
ESP_RETURN_ON_FALSE((rts_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(rts_io_num))), ESP_FAIL, UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), ESP_FAIL, UART_TAG, "cts_io_num error");
}
#if (SOC_UART_LP_NUM >= 1 && !SOC_LP_GPIO_MATRIX_SUPPORTED)
else { // LP_UART has its fixed IOs
#if (SOC_UART_LP_NUM >= 1)
else { // LP_UART IO check
const uart_periph_sig_t *pins = uart_periph_signal[uart_num].pins;
#if !SOC_LP_GPIO_MATRIX_SUPPORTED
// LP_UART has its fixed IOs
ESP_RETURN_ON_FALSE((tx_io_num < 0 || (tx_io_num == pins[SOC_UART_TX_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "tx_io_num error");
ESP_RETURN_ON_FALSE((rx_io_num < 0 || (rx_io_num == pins[SOC_UART_RX_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "rx_io_num error");
ESP_RETURN_ON_FALSE((rts_io_num < 0 || (rts_io_num == pins[SOC_UART_RTS_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cts_io_num < 0 || (cts_io_num == pins[SOC_UART_CTS_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "cts_io_num error");
#else // SOC_LP_GPIO_MATRIX_SUPPORTED
// LP_UART IOs can be routed any LP_IOs
//TODO: IDF-7815, check for LP_IO 0~15
#endif // SOC_LP_GPIO_MATRIX_SUPPORTED
}
#endif
@ -663,8 +685,8 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
if (tx_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, tx_io_num, SOC_UART_TX_PIN_IDX)) {
if (uart_num < SOC_UART_HP_NUM) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
gpio_set_level(tx_io_num, 1);
esp_rom_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX), 0, 0);
gpio_set_level(tx_io_num, 1);
esp_rom_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX), 0, 0);
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
else {
@ -672,7 +694,7 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
rtc_gpio_set_direction(tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
rtc_gpio_init(tx_io_num);
rtc_gpio_iomux_func_sel(tx_io_num, 1);
LP_GPIO.func10_out_sel_cfg.reg_gpio_func10_out_sel = uart_periph_signal[uart_num].pins[SOC_UART_TX_PIN_IDX].signal;
LP_GPIO.func10_out_sel_cfg.reg_gpio_func10_out_sel = uart_periph_signal[uart_num].pins[SOC_UART_TX_PIN_IDX].signal;
}
#endif
}
@ -708,7 +730,7 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
rtc_gpio_set_direction(rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
rtc_gpio_init(rts_io_num);
rtc_gpio_iomux_func_sel(rts_io_num, 1);
LP_GPIO.func10_out_sel_cfg.reg_gpio_func12_out_sel = uart_periph_signal[uart_num].pins[SOC_UART_RTS_PIN_IDX].signal;
LP_GPIO.func10_out_sel_cfg.reg_gpio_func12_out_sel = uart_periph_signal[uart_num].pins[SOC_UART_RTS_PIN_IDX].signal;
}
#endif
}
@ -794,16 +816,20 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_init(&(uart_context[uart_num].hal), uart_num);
if (uart_num < SOC_UART_HP_NUM) {
uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
UART_SCLK_ATOMIC() {
uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
}
}
#if (SOC_UART_LP_NUM >= 1)
else {
PERIPH_RCC_ATOMIC() {
LP_UART_CLK_ATOMIC() {
lp_uart_ll_set_source_clk(uart_context[uart_num].hal.dev, (soc_periph_lp_uart_clk_src_t)uart_sclk_sel);
}
}
#endif
uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq);
UART_SCLK_ATOMIC() {
uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq);
}
uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity);
uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), uart_config->data_bits);
uart_hal_set_stop_bits(&(uart_context[uart_num].hal), uart_config->stop_bits);

2
components/esp_hw_support/port/esp32p4/esp_clk_tree.c
View File

@ -26,7 +26,7 @@ uint32_t *freq_value)
clk_src_freq = 40 * MHZ;
break;
case SOC_MOD_CLK_XTAL_D2:
clk_src_freq = (40* MHZ) >> 1;
clk_src_freq = (40 * MHZ) >> 1;
break;
case SOC_MOD_CLK_LP_PLL:
clk_src_freq = 8 * MHZ;

15
components/esp_pm/pm_impl.c
View File

@ -17,6 +17,7 @@
#include "esp_cpu.h"
#include "esp_private/crosscore_int.h"
#include "esp_private/uart_private.h"
#include "soc/rtc.h"
#include "hal/uart_ll.h"
@ -42,6 +43,7 @@
#include "esp_private/sleep_cpu.h"
#include "esp_private/sleep_gpio.h"
#include "esp_private/sleep_modem.h"
#include "esp_private/periph_ctrl.h"
#include "esp_sleep.h"
#include "sdkconfig.h"
@ -736,14 +738,19 @@ void esp_pm_impl_init(void)
#else
#error "No UART clock source is aware of DFS"
#endif // SOC_UART_SUPPORT_xxx
while(!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM)));
while(!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM))) {
;
}
/* When DFS is enabled, override system setting and use REFTICK as UART clock source */
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
UART_SCLK_ATOMIC() {
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
}
uint32_t sclk_freq;
esp_err_t err = uart_get_sclk_freq(clk_source, &sclk_freq);
assert(err == ESP_OK);
uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
UART_SCLK_ATOMIC() {
uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
}
#endif // CONFIG_ESP_CONSOLE_UART
#ifdef CONFIG_PM_TRACE

6
components/esp_rom/patches/esp_rom_uart.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -25,6 +25,10 @@ IRAM_ATTR void esp_rom_uart_tx_wait_idle(uint8_t uart_no)
IRAM_ATTR void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_hz, uint32_t baud_rate)
{
// To avoid build errors about __DECLARE_RCC_ATOMIC_ENV
#if !BOOTLOADER_BUILD
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
#endif
uart_ll_set_baudrate(UART_LL_GET_HW(uart_no), baud_rate, clock_hz);
}

13
components/esp_system/port/cpu_start.c
View File

@ -91,6 +91,7 @@
#include "esp_cpu.h"
#include "esp_private/esp_clk.h"
#include "spi_flash_mmap.h"
#include "esp_private/periph_ctrl.h"
#if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX
#include "esp_private/trax.h"
@ -143,6 +144,13 @@ static volatile bool s_cpu_inited[SOC_CPU_CORES_NUM] = { false };
static volatile bool s_resume_cores;
#endif
#if CONFIG_IDF_TARGET_ESP32P4
#define UART_START_SCLK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
// #define UART_START_SCLK_ATOMIC() for(int i = 1, __DECLARE_RCC_ATOMIC_ENV; i < 1; i--)
#define UART_START_SCLK_ATOMIC() int __DECLARE_RCC_ATOMIC_ENV;
#endif
static void core_intr_matrix_clear(void)
{
uint32_t core_id = esp_cpu_get_core_id();
@ -682,7 +690,10 @@ void IRAM_ATTR call_start_cpu0(void)
clock_hz = esp_clk_xtal_freq(); // From esp32-s3 on, UART clock source is selected to XTAL in ROM
#endif
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
UART_START_SCLK_ATOMIC() {
(void) __DECLARE_RCC_ATOMIC_ENV; // To avoid build warning about __DECLARE_RCC_ATOMIC_ENV defined but not used on P4
esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
}
#endif
#endif

10
components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c
View File

@ -26,6 +26,7 @@
#include "esp_rom_sys.h"
#include "esp_timer.h"
#include "esp_private/esp_clk.h"
#include "esp_private/uart_private.h"
#include "esp_random.h"
#include "nvs_flash.h"
#include "nvs.h"
@ -229,11 +230,14 @@ TEST_CASE("light sleep and frequency switching", "[deepsleep]")
#elif SOC_UART_SUPPORT_XTAL_CLK
clk_source = UART_SCLK_XTAL;
#endif
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
UART_SCLK_ATOMIC() {
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
}
uint32_t sclk_freq;
TEST_ESP_OK(uart_get_sclk_freq(clk_source, &sclk_freq));
uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
UART_SCLK_ATOMIC() {
uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
}
#endif
rtc_cpu_freq_config_t config_xtal, config_default;

61
components/hal/esp32/include/hal/uart_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -15,6 +15,7 @@
#include "esp_attr.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/dport_reg.h"
#include "hal/uart_types.h"
#ifdef __cplusplus
@ -55,6 +56,64 @@ typedef enum {
UART_INTR_CMD_CHAR_DET = (0x1<<18),
} uart_intr_t;
/**
* @brief Enable the bus clock for uart
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable true to enable, false to disable
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
uint32_t reg_val = DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
switch (uart_num)
{
case 0:
reg_val = reg_val & (~DPORT_UART_CLK_EN);
reg_val = reg_val | (enable << 2);
break;
case 1:
reg_val = reg_val & (~DPORT_UART1_CLK_EN);
reg_val = reg_val | (enable << 5);
break;
case 2:
reg_val = reg_val & (~DPORT_UART2_CLK_EN);
reg_val = reg_val | (enable << 23);
break;
default:
abort();
break;
}
DPORT_WRITE_PERI_REG(DPORT_PERIP_CLK_EN_REG, reg_val);
}
#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset UART module
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num)
{
case 0:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
break;
case 1:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
break;
case 2:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
break;
default:
abort();
break;
}
}
// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Set the UART source clock.
*

50
components/hal/esp32c2/include/hal/uart_ll.h
View File

@ -11,10 +11,11 @@
#include <stdlib.h>
#include "hal/uart_types.h"
#include "hal/misc.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/clk_tree_defs.h"
#include "hal/misc.h"
#include "soc/system_struct.h"
#include "esp_attr.h"
#ifdef __cplusplus
@ -97,6 +98,53 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
hw->clk_conf.tx_sclk_en = 0;
}
/**
* @brief Enable the bus clock for uart
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable true to enable, false to disable
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
switch (uart_num)
{
case 0:
SYSTEM.perip_clk_en0.uart_clk_en = enable;
break;
case 1:
SYSTEM.perip_clk_en0.uart1_clk_en = enable;
break;
default:
abort();
break;
}
}
// SYSTEM.perip_clk_en0 is a shared register, so this function must be used in an atomic way
#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset UART module
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num)
{
case 0:
SYSTEM.perip_rst_en0.uart_rst = 1;
SYSTEM.perip_rst_en0.uart_rst = 0;
break;
case 1:
SYSTEM.perip_rst_en0.uart1_rst = 1;
SYSTEM.perip_rst_en0.uart1_rst = 0;
break;
default:
abort();
break;
}
}
// SYSTEM.perip_rst_en0 is a shared register, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Set the UART source clock.
*

55
components/hal/esp32c3/include/hal/uart_ll.h
View File

@ -15,6 +15,7 @@
#include "hal/uart_types.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/system_struct.h"
#include "esp_attr.h"
#ifdef __cplusplus
@ -97,6 +98,60 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
hw->clk_conf.tx_sclk_en = 0;
}
/**
* @brief Enable the bus clock for uart
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable true to enable, false to disable
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
switch (uart_num)
{
case 0:
SYSTEM.perip_clk_en0.reg_uart_clk_en = enable;
break;
case 1:
SYSTEM.perip_clk_en0.reg_uart1_clk_en = enable;
break;
case 2:
SYSTEM.perip_clk_en1.reg_uart2_clk_en = enable;
break;
default:
abort();
break;
}
}
// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset UART module
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num)
{
case 0:
SYSTEM.perip_rst_en0.reg_uart_rst = 1;
SYSTEM.perip_rst_en0.reg_uart_rst = 0;
break;
case 1:
SYSTEM.perip_rst_en0.reg_uart1_rst = 1;
SYSTEM.perip_rst_en0.reg_uart1_rst = 0;
break;
case 2:
SYSTEM.perip_rst_en1.reg_uart2_rst = 1;
SYSTEM.perip_rst_en1.reg_uart2_rst = 0;
break;
default:
abort();
break;
}
}
// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Set the UART source clock.
*

45
components/hal/esp32c6/include/hal/uart_ll.h
View File

@ -229,6 +229,51 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
}
}
/**
* @brief Enable the bus clock for uart
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable true to enable, false to disable
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
switch (uart_num)
{
case 0:
PCR.uart0_conf.uart0_clk_en = enable;
break;
case 1:
PCR.uart1_conf.uart1_clk_en = enable;
break;
default:
// LP_UART
abort();
break;
}
}
/**
* @brief Reset UART module
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num)
{
case 0:
PCR.uart0_conf.uart0_rst_en = 1;
PCR.uart0_conf.uart0_rst_en = 0;
break;
case 1:
PCR.uart1_conf.uart1_rst_en = 1;
PCR.uart1_conf.uart1_rst_en = 0;
break;
default:
// LP_UART
abort();
break;
}
}
/**
* @brief Set the UART source clock.
*

43
components/hal/esp32h2/include/hal/uart_ll.h
View File

@ -130,6 +130,49 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0);
}
/**
* @brief Enable the bus clock for uart
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable true to enable, false to disable
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
switch (uart_num)
{
case 0:
PCR.uart0_conf.uart0_clk_en = enable;
break;
case 1:
PCR.uart1_conf.uart1_clk_en = enable;
break;
default:
abort();
break;
}
}
/**
* @brief Reset UART module
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num)
{
case 0:
PCR.uart0_conf.uart0_rst_en = 1;
PCR.uart0_conf.uart0_rst_en = 0;
break;
case 1:
PCR.uart1_conf.uart1_rst_en = 1;
PCR.uart1_conf.uart1_rst_en = 0;
break;
default:
abort();
break;
}
}
/**
* @brief Set the UART source clock.
*

35
components/hal/esp32p4/include/hal/clk_gate_ll.h
View File

@ -38,16 +38,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN;
case PERIPH_LCD_MODULE:
return HP_SYS_CLKRST_REG_LCD_CLK_EN;
case PERIPH_UART0_MODULE:
return HP_SYS_CLKRST_REG_UART0_CLK_EN;
case PERIPH_UART1_MODULE:
return HP_SYS_CLKRST_REG_UART1_CLK_EN;
case PERIPH_UART2_MODULE:
return HP_SYS_CLKRST_REG_UART2_CLK_EN;
case PERIPH_UART3_MODULE:
return HP_SYS_CLKRST_REG_UART3_CLK_EN;
case PERIPH_UART4_MODULE:
return HP_SYS_CLKRST_REG_UART4_CLK_EN;
case PERIPH_TWAI0_MODULE:
return HP_SYS_CLKRST_REG_TWAI0_CLK_EN;
case PERIPH_TWAI1_MODULE:
@ -119,16 +109,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return HP_SYS_CLKRST_REG_RST_EN_PPA;
case PERIPH_SYSTIMER_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_STIMER;
case PERIPH_UART0_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_UART0_CORE;
case PERIPH_UART1_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_UART1_CORE;
case PERIPH_UART2_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_UART2_CORE;
case PERIPH_UART3_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_UART3_CORE;
case PERIPH_UART4_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_UART4_CORE;
case PERIPH_UHCI_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_UHCI;
case PERIPH_I3C_MODULE:
@ -210,16 +190,6 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
return HP_SYS_CLKRST_SOC_CLK_CTRL2_REG;
case PERIPH_LCD_MODULE:
return HP_SYS_CLKRST_PERI_CLK_CTRL110_REG;
case PERIPH_UART0_MODULE:
return HP_SYS_CLKRST_PERI_CLK_CTRL111_REG;
case PERIPH_UART1_MODULE:
return HP_SYS_CLKRST_PERI_CLK_CTRL112_REG;
case PERIPH_UART2_MODULE:
return HP_SYS_CLKRST_PERI_CLK_CTRL113_REG;
case PERIPH_UART3_MODULE:
return HP_SYS_CLKRST_PERI_CLK_CTRL114_REG;
case PERIPH_UART4_MODULE:
return HP_SYS_CLKRST_PERI_CLK_CTRL115_REG;
case PERIPH_TWAI0_MODULE:
case PERIPH_TWAI1_MODULE:
case PERIPH_TWAI2_MODULE:
@ -268,11 +238,6 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
return HP_SYS_CLKRST_HP_RST_EN0_REG;
case PERIPH_PPA_MODULE:
case PERIPH_SYSTIMER_MODULE:
case PERIPH_UART0_MODULE:
case PERIPH_UART1_MODULE:
case PERIPH_UART2_MODULE:
case PERIPH_UART3_MODULE:
case PERIPH_UART4_MODULE:
case PERIPH_UHCI_MODULE:
case PERIPH_I3C_MODULE:
case PERIPH_I2C0_MODULE:

194
components/hal/esp32p4/include/hal/uart_ll.h
View File

@ -87,6 +87,9 @@ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *sou
case 1:
*source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2;
break;
case 2:
*source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_PLL;
break;
}
}
@ -96,7 +99,7 @@ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *sou
* @param hw Address offset of the LP UART peripheral registers
* @param src_clk Source clock for the LP UART peripheral
*/
static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_clk_src_t src_clk)
FORCE_INLINE_ATTR void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_clk_src_t src_clk)
{
(void)hw;
switch (src_clk) {
@ -106,13 +109,16 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
case LP_UART_SCLK_XTAL_D2:
LPPERI.core_clk_sel.lp_uart_clk_sel = 1;
break;
case LP_UART_SCLK_LP_PLL:
LPPERI.core_clk_sel.lp_uart_clk_sel = 2;
break;
default:
// Invalid LP_UART clock source
HAL_ASSERT(false);
}
}
/// LPPERI.core_clk_sel is a shared register, so this function must be used in an atomic way
// LPPERI.core_clk_sel is a shared register, so this function must be used in an atomic way
#define lp_uart_ll_set_source_clk(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_set_source_clk(__VA_ARGS__)
/**
@ -121,13 +127,13 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
* @param hw_id LP UART instance ID
* @param enable True to enable, False to disable
*/
static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable)
FORCE_INLINE_ATTR void lp_uart_ll_enable_bus_clock(int hw_id, bool enable)
{
(void)hw_id;
LPPERI.clk_en.ck_en_lp_uart = enable;
}
/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
#define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_enable_bus_clock(__VA_ARGS__)
/**
@ -135,17 +141,18 @@ static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable)
*
* @param hw_id LP UART instance ID
*/
static inline void lp_uart_ll_reset_register(int hw_id)
FORCE_INLINE_ATTR void lp_uart_ll_reset_register(int hw_id)
{
(void)hw_id;
LPPERI.reset_en.rst_en_lp_uart = 1;
LPPERI.reset_en.rst_en_lp_uart = 0;
}
/// LPPERI.reset_en is a shared register, so this function must be used in an atomic way
// LPPERI.reset_en is a shared register, so this function must be used in an atomic way
#define lp_uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_reset_register(__VA_ARGS__)
/*************************************** General LL functions ******************************************/
/**
* @brief Sync the update to UART core clock domain
*
@ -186,6 +193,8 @@ FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
abort();
}
}
// HP_SYS_CLKRST.hp_rst_en1 is a shared register, so this function must be used in an atomic way
#define uart_ll_set_reset_core(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_set_reset_core(__VA_ARGS__)
/**
* @brief Enable the UART clock.
@ -199,35 +208,22 @@ FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
{
if ((hw) == &UART0) {
HP_SYS_CLKRST.peri_clk_ctrl110.reg_uart0_clk_en = 1;
//To do: call these two in clk_gate_ll.h
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart0_sys_clk_en = 1;
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart0_apb_clk_en = 1;
} else if ((hw) == &UART1) {
HP_SYS_CLKRST.peri_clk_ctrl111.reg_uart1_clk_en = 1;
//To do: call these two in clk_gate_ll.h
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart1_sys_clk_en = 1;
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart1_apb_clk_en = 1;
} else if ((hw) == &UART2) {
HP_SYS_CLKRST.peri_clk_ctrl112.reg_uart2_clk_en = 1;
//To do: call these two in clk_gate_ll.h
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart2_sys_clk_en = 1;
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart2_apb_clk_en = 1;
} else if ((hw) == &UART3) {
HP_SYS_CLKRST.peri_clk_ctrl113.reg_uart3_clk_en = 1;
//To do: call these two in clk_gate_ll.h
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart3_sys_clk_en = 1;
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart3_apb_clk_en = 1;
} else if ((hw) == &UART4) {
HP_SYS_CLKRST.peri_clk_ctrl114.reg_uart4_clk_en = 1;
//To do: call these two in clk_gate_ll.h
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart4_sys_clk_en = 1;
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart4_apb_clk_en = 1;
} else {
// LP_UART reset shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
abort();
}
}
// HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way
#define uart_ll_sclk_enable(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_sclk_enable(__VA_ARGS__)
/**
* @brief Disable the UART clock.
@ -240,35 +236,97 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
{
if ((hw) == &UART0) {
HP_SYS_CLKRST.peri_clk_ctrl110.reg_uart0_clk_en = 0;
//To do: call these two in clk_gate_ll.h
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart0_sys_clk_en = 0;
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart0_apb_clk_en = 0;
} else if ((hw) == &UART1) {
HP_SYS_CLKRST.peri_clk_ctrl111.reg_uart1_clk_en = 0;
//To do: call these two in clk_gate_ll.h
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart1_sys_clk_en = 0;
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart1_apb_clk_en = 0;
} else if ((hw) == &UART2) {
HP_SYS_CLKRST.peri_clk_ctrl112.reg_uart2_clk_en = 0;
//To do: call these two in clk_gate_ll.h
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart2_sys_clk_en = 0;
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart2_apb_clk_en = 0;
} else if ((hw) == &UART3) {
HP_SYS_CLKRST.peri_clk_ctrl113.reg_uart3_clk_en = 0;
//To do: call these two in clk_gate_ll.h
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart3_sys_clk_en = 0;
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart3_apb_clk_en = 0;
} else if ((hw) == &UART4) {
HP_SYS_CLKRST.peri_clk_ctrl114.reg_uart4_clk_en = 0;
//To do: call these two in clk_gate_ll.h
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart4_sys_clk_en = 0;
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart4_apb_clk_en = 0;
} else {
// LP_UART reset shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
abort();
}
}
// HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way
#define uart_ll_sclk_disable(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_sclk_disable(__VA_ARGS__)
/**
* @brief Enable the bus clock for uart
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable true to enable, false to disable
*/
FORCE_INLINE_ATTR void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
switch (uart_num)
{
case 0:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart0_apb_clk_en = enable;
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart0_sys_clk_en = enable;
break;
case 1:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart1_apb_clk_en = enable;
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart1_sys_clk_en = enable;
break;
case 2:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart2_apb_clk_en = enable;
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart2_sys_clk_en = enable;
break;
case 3:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart3_apb_clk_en = enable;
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart3_sys_clk_en = enable;
break;
case 4:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uart4_apb_clk_en = enable;
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uart4_sys_clk_en = enable;
break;
default:
// LP_UART
abort();
break;
}
}
// HP_SYS_CLKRST.soc_clk_ctrlx are shared registers, so this function must be used in an atomic way
#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset UART module
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
*/
FORCE_INLINE_ATTR void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num)
{
case 0:
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart0_apb = 1;
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart0_apb = 0;
break;
case 1:
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart1_apb = 1;
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart1_apb = 0;
break;
case 2:
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart2_apb = 1;
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart2_apb = 0;
break;
case 3:
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart3_apb = 1;
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart3_apb = 0;
break;
case 4:
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart4_apb = 1;
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart4_apb = 0;
break;
default:
// LP_UART
abort();
break;
}
}
// HP_SYS_CLKRST.hp_rst_en1 is a shared register, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Set the UART source clock.
@ -307,11 +365,11 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
} else if ((hw) == &UART4) {
HP_SYS_CLKRST.peri_clk_ctrl114.reg_uart4_clk_src_sel = sel_value;
} else {
// LP_UART reset shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
abort();
}
}
//HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way
#define uart_ll_set_sclk(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_set_sclk(__VA_ARGS__)
/**
* @brief Get the UART source clock type.
@ -364,36 +422,36 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
if ((hw) == &LP_UART){
uint32_t clk_div = ((sclk_freq) << 4) / (baud);
hw->clkdiv_sync.clkdiv = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
} else {
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
int sclk_div = DIV_UP(sclk_freq, max_div * baud);
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
hw->clkdiv_sync.clkdiv = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
//needs force u32 write
if ((hw) == &UART0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl111, reg_uart0_sclk_div_num, sclk_div - 1);
} else if ((hw) == &UART1){
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl112, reg_uart1_sclk_div_num, sclk_div - 1);
} else if ((hw) == &UART2){
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl113, reg_uart2_sclk_div_num, sclk_div - 1);
} else if ((hw) == &UART3){
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl114, reg_uart3_sclk_div_num, sclk_div - 1);
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl115, reg_uart4_sclk_div_num, sclk_div - 1);
}
}
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
int sclk_div = DIV_UP(sclk_freq, max_div * baud);
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
hw->clkdiv_sync.clkdiv = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
//needs force u32 write
if ((hw) == &UART0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl111, reg_uart0_sclk_div_num, sclk_div - 1);
} else if ((hw) == &UART1) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl112, reg_uart1_sclk_div_num, sclk_div - 1);
} else if ((hw) == &UART2) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl113, reg_uart2_sclk_div_num, sclk_div - 1);
} else if ((hw) == &UART3) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl114, reg_uart3_sclk_div_num, sclk_div - 1);
} else if ((hw) == &UART4) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl115, reg_uart4_sclk_div_num, sclk_div - 1);
} else {
//LP UART
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
}
#undef DIV_UP
uart_ll_update(hw);
}
#if !BOOTLOADER_BUILD
//HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way
#define uart_ll_set_baudrate(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_set_baudrate(__VA_ARGS__)
#endif
/**
* @brief Get the current baud-rate.
@ -410,13 +468,13 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
int sclk_div = 0;
if ((hw) == &UART0) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl111, reg_uart0_sclk_div_num) + 1;
} else if ((hw) == &UART1){
} else if ((hw) == &UART1) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl112, reg_uart1_sclk_div_num) + 1;
} else if ((hw) == &UART2){
} else if ((hw) == &UART2) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl113, reg_uart2_sclk_div_num) + 1;
} else if ((hw) == &UART3){
} else if ((hw) == &UART3) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl114, reg_uart3_sclk_div_num) + 1;
} else if ((hw) == &UART4){
} else if ((hw) == &UART4) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl115, reg_uart4_sclk_div_num) + 1;
} else {
return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag));

54
components/hal/esp32s2/include/hal/uart_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -15,6 +15,8 @@
#include "hal/uart_types.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/system_reg.h"
#include "soc/dport_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
@ -53,6 +55,56 @@ typedef enum {
UART_INTR_WAKEUP = (0x1 << 19),
} uart_intr_t;
/**
* @brief Enable the bus clock for uart
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable true to enable, false to disable
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
uint32_t reg_val = READ_PERI_REG(DPORT_PERIP_CLK_EN0_REG);
switch (uart_num)
{
case 0:
reg_val = reg_val & (~DPORT_UART_CLK_EN);
reg_val = reg_val | (enable << DPORT_UART_CLK_EN_S);
break;
case 1:
reg_val = reg_val & (~DPORT_UART1_CLK_EN);
reg_val = reg_val | (enable << DPORT_UART1_CLK_EN_S);
break;
default:
abort();
break;
}
WRITE_PERI_REG(DPORT_PERIP_CLK_EN0_REG, reg_val);
}
#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset UART module
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num)
{
case 0:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
break;
case 1:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
break;
default:
abort();
break;
}
}
// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Set the UART source clock.
*

55
components/hal/esp32s3/include/hal/uart_ll.h
View File

@ -15,6 +15,7 @@
#include "hal/uart_types.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/system_struct.h"
#include "esp_attr.h"
#ifdef __cplusplus
@ -69,6 +70,60 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
hw->clk_conf.rst_core = core_rst_en;
}
/**
* @brief Enable the bus clock for uart
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable true to enable, false to disable
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
switch (uart_num)
{
case 0:
SYSTEM.perip_clk_en0.uart_clk_en = enable;
break;
case 1:
SYSTEM.perip_clk_en0.uart1_clk_en = enable;
break;
case 2:
SYSTEM.perip_clk_en1.uart2_clk_en = enable;
break;
default:
abort();
break;
}
}
// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset UART module
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num)
{
case 0:
SYSTEM.perip_rst_en0.uart_rst = 1;
SYSTEM.perip_rst_en0.uart_rst = 0;
break;
case 1:
SYSTEM.perip_rst_en0.uart1_rst = 1;
SYSTEM.perip_rst_en0.uart1_rst = 0;
break;
case 2:
SYSTEM.perip_rst_en1.uart2_rst = 1;
SYSTEM.perip_rst_en1.uart2_rst = 0;
break;
default:
abort();
break;
}
}
// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Set the UART source clock.
*

42
components/hal/include/hal/uart_hal.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -29,6 +29,26 @@ typedef struct {
uart_dev_t *dev;
} uart_hal_context_t;
/**
* @brief Configure the UART baud-rate and select the source clock
*
* @param hal Context of the HAL layer
* @param baud_rate The baud-rate to be set
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
*/
#define uart_hal_set_baudrate(hal, baud_rate, sclk_freq) uart_ll_set_baudrate((hal)->dev, baud_rate, sclk_freq)
/**
* @brief Set the UART source clock type
* @param hal Context of the HAL layer
* @param sclk The UART source clock type.
*
* @return None
*/
#define uart_hal_set_sclk(hal, sclk) uart_ll_set_sclk((hal)->dev, sclk);
/**
* @brief Clear the UART interrupt status
*
@ -188,15 +208,6 @@ void uart_hal_rxfifo_rst(uart_hal_context_t *hal);
*/
void uart_hal_init(uart_hal_context_t *hal, uart_port_t uart_num);
/**
* @brief Set the UART source clock type
* @param hal Context of the HAL layer
* @param sclk The UART source clock type.
*
* @return None
*/
void uart_hal_set_sclk(uart_hal_context_t *hal, soc_module_clk_t sclk);
/**
* @brief Get the UART source clock type
*
@ -207,17 +218,6 @@ void uart_hal_set_sclk(uart_hal_context_t *hal, soc_module_clk_t sclk);
*/
void uart_hal_get_sclk(uart_hal_context_t *hal, soc_module_clk_t *sclk);
/**
* @brief Configure the UART baud-rate and select the source clock
*
* @param hal Context of the HAL layer
* @param baud_rate The baud-rate to be set
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
*/
void uart_hal_set_baudrate(uart_hal_context_t *hal, uint32_t baud_rate, uint32_t sclk_freq);
/**
* @brief Configure the UART stop bit
*

12
components/hal/uart_hal.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -8,21 +8,11 @@
#include "hal/uart_hal.h"
#include "soc/soc_caps.h"
void uart_hal_set_sclk(uart_hal_context_t *hal, soc_module_clk_t sclk)
{
uart_ll_set_sclk(hal->dev, sclk);
}
void uart_hal_get_sclk(uart_hal_context_t *hal, soc_module_clk_t *sclk)
{
uart_ll_get_sclk(hal->dev, sclk);
}
void uart_hal_set_baudrate(uart_hal_context_t *hal, uint32_t baud_rate, uint32_t sclk_freq)
{
uart_ll_set_baudrate(hal->dev, baud_rate, sclk_freq);
}
void uart_hal_get_baudrate(uart_hal_context_t *hal, uint32_t *baud_rate, uint32_t sclk_freq)
{
*baud_rate = uart_ll_get_baudrate(hal->dev, sclk_freq);

16
components/soc/esp32p4/include/soc/uart_struct.h
View File

@ -880,7 +880,21 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.
*/
uint32_t sclk_div_b:6;
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
*/
uint32_t sclk_div_a:6;
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
* It is only used by LP UART
* HP UART's sclk_div_num is in hp_sys_clkrst_struct.h
*/
uint32_t sclk_div_num:8;
uint32_t reserved_20:4;
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
* Set this bit to enable UART Tx clock.
*/

5
components/ulp/lp_core/lp_core_uart.c
View File

@ -13,6 +13,7 @@
#include "hal/rtc_io_types.h"
#include "esp_clk_tree.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/uart_private.h"
#define LP_UART_PORT_NUM LP_UART_NUM_0
#define LP_UART_TX_IDLE_NUM_DEFAULT (0U)
@ -52,7 +53,9 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg)
}
/* Override protocol parameters from the configuration */
uart_hal_set_baudrate(&hal, cfg->uart_proto_cfg.baud_rate, sclk_freq);
UART_CLK_ATOMIC() {
uart_hal_set_baudrate(&hal, cfg->uart_proto_cfg.baud_rate, sclk_freq);
}
uart_hal_set_parity(&hal, cfg->uart_proto_cfg.parity);
uart_hal_set_data_bit_num(&hal, cfg->uart_proto_cfg.data_bits);
uart_hal_set_stop_bits(&hal, cfg->uart_proto_cfg.stop_bits);