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soc/rtc_clk: don’t clear DPORT_CPUPERIOD_SEL when switching to XTAL
This is not necessary since RTC_CNTL_SOC_CLK_SEL is set before this.
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@ -400,7 +400,6 @@ static void rtc_clk_cpu_freq_to_xtal()
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
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REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
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REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
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DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL
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rtc_clk_apb_freq_update(xtal_freq * MHZ);
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rtc_clk_apb_freq_update(xtal_freq * MHZ);
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s_cur_freq = RTC_CPU_FREQ_XTAL;
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s_cur_freq = RTC_CPU_FREQ_XTAL;
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@ -472,7 +471,6 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
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*/
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*/
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rtc_clk_wait_for_slow_cycle();
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rtc_clk_wait_for_slow_cycle();
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
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RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
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RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
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RTC_CNTL_BBPLL_I2C_FORCE_PD);
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RTC_CNTL_BBPLL_I2C_FORCE_PD);
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