From 44df5b31afb68177570152f63dd46e5d35382532 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 30 Jan 2023 18:03:41 +0800 Subject: [PATCH] feature: add ram loadable app support --- Kconfig | 6 +- components/bootloader_support/CMakeLists.txt | 28 +++++--- .../bootloader_support/src/bootloader_init.c | 12 ++-- .../src/esp32/bootloader_esp32.c | 23 ++++--- .../src/esp32c2/bootloader_esp32c2.c | 28 +++++--- .../src/esp32c3/bootloader_esp32c3.c | 27 +++++--- .../src/esp32c6/bootloader_esp32c6.c | 31 ++++++--- .../src/esp32h2/bootloader_esp32h2.c | 30 ++++++--- .../src/esp32h4/bootloader_esp32h4.c | 26 ++++--- .../src/esp32s2/bootloader_esp32s2.c | 31 ++++++--- .../src/esp32s3/bootloader_esp32s3.c | 26 ++++--- components/esp_hw_support/Kconfig | 1 + .../esp_hw_support/port/esp32s3/rtc_init.c | 8 +-- components/esp_psram/Kconfig | 2 +- .../esp_rom/esp32c6/ld/esp32c6.rom.api.ld | 3 +- .../esp_rom/esp32h2/ld/esp32h2.rom.api.ld | 3 +- .../esp32h4/ld/rev1/esp32h4.rom.api.ld | 1 + components/esp_system/esp_err.c | 5 +- .../esp_system/ld/esp32c3/sections.ld.in | 2 +- .../esp_system/ld/esp32c6/sections.ld.in | 2 +- .../esp_system/ld/esp32h2/sections.ld.in | 2 +- .../esp_system/ld/esp32h4/sections.ld.in | 2 +- .../esp_system/ld/esp32s2/sections.ld.in | 1 - .../esp_system/ld/esp32s3/sections.ld.in | 2 +- components/esp_system/ld/ld.common | 4 ++ components/esp_system/port/cpu_start.c | 67 ++++++++++++------- components/esp_system/port/panic_handler.c | 8 ++- components/esp_system/startup.c | 2 + components/hal/CMakeLists.txt | 21 ++++-- components/hal/linker.lf | 9 +-- components/newlib/assert.c | 5 +- components/openthread/CMakeLists.txt | 2 + components/spi_flash/CMakeLists.txt | 18 ++--- components/spi_flash/Kconfig | 1 + components/spi_flash/linker.lf | 29 ++++---- 35 files changed, 298 insertions(+), 170 deletions(-) diff --git a/Kconfig b/Kconfig index 09cc488f4d..c830a0f28d 100644 --- a/Kconfig +++ b/Kconfig @@ -170,10 +170,10 @@ mainmenu "Espressif IoT Development Framework Configuration" Example gdbinit files for other targets can be found in tools/test_apps/system/gdb_loadable_elf/ Recommended sdkconfig.defaults for building loadable ELF files is as follows. - CONFIG_APP_BUILD_TYPE_ELF_RAM is required, other options help reduce application + CONFIG_APP_BUILD_TYPE_RAM is required, other options help reduce application memory footprint. - CONFIG_APP_BUILD_TYPE_ELF_RAM=y + CONFIG_APP_BUILD_TYPE_RAM=y CONFIG_VFS_SUPPORT_TERMIOS= CONFIG_NEWLIB_NANO_FORMAT=y CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT=y @@ -258,7 +258,7 @@ mainmenu "Espressif IoT Development Framework Configuration" bool depends on IDF_TARGET_ESP32 default y if APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS - default y if APP_BUILD_TYPE_ELF_RAM + default y if APP_BUILD_TYPE_RAM endmenu # Build type diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt index cd2e1eac74..3651258380 100644 --- a/components/bootloader_support/CMakeLists.txt +++ b/components/bootloader_support/CMakeLists.txt @@ -2,21 +2,31 @@ set(srcs "src/bootloader_common.c" "src/bootloader_common_loader.c" "src/bootloader_clock_init.c" - "bootloader_flash/src/bootloader_flash.c" "src/bootloader_mem.c" "src/bootloader_random.c" "src/bootloader_random_${IDF_TARGET}.c" - "src/bootloader_utility.c" - "src/esp_image_format.c" + "src/bootloader_efuse.c" "src/flash_encrypt.c" "src/secure_boot.c" - "src/flash_partitions.c" - "bootloader_flash/src/flash_qio_mode.c" - "bootloader_flash/src/bootloader_flash_config_${IDF_TARGET}.c" - "src/bootloader_efuse.c" ) -if(BOOTLOADER_BUILD) +if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) + list(APPEND srcs + "bootloader_flash/src/bootloader_flash.c" + "bootloader_flash/src/flash_qio_mode.c" + "bootloader_flash/src/bootloader_flash_config_${IDF_TARGET}.c" + ) +endif() + +if(CONFIG_APP_BUILD_TYPE_APP_2NDBOOT) + list(APPEND srcs + "src/bootloader_utility.c" + "src/flash_partitions.c" + "src/esp_image_format.c" + ) +endif() + +if(BOOTLOADER_BUILD OR CONFIG_APP_BUILD_TYPE_RAM) set(include_dirs "include" "bootloader_flash/include" "private_include") set(priv_requires micro-ecc spi_flash efuse esp_app_format) @@ -25,7 +35,6 @@ if(BOOTLOADER_BUILD) "src/bootloader_clock_loader.c" "src/bootloader_console.c" "src/bootloader_console_loader.c" - "src/bootloader_panic.c" "src/${IDF_TARGET}/bootloader_sha.c" "src/${IDF_TARGET}/bootloader_soc.c" "src/${IDF_TARGET}/bootloader_${IDF_TARGET}.c" @@ -41,6 +50,7 @@ else() endif() if(BOOTLOADER_BUILD) + list(APPEND srcs "src/bootloader_panic.c") if(CONFIG_SECURE_FLASH_ENC_ENABLED) list(APPEND srcs "src/flash_encryption/flash_encrypt.c" "src/${IDF_TARGET}/flash_encryption_secure_features.c") diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c index 5b568eccb2..a03a1544f4 100644 --- a/components/bootloader_support/src/bootloader_init.c +++ b/components/bootloader_support/src/bootloader_init.c @@ -33,7 +33,7 @@ esp_err_t bootloader_read_bootloader_header(void) { /* load bootloader image header */ if (bootloader_flash_read(ESP_BOOTLOADER_OFFSET, &bootloader_image_hdr, sizeof(esp_image_header_t), true) != ESP_OK) { - ESP_LOGE(TAG, "failed to load bootloader image header!"); + ESP_EARLY_LOGE(TAG, "failed to load bootloader image header!"); return ESP_FAIL; } return ESP_OK; @@ -44,7 +44,7 @@ esp_err_t bootloader_check_bootloader_validity(void) unsigned int revision = efuse_hal_chip_revision(); unsigned int major = revision / 100; unsigned int minor = revision % 100; - ESP_LOGI(TAG, "chip revision: v%d.%d", major, minor); + ESP_EARLY_LOGI(TAG, "chip revision: v%d.%d", major, minor); /* compare with the one set in bootloader image header */ if (bootloader_common_check_chip_validity(&bootloader_image_hdr, ESP_IMAGE_BOOTLOADER) != ESP_OK) { return ESP_FAIL; @@ -72,7 +72,7 @@ void bootloader_config_wdt(void) #ifdef CONFIG_BOOTLOADER_WDT_ENABLE //Initialize and start RWDT to protect the for bootloader if configured to do so - ESP_LOGD(TAG, "Enabling RTCWDT(%d ms)", CONFIG_BOOTLOADER_WDT_TIME_MS); + ESP_EARLY_LOGD(TAG, "Enabling RTCWDT(%d ms)", CONFIG_BOOTLOADER_WDT_TIME_MS); wdt_hal_init(&rwdt_ctx, WDT_RWDT, 0, false); uint32_t stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000); wdt_hal_write_protect_disable(&rwdt_ctx); @@ -90,14 +90,14 @@ void bootloader_config_wdt(void) void bootloader_enable_random(void) { - ESP_LOGI(TAG, "Enabling RNG early entropy source..."); + ESP_EARLY_LOGI(TAG, "Enabling RNG early entropy source..."); bootloader_random_enable(); } void bootloader_print_banner(void) { - ESP_LOGI(TAG, "ESP-IDF %s 2nd stage bootloader", IDF_VER); + ESP_EARLY_LOGI(TAG, "ESP-IDF %s 2nd stage bootloader", IDF_VER); #ifndef CONFIG_APP_REPRODUCIBLE_BUILD - ESP_LOGI(TAG, "compile time " __DATE__ " " __TIME__); + ESP_EARLY_LOGI(TAG, "compile time " __DATE__ " " __TIME__); #endif } diff --git a/components/bootloader_support/src/esp32/bootloader_esp32.c b/components/bootloader_support/src/esp32/bootloader_esp32.c index d3ec3497ce..e869b9b6e7 100644 --- a/components/bootloader_support/src/esp32/bootloader_esp32.c +++ b/components/bootloader_support/src/esp32/bootloader_esp32.c @@ -357,6 +357,8 @@ esp_err_t bootloader_init(void) WSR(MEMCTL, memctl); #endif // XCHAL_ERRATUM_572 +// In RAM_APP, memory will be initialized in `call_start_cpu0` +#if !CONFIG_APP_BUILD_TYPE_RAM bootloader_init_mem(); // check that static RAM is after the stack @@ -371,6 +373,8 @@ esp_err_t bootloader_init(void) #endif // clear bss section bootloader_clear_bss_section(); +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // init eFuse virtual mode (read eFuses to RAM) #ifdef CONFIG_EFUSE_VIRTUAL ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); @@ -380,11 +384,9 @@ esp_err_t bootloader_init(void) #endif // bootst up vddsdio bootloader_common_vddsdio_configure(); - // reset MMU - bootloader_reset_mmu(); // check rated CPU clock if ((ret = bootloader_check_rated_cpu_clock()) != ESP_OK) { - goto err; + return ret; } // config clock bootloader_clock_configure(); @@ -392,31 +394,36 @@ esp_err_t bootloader_init(void) bootloader_console_init(); /* print 2nd bootloader banner */ bootloader_print_banner(); + +#if !CONFIG_APP_BUILD_TYPE_RAM + // reset MMU + bootloader_reset_mmu(); // update flash ID bootloader_flash_update_id(); // Check and run XMC startup flow if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) { ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); - goto err; + return ret; } // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { - goto err; + return ret; } // read chip revision and check if it's compatible to bootloader if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { - goto err; + return ret; } // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { - goto err; + return ret; } +#endif // #if !CONFIG_APP_BUILD_TYPE_RAM + // check whether a WDT reset happend bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); // enable RNG early entropy source bootloader_enable_random(); -err: return ret; } diff --git a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c index 0b6b67f781..9da25dce2a 100644 --- a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c +++ b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c @@ -245,6 +245,9 @@ esp_err_t bootloader_init(void) esp_err_t ret = ESP_OK; bootloader_super_wdt_auto_feed(); + +// In RAM_APP, memory will be initialized in `call_start_cpu0` +#if !CONFIG_APP_BUILD_TYPE_RAM // protect memory region bootloader_init_mem(); /* check that static RAM is after the stack */ @@ -252,6 +255,8 @@ esp_err_t bootloader_init(void) assert(&_data_start <= &_data_end); // clear bss section bootloader_clear_bss_section(); +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // init eFuse virtual mode (read eFuses to RAM) #ifdef CONFIG_EFUSE_VIRTUAL ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); @@ -259,38 +264,41 @@ esp_err_t bootloader_init(void) esp_efuse_init_virtual_mode_in_ram(); #endif #endif - //init cache hal - cache_hal_init(); - //reset mmu - mmu_hal_init(); - // config mmu page size - mmu_ll_set_page_size(0, SPI_FLASH_MMU_PAGE_SIZE); // config clock bootloader_clock_configure(); // initialize console, from now on, we can use esp_log bootloader_console_init(); /* print 2nd bootloader banner */ bootloader_print_banner(); + +#if !CONFIG_APP_BUILD_TYPE_RAM + //init cache hal + cache_hal_init(); + //reset mmu + mmu_hal_init(); + // config mmu page size + mmu_ll_set_page_size(0, SPI_FLASH_MMU_PAGE_SIZE); // update flash ID bootloader_flash_update_id(); // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { - goto err; + return ret; } // read chip revision and check if it's compatible to bootloader if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { - goto err; + return ret; } // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { - goto err; + return ret; } +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // check whether a WDT reset happend bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); // enable RNG early entropy source bootloader_enable_random(); -err: return ret; } diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index c67c9aefe3..8cb6bbe3a3 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -297,6 +297,9 @@ esp_err_t bootloader_init(void) bootloader_hardware_init(); bootloader_ana_reset_config(); bootloader_super_wdt_auto_feed(); + +// In RAM_APP, memory will be initialized in `call_start_cpu0` +#if !CONFIG_APP_BUILD_TYPE_RAM // protect memory region bootloader_init_mem(); /* check that static RAM is after the stack */ @@ -304,6 +307,8 @@ esp_err_t bootloader_init(void) assert(&_data_start <= &_data_end); // clear bss section bootloader_clear_bss_section(); +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // init eFuse virtual mode (read eFuses to RAM) #ifdef CONFIG_EFUSE_VIRTUAL ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); @@ -311,41 +316,45 @@ esp_err_t bootloader_init(void) esp_efuse_init_virtual_mode_in_ram(); #endif #endif - //init cache hal - cache_hal_init(); - //reset mmu - mmu_hal_init(); // config clock bootloader_clock_configure(); // initialize console, from now on, we can use esp_log bootloader_console_init(); /* print 2nd bootloader banner */ bootloader_print_banner(); + +#if !CONFIG_APP_BUILD_TYPE_RAM + //init cache hal + cache_hal_init(); + //reset mmu + mmu_hal_init(); // update flash ID bootloader_flash_update_id(); // Check and run XMC startup flow if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) { ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); - goto err; + return ret; } // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { - goto err; + return ret; } // read chip revision and check if it's compatible to bootloader if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { - goto err; + return ret; } // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { - goto err; + return ret; } +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // check whether a WDT reset happend bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); // enable RNG early entropy source bootloader_enable_random(); -err: + return ret; } diff --git a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c index eee533e640..f3eeb64a0a 100644 --- a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c +++ b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -229,7 +229,7 @@ static void bootloader_super_wdt_auto_feed(void) static inline void bootloader_hardware_init(void) { // In 80MHz flash mode, ROM sets the mspi module clk divider to 2, fix it here -#if CONFIG_ESPTOOLPY_FLASHFREQ_80M +#if CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_APP_BUILD_TYPE_RAM clk_ll_mspi_fast_set_hs_divider(6); esp_rom_spiflash_config_clk(1, 0); esp_rom_spiflash_config_clk(1, 1); @@ -280,6 +280,9 @@ esp_err_t bootloader_init(void) bootloader_hardware_init(); bootloader_ana_reset_config(); bootloader_super_wdt_auto_feed(); + +// In RAM_APP, memory will be initialized in `call_start_cpu0` +#if !CONFIG_APP_BUILD_TYPE_RAM // protect memory region bootloader_init_mem(); /* check that static RAM is after the stack */ @@ -287,6 +290,8 @@ esp_err_t bootloader_init(void) assert(&_data_start <= &_data_end); // clear bss section bootloader_clear_bss_section(); +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // init eFuse virtual mode (read eFuses to RAM) #ifdef CONFIG_EFUSE_VIRTUAL ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); @@ -294,41 +299,45 @@ esp_err_t bootloader_init(void) esp_efuse_init_virtual_mode_in_ram(); #endif #endif - //init cache hal - cache_hal_init(); - //reset mmu - mmu_hal_init(); // config clock bootloader_clock_configure(); // initialize console, from now on, we can use esp_log bootloader_console_init(); /* print 2nd bootloader banner */ bootloader_print_banner(); + +#if !CONFIG_APP_BUILD_TYPE_RAM + //init cache hal + cache_hal_init(); + //reset mmu + mmu_hal_init(); // update flash ID bootloader_flash_update_id(); // Check and run XMC startup flow if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) { ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); - goto err; + return ret; } // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { - goto err; + return ret; } // read chip revision and check if it's compatible to bootloader if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { - goto err; + return ret; } // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { - goto err; + return ret; } +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // check whether a WDT reset happend bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); // enable RNG early entropy source bootloader_enable_random(); -err: + return ret; } diff --git a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c index e4043e49d3..a2c9245e30 100644 --- a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c +++ b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -267,6 +267,9 @@ esp_err_t bootloader_init(void) bootloader_hardware_init(); bootloader_ana_reset_config(); bootloader_super_wdt_auto_feed(); + +// In RAM_APP, memory will be initialized in `call_start_cpu0` +#if !CONFIG_APP_BUILD_TYPE_RAM // protect memory region bootloader_init_mem(); /* check that static RAM is after the stack */ @@ -274,6 +277,8 @@ esp_err_t bootloader_init(void) assert(&_data_start <= &_data_end); // clear bss section bootloader_clear_bss_section(); +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // init eFuse virtual mode (read eFuses to RAM) #ifdef CONFIG_EFUSE_VIRTUAL ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); @@ -281,41 +286,46 @@ esp_err_t bootloader_init(void) esp_efuse_init_virtual_mode_in_ram(); #endif #endif - //init cache hal - cache_hal_init(); - //reset mmu - mmu_hal_init(); // config clock bootloader_clock_configure(); // initialize console, from now on, we can use esp_log bootloader_console_init(); /* print 2nd bootloader banner */ bootloader_print_banner(); + +#if !CONFIG_APP_BUILD_TYPE_RAM + //init cache hal + cache_hal_init(); + //reset mmu + mmu_hal_init(); + // update flash ID bootloader_flash_update_id(); // Check and run XMC startup flow if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) { ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); - goto err; + return ret; } // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { - goto err; + return ret; } // read chip revision and check if it's compatible to bootloader if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { - goto err; + return ret; } // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { - goto err; + return ret; } +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // check whether a WDT reset happend bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); // enable RNG early entropy source bootloader_enable_random(); -err: + return ret; } diff --git a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c index 9e4589383e..8d75accd18 100644 --- a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c +++ b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c @@ -263,6 +263,9 @@ esp_err_t bootloader_init(void) bootloader_hardware_init(); bootloader_ana_reset_config(); bootloader_super_wdt_auto_feed(); + +// In RAM_APP, memory will be initialized in `call_start_cpu0` +#if !CONFIG_APP_BUILD_TYPE_RAM // protect memory region bootloader_init_mem(); /* check that static RAM is after the stack */ @@ -270,41 +273,46 @@ esp_err_t bootloader_init(void) assert(&_data_start <= &_data_end); // clear bss section bootloader_clear_bss_section(); - //init cache hal - cache_hal_init(); //TODO IDF-4649 - //reset mmu - mmu_hal_init(); +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // config clock bootloader_clock_configure(); // initialize console, from now on, we can use esp_log bootloader_console_init(); /* print 2nd bootloader banner */ bootloader_print_banner(); + +#if !CONFIG_APP_BUILD_TYPE_RAM + //init cache hal + cache_hal_init(); //TODO IDF-4649 + //reset mmu + mmu_hal_init(); // update flash ID bootloader_flash_update_id(); // Check and run XMC startup flow if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) { ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); - goto err; + return ret; } // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { - goto err; + return ret; } // read chip revision and check if it's compatible to bootloader if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { - goto err; + return ret; } // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { - goto err; + return ret; } +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // check whether a WDT reset happend bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); // enable RNG early entropy source bootloader_enable_random(); -err: return ret; } diff --git a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c index 7a280e8805..8250bd63f1 100644 --- a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c +++ b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c @@ -287,6 +287,8 @@ esp_err_t bootloader_init(void) bootloader_super_wdt_auto_feed(); // protect memory region +// In RAM_APP, memory will be initialized in `call_start_cpu0` +#if !CONFIG_APP_BUILD_TYPE_RAM bootloader_init_mem(); /* check that static RAM is after the stack */ @@ -298,6 +300,8 @@ esp_err_t bootloader_init(void) #endif // clear bss section bootloader_clear_bss_section(); +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // init eFuse virtual mode (read eFuses to RAM) #ifdef CONFIG_EFUSE_VIRTUAL ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); @@ -305,43 +309,48 @@ esp_err_t bootloader_init(void) esp_efuse_init_virtual_mode_in_ram(); #endif #endif - // init cache hal - cache_hal_init(); - // reset mmu - mmu_hal_init(); - // Workaround: normal ROM bootloader exits with DROM0 cache unmasked, but 2nd bootloader exits with it masked. - REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0); + // config clock bootloader_clock_configure(); // initialize console, from now on, we can use esp_log bootloader_console_init(); /* print 2nd bootloader banner */ bootloader_print_banner(); + +#if !CONFIG_APP_BUILD_TYPE_RAM + // init cache hal + cache_hal_init(); + // reset mmu + mmu_hal_init(); + // Workaround: normal ROM bootloader exits with DROM0 cache unmasked, but 2nd bootloader exits with it masked. + REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0); // update flash ID bootloader_flash_update_id(); // Check and run XMC startup flow if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) { ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); - goto err; + return ret; } // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { - goto err; + return ret; } // read chip revision and check if it's compatible to bootloader if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { - goto err; + return ret; } // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { - goto err; + return ret; } +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // check whether a WDT reset happend bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); // enable RNG early entropy source bootloader_enable_random(); -err: + return ret; } diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c index 53a426a6c0..e28ddcf384 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -333,6 +333,9 @@ esp_err_t bootloader_init(void) bootloader_ana_reset_config(); bootloader_super_wdt_auto_feed(); + +// In RAM_APP, memory will be initialized in `call_start_cpu0` +#if !CONFIG_APP_BUILD_TYPE_RAM // protect memory region bootloader_init_mem(); /* check that static RAM is after the stack */ @@ -344,6 +347,8 @@ esp_err_t bootloader_init(void) #endif // clear bss section bootloader_clear_bss_section(); +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // init eFuse virtual mode (read eFuses to RAM) #ifdef CONFIG_EFUSE_VIRTUAL ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); @@ -351,41 +356,44 @@ esp_err_t bootloader_init(void) esp_efuse_init_virtual_mode_in_ram(); #endif #endif - //init cache hal - cache_hal_init(); - //reset mmu - mmu_hal_init(); // config clock bootloader_clock_configure(); // initialize console, from now on, we can use esp_log bootloader_console_init(); /* print 2nd bootloader banner */ bootloader_print_banner(); + +#if !CONFIG_APP_BUILD_TYPE_RAM + //init cache hal + cache_hal_init(); + //reset mmu + mmu_hal_init(); // update flash ID bootloader_flash_update_id(); // Check and run XMC startup flow if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) { ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); - goto err; + return ret; } // read bootloader header if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { - goto err; + return ret; } // read chip revision and check if it's compatible to bootloader if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { - goto err; + return ret; } // initialize spi flash if ((ret = bootloader_init_spi_flash()) != ESP_OK) { - goto err; + return ret; } +#endif // !CONFIG_APP_BUILD_TYPE_RAM + // check whether a WDT reset happend bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); // enable RNG early entropy source bootloader_enable_random(); -err: return ret; } diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index 19bcccb506..a4985c24d1 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -96,6 +96,7 @@ menu "Hardware Settings" config ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND bool "Flash leakage current workaround in light sleep" + depends on !APP_BUILD_TYPE_PURE_RAM_APP default y help When the CS pin of Flash is not pulled up, the sleep current will diff --git a/components/esp_hw_support/port/esp32s3/rtc_init.c b/components/esp_hw_support/port/esp32s3/rtc_init.c index 18b7abd5a5..3a3600440c 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_init.c +++ b/components/esp_hw_support/port/esp32s3/rtc_init.c @@ -252,7 +252,7 @@ static void set_ocode_by_efuse(int calib_version) */ static void calibrate_ocode(void) { -#ifndef BOOTLOADER_BUILD +#if !defined(BOOTLOADER_BUILD) && !defined(CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) /** * Background: * 1. Following code will switch the system clock to XTAL first, to self-calibrate the OCode. @@ -262,7 +262,7 @@ static void calibrate_ocode(void) * When CPU clock switches down, the delay should be cleared. Therefore here we call this function to remove the delays. */ mspi_timing_change_speed_mode_cache_safe(true); -#endif +#endif // #if !defined(BOOTLOADER_BUILD) && !defined(CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) /* Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration (must turn off PLL). Method: @@ -308,10 +308,10 @@ static void calibrate_ocode(void) } } rtc_clk_cpu_freq_set_config(&old_config); -#ifndef BOOTLOADER_BUILD +#if !defined(BOOTLOADER_BUILD) && !defined(CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) //System clock is switched back to PLL. Here we switch to the MSPI high speed mode, add the delays back mspi_timing_change_speed_mode_cache_safe(false); -#endif +#endif // #if !defined(BOOTLOADER_BUILD) && !defined(CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) } static uint32_t get_dig_dbias_by_efuse(uint8_t pvt_scheme_ver) diff --git a/components/esp_psram/Kconfig b/components/esp_psram/Kconfig index 44bcc1534d..891fa9826f 100644 --- a/components/esp_psram/Kconfig +++ b/components/esp_psram/Kconfig @@ -1,5 +1,5 @@ menu "ESP PSRAM" - + depends on !APP_BUILD_TYPE_PURE_RAM_APP # Will be refactored after !18050 to merge target-specific items orsource "./$IDF_TARGET/Kconfig.spiram" diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld index 04f47bdde3..bbb4093565 100644 --- a/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -45,6 +45,7 @@ PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); +PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable ); PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); diff --git a/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld index f6c327d758..486dd3944c 100644 --- a/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld +++ b/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -46,6 +46,7 @@ PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); +PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable ); PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld index a12e1c2c5a..a108eb5b36 100644 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld +++ b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld @@ -47,6 +47,7 @@ PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); +PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable); PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); diff --git a/components/esp_system/esp_err.c b/components/esp_system/esp_err.c index 7fbaf9dcaa..ecc3de99bb 100644 --- a/components/esp_system/esp_err.c +++ b/components/esp_system/esp_err.c @@ -31,7 +31,10 @@ static void esp_error_check_failed_print(const char *msg, esp_err_t rc, const ch esp_rom_printf(" (%s)", esp_err_to_name(rc)); #endif //CONFIG_ESP_ERR_TO_NAME_LOOKUP esp_rom_printf(" at 0x%08x\n", esp_cpu_get_call_addr(addr)); - if (spi_flash_cache_enabled()) { // strings may be in flash cache +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + if (spi_flash_cache_enabled()) // strings may be in flash cache +#endif + { esp_rom_printf("file: \"%s\" line %d\nfunc: %s\nexpression: %s\n", file, line, function, expression); } } diff --git a/components/esp_system/ld/esp32c3/sections.ld.in b/components/esp_system/ld/esp32c3/sections.ld.in index ac7ab6cfb8..bb2ed2f14c 100644 --- a/components/esp_system/ld/esp32c3/sections.ld.in +++ b/components/esp_system/ld/esp32c3/sections.ld.in @@ -250,7 +250,7 @@ SECTIONS . = . + SIZEOF(.flash.text); /* Prepare the alignment of the section above. Few bytes (0x20) must be * added for the mapping header. */ - . = ALIGN(0x10000) + 0x20; + . = ALIGN(_esp_mmu_block_size) + 0x20; _rodata_reserved_start = .; } > default_rodata_seg diff --git a/components/esp_system/ld/esp32c6/sections.ld.in b/components/esp_system/ld/esp32c6/sections.ld.in index 7a17be374e..d8e72f755a 100644 --- a/components/esp_system/ld/esp32c6/sections.ld.in +++ b/components/esp_system/ld/esp32c6/sections.ld.in @@ -283,7 +283,7 @@ SECTIONS . = . + SIZEOF(.flash.text); /* Prepare the alignment of the section above. Few bytes (0x20) must be * added for the mapping header. */ - . = ALIGN(0x10000) + 0x20; + . = ALIGN(_esp_mmu_block_size) + 0x20; _rodata_reserved_start = .; } > default_rodata_seg diff --git a/components/esp_system/ld/esp32h2/sections.ld.in b/components/esp_system/ld/esp32h2/sections.ld.in index 68508de11b..096e63d27d 100644 --- a/components/esp_system/ld/esp32h2/sections.ld.in +++ b/components/esp_system/ld/esp32h2/sections.ld.in @@ -283,7 +283,7 @@ SECTIONS . = . + SIZEOF(.flash.text); /* Prepare the alignment of the section above. Few bytes (0x20) must be * added for the mapping header. */ - . = ALIGN(0x10000) + 0x20; + . = ALIGN(_esp_mmu_block_size) + 0x20; _rodata_reserved_start = .; } > default_rodata_seg diff --git a/components/esp_system/ld/esp32h4/sections.ld.in b/components/esp_system/ld/esp32h4/sections.ld.in index ec03a82fb2..84726e7414 100644 --- a/components/esp_system/ld/esp32h4/sections.ld.in +++ b/components/esp_system/ld/esp32h4/sections.ld.in @@ -253,7 +253,7 @@ SECTIONS . = . + SIZEOF(.flash.text); /* Prepare the alignment of the section above. Few bytes (0x20) must be * added for the mapping header. */ - . = ALIGN(0x10000) + 0x20; + . = ALIGN(_esp_mmu_block_size) + 0x20; _rodata_reserved_start = .; } > default_rodata_seg diff --git a/components/esp_system/ld/esp32s2/sections.ld.in b/components/esp_system/ld/esp32s2/sections.ld.in index 1ea6eaa606..575e1e289e 100644 --- a/components/esp_system/ld/esp32s2/sections.ld.in +++ b/components/esp_system/ld/esp32s2/sections.ld.in @@ -188,7 +188,6 @@ SECTIONS /* iram_end_test section exists for use by memprot unit tests only */ *(.iram_end_test) _iram_text_end = ABSOLUTE(.); - _iram_end = ABSOLUTE(.); } > iram0_0_seg .dram0_reserved_for_iram (NOLOAD): diff --git a/components/esp_system/ld/esp32s3/sections.ld.in b/components/esp_system/ld/esp32s3/sections.ld.in index efe69736e9..afd83defa1 100644 --- a/components/esp_system/ld/esp32s3/sections.ld.in +++ b/components/esp_system/ld/esp32s3/sections.ld.in @@ -287,7 +287,7 @@ SECTIONS . = . + SIZEOF(.flash.text); /* Prepare the alignment of the section above. Few bytes (0x20) must be * added for the mapping header. */ - . = ALIGN(0x10000) + 0x20; + . = ALIGN(_esp_mmu_block_size) + 0x20; _rodata_reserved_start = .; /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ } > default_rodata_seg diff --git a/components/esp_system/ld/ld.common b/components/esp_system/ld/ld.common index 26607f9263..46f61c554b 100644 --- a/components/esp_system/ld/ld.common +++ b/components/esp_system/ld/ld.common @@ -23,4 +23,8 @@ _esp_memprot_align_size = CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE; _esp_memprot_align_size = 0; #endif +#if CONFIG_APP_BUILD_TYPE_RAM +_esp_mmu_block_size = 0; +#else _esp_mmu_block_size = (CONFIG_MMU_PAGE_SIZE); +#endif diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index ca11a60508..6c1ef92d1c 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -95,9 +95,10 @@ #include "bootloader_mem.h" -#if CONFIG_APP_BUILD_TYPE_ELF_RAM +#if CONFIG_APP_BUILD_TYPE_RAM #include "esp_rom_spiflash.h" -#endif // CONFIG_APP_BUILD_TYPE_ELF_RAM +#include "bootloader_init.h" +#endif // CONFIG_APP_BUILD_TYPE_RAM //This dependency will be removed in the future #include "soc/ext_mem_defs.h" @@ -176,9 +177,11 @@ void IRAM_ATTR call_start_cpu1(void) // Clear interrupt matrix for APP CPU core core_intr_matrix_clear(); +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler //has started, but it isn't active *on this CPU* yet. esp_cache_err_int_init(); +#endif #if (CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP32_TRAX_TWOBANKS) || \ (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_ESP32S3_TRAX_TWOBANKS) @@ -209,10 +212,10 @@ static void start_other_core(void) ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1); -#if CONFIG_IDF_TARGET_ESP32 +#if CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP Cache_Flush(1); Cache_Read_Enable(1); -#endif +#endif // #if CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP esp_cpu_unstall(1); @@ -288,6 +291,27 @@ void IRAM_ATTR call_start_cpu0(void) rst_reas[1] = esp_rom_get_reset_reason(1); #endif + //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this. + memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start)); + +#if defined(CONFIG_IDF_TARGET_ESP32) && defined(CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY) + // Clear IRAM BSS + memset(&_iram_bss_start, 0, (&_iram_bss_end - &_iram_bss_start) * sizeof(_iram_bss_start)); +#endif + +#if SOC_RTC_FAST_MEM_SUPPORTED || SOC_RTC_SLOW_MEM_SUPPORTED + /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */ + if (rst_reas[0] != RESET_REASON_CORE_DEEP_SLEEP) { + memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start)); + } +#endif + + // When the APP is loaded into ram for execution, some hardware initialization behaviors + // in the bootloader are still necessary +#if CONFIG_APP_BUILD_TYPE_RAM + bootloader_init(); +#endif + #ifndef CONFIG_BOOTLOADER_WDT_ENABLE // from panic handler we can be reset by RWDT or TG0WDT if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 @@ -306,21 +330,7 @@ void IRAM_ATTR call_start_cpu0(void) } #endif - //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this. - memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start)); - -#if defined(CONFIG_IDF_TARGET_ESP32) && defined(CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY) - // Clear IRAM BSS - memset(&_iram_bss_start, 0, (&_iram_bss_end - &_iram_bss_start) * sizeof(_iram_bss_start)); -#endif - -#if SOC_RTC_FAST_MEM_SUPPORTED || SOC_RTC_SLOW_MEM_SUPPORTED - /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */ - if (rst_reas[0] != RESET_REASON_CORE_DEEP_SLEEP) { - memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start)); - } -#endif - +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP #if CONFIG_IDF_TARGET_ESP32S2 /* Configure the mode of instruction cache : cache size, cache associated ways, cache line size. */ extern void esp_config_instruction_cache_mode(void); @@ -391,7 +401,6 @@ void IRAM_ATTR call_start_cpu0(void) mspi_timing_flash_tuning(); #endif - bootloader_init_mem(); #if CONFIG_SPIRAM_BOOT_INIT if (esp_psram_init() != ESP_OK) { #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY @@ -407,6 +416,9 @@ void IRAM_ATTR call_start_cpu0(void) #endif } #endif +#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + + bootloader_init_mem(); #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE s_cpu_up[0] = true; @@ -443,6 +455,7 @@ void IRAM_ATTR call_start_cpu0(void) } #endif //CONFIG_SPIRAM_MEMTEST +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP //TODO: IDF-5023, replace with MMU driver #if CONFIG_IDF_TARGET_ESP32S3 int s_instr_flash2spiram_off = 0; @@ -490,6 +503,7 @@ void IRAM_ATTR call_start_cpu0(void) esp_enable_cache_wrap(1); #endif #endif +#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); @@ -535,7 +549,9 @@ void IRAM_ATTR call_start_cpu0(void) esp_deep_sleep_wakeup_io_reset(); } +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP esp_cache_err_int_init(); +#endif #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE && !CONFIG_ESP_SYSTEM_MEMPROT_TEST // Memprot cannot be locked during OS startup as the lock-on prevents any PMS changes until a next reboot @@ -575,26 +591,26 @@ void IRAM_ATTR call_start_cpu0(void) // Read the application binary image header. This will also decrypt the header if the image is encrypted. __attribute__((unused)) esp_image_header_t fhdr = {0}; -#ifdef CONFIG_APP_BUILD_TYPE_ELF_RAM +#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP fhdr.spi_mode = ESP_IMAGE_SPI_MODE_DIO; fhdr.spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2; fhdr.spi_size = ESP_IMAGE_FLASH_SIZE_4MB; extern void esp_rom_spiflash_attach(uint32_t, bool); -#if !CONFIG_IDF_TARGET_ESP32C2 +#if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false); #else - // ESP32C2 cannot get flash_gpio_info from efuse esp_rom_spiflash_attach(0, false); -#endif // CONFIG_IDF_TARGET_ESP32C2 +#endif bootloader_flash_unlock(); #else // This assumes that DROM is the first segment in the application binary, i.e. that we can read // the binary header through cache by accessing SOC_DROM_LOW address. hal_memcpy(&fhdr, (void *) SOC_DROM_LOW, sizeof(fhdr)); -#endif // CONFIG_APP_BUILD_TYPE_ELF_RAM +#endif // CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP #if CONFIG_IDF_TARGET_ESP32 #if !CONFIG_SPIRAM_BOOT_INIT // If psram is uninitialized, we need to improve some flash configuration. @@ -613,6 +629,7 @@ void IRAM_ATTR call_start_cpu0(void) } bootloader_flash_update_size(app_flash_size); #endif //CONFIG_SPI_FLASH_SIZE_OVERRIDE +#endif //!CONFIG_APP_BUILD_TYPE_PURE_RAM_APP #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE s_cpu_inited[0] = true; diff --git a/components/esp_system/port/panic_handler.c b/components/esp_system/port/panic_handler.c index 3acf88a236..013c77a7e5 100644 --- a/components/esp_system/port/panic_handler.c +++ b/components/esp_system/port/panic_handler.c @@ -196,20 +196,22 @@ static void panic_handler(void *frame, bool pseudo_excause) * This function must always be in IRAM as it is required to * re-enable the flash cache. */ +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP static void IRAM_ATTR panic_enable_cache(void) { int core_id = esp_cpu_get_core_id(); - if (!spi_flash_cache_enabled()) { esp_ipc_isr_stall_abort(); spi_flash_enable_cache(core_id); } } +#endif void IRAM_ATTR panicHandler(void *frame) { - +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP panic_enable_cache(); +#endif // This panic handler gets called for when the double exception vector, // kernel exception vector gets used; as well as handling interrupt-based // faults cache error, wdt expiry. EXCAUSE register gets written with @@ -219,7 +221,9 @@ void IRAM_ATTR panicHandler(void *frame) void IRAM_ATTR xt_unhandled_exception(void *frame) { +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP panic_enable_cache(); +#endif panic_handler(frame, false); } diff --git a/components/esp_system/startup.c b/components/esp_system/startup.c index 2a361cbc03..73b390fca1 100644 --- a/components/esp_system/startup.c +++ b/components/esp_system/startup.c @@ -331,6 +331,7 @@ static void do_core_init(void) err = esp_pthread_init(); assert(err == ESP_OK && "Failed to init pthread module!"); +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP #if CONFIG_SPI_FLASH_ROM_IMPL spi_flash_rom_impl_init(); #endif @@ -342,6 +343,7 @@ static void do_core_init(void) #if CONFIG_SPI_FLASH_BROWNOUT_RESET spi_flash_needs_reset_check(); #endif // CONFIG_SPI_FLASH_BROWNOUT_RESET +#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP #ifdef CONFIG_EFUSE_VIRTUAL ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 095233343e..edadd478df 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -8,8 +8,8 @@ endif() set(srcs "mpu_hal.c" "efuse_hal.c" - "${target}/efuse_hal.c" - "mmu_hal.c") + "${target}/efuse_hal.c") + set(includes "${target}/include" "include" "platform_port/include") @@ -17,7 +17,11 @@ if(NOT CONFIG_HAL_WDT_USE_ROM_IMPL) list(APPEND srcs "wdt_hal_iram.c") endif() -if(NOT ${target} STREQUAL "esp32") +if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) + list(APPEND srcs "mmu_hal.c") +endif() + +if(NOT ${target} STREQUAL "esp32" AND NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) list(APPEND srcs "cache_hal.c") endif() @@ -35,13 +39,18 @@ if(NOT BOOTLOADER_BUILD) "gpio_hal.c" "uart_hal.c" "uart_hal_iram.c" - "spi_flash_hal.c" - "spi_flash_hal_iram.c" - "spi_flash_encrypt_hal_iram.c" "adc_hal_common.c" "adc_oneshot_hal.c" "${target}/clk_tree_hal.c") + if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) + list(APPEND srcs + "spi_flash_hal.c" + "spi_flash_hal_iram.c" + "spi_flash_encrypt_hal_iram.c" + ) + endif() + if(CONFIG_SOC_SYSTIMER_SUPPORTED AND NOT CONFIG_HAL_SYSTIMER_USE_ROM_IMPL) list(APPEND srcs "systimer_hal.c") endif() diff --git a/components/hal/linker.lf b/components/hal/linker.lf index 42aec03118..fe94161376 100644 --- a/components/hal/linker.lf +++ b/components/hal/linker.lf @@ -1,8 +1,11 @@ [mapping:hal] archive: libhal.a entries: - mmu_hal (noflash) - if IDF_TARGET_ESP32 = n: + if APP_BUILD_TYPE_PURE_RAM_APP = n: + mmu_hal (noflash) + spi_flash_hal_iram (noflash) + spi_flash_encrypt_hal_iram (noflash) + if IDF_TARGET_ESP32 = n && APP_BUILD_TYPE_PURE_RAM_APP = n: cache_hal (noflash) if SOC_GPSPI_SUPPORTED = y: spi_hal_iram (noflash) @@ -11,8 +14,6 @@ entries: uart_hal_iram (noflash) else: uart_hal_iram (default) - spi_flash_hal_iram (noflash) - spi_flash_encrypt_hal_iram (noflash) if SOC_LEDC_SUPPORTED = y: ledc_hal_iram (noflash) if SOC_I2C_SUPPORTED = y: diff --git a/components/newlib/assert.c b/components/newlib/assert.c index bb8449339a..5b0d80736f 100644 --- a/components/newlib/assert.c +++ b/components/newlib/assert.c @@ -47,7 +47,10 @@ void __attribute__((noreturn)) __assert_func(const char *file, int line, const c itoa(line, lbuf, 10); - if (!spi_flash_cache_enabled()) { +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + if (!spi_flash_cache_enabled()) +#endif + { if (esp_ptr_in_drom(file)) { file = CACHE_DISABLED_STR; } diff --git a/components/openthread/CMakeLists.txt b/components/openthread/CMakeLists.txt index 732d7a51ad..73569f24ff 100644 --- a/components/openthread/CMakeLists.txt +++ b/components/openthread/CMakeLists.txt @@ -1,4 +1,6 @@ if(CONFIG_OPENTHREAD_ENABLED) + idf_build_get_property(idf_target IDF_TARGET) + set(public_include_dirs "include" "openthread/include") diff --git a/components/spi_flash/CMakeLists.txt b/components/spi_flash/CMakeLists.txt index 08129892d3..c3b32e2bed 100644 --- a/components/spi_flash/CMakeLists.txt +++ b/components/spi_flash/CMakeLists.txt @@ -3,17 +3,10 @@ if(${target} STREQUAL "linux") return() endif() -if(BOOTLOADER_BUILD) +if(BOOTLOADER_BUILD OR CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) set(cache_srcs "") set(priv_requires bootloader_support soc) else() - set(cache_srcs - "cache_utils.c" - "flash_mmap.c" - "flash_ops.c" - "${target}/flash_ops_${target}.c" - ) - set(srcs "flash_brownout_hook.c") if(CONFIG_SOC_SPI_MEM_SUPPORT_OPI_MODE) @@ -38,6 +31,13 @@ else() "spi_flash_chip_th.c" "memspi_host_driver.c") + set(cache_srcs + "cache_utils.c" + "flash_mmap.c" + "flash_ops.c" + "${target}/flash_ops_${target}.c" + ) + list(APPEND cache_srcs "esp_flash_api.c" "esp_flash_spi_init.c" @@ -63,7 +63,7 @@ if(CMAKE_C_COMPILER_ID MATCHES "GNU") " -fno-inline-small-functions -fno-inline-functions-called-once") endif() -if(NOT BOOTLOADER_BUILD) +if(NOT BOOTLOADER_BUILD AND NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) if(CONFIG_SPIRAM) # [refactor-todo]: requires "esp_psram" for few MMU usages in `flash_mmap.c` # will be replaced with MMU requirements diff --git a/components/spi_flash/Kconfig b/components/spi_flash/Kconfig index 209d6e1cd4..cf73c13af1 100644 --- a/components/spi_flash/Kconfig +++ b/components/spi_flash/Kconfig @@ -1,4 +1,5 @@ menu "SPI Flash driver" + depends on !APP_BUILD_TYPE_PURE_RAM_APP config SPI_FLASH_VERIFY_WRITE bool "Verify SPI flash writes" diff --git a/components/spi_flash/linker.lf b/components/spi_flash/linker.lf index 62130ab71a..1d9a112655 100644 --- a/components/spi_flash/linker.lf +++ b/components/spi_flash/linker.lf @@ -1,19 +1,20 @@ [mapping:spi_flash] archive: libspi_flash.a entries: - spi_flash_chip_generic (noflash) - spi_flash_chip_issi (noflash) - spi_flash_chip_mxic (noflash) - spi_flash_chip_gd (noflash) - spi_flash_chip_winbond (noflash) - spi_flash_chip_boya (noflash) - spi_flash_chip_th (noflash) - memspi_host_driver (noflash) - flash_brownout_hook (noflash) + if APP_BUILD_TYPE_PURE_RAM_APP = n: + spi_flash_chip_generic (noflash) + spi_flash_chip_issi (noflash) + spi_flash_chip_mxic (noflash) + spi_flash_chip_gd (noflash) + spi_flash_chip_winbond (noflash) + spi_flash_chip_boya (noflash) + spi_flash_chip_th (noflash) + memspi_host_driver (noflash) + flash_brownout_hook (noflash) - if IDF_TARGET_ESP32S3 = y: - spi_flash_chip_mxic_opi (noflash) - spi_flash_hpm_enable (noflash) + if IDF_TARGET_ESP32S3 = y: + spi_flash_chip_mxic_opi (noflash) + spi_flash_hpm_enable (noflash) - if ESPTOOLPY_OCT_FLASH = y || ESPTOOLPY_FLASH_MODE_AUTO_DETECT = y: - spi_flash_oct_flash_init (noflash) + if ESPTOOLPY_OCT_FLASH = y || ESPTOOLPY_FLASH_MODE_AUTO_DETECT = y: + spi_flash_oct_flash_init (noflash)