alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

components/bt: Disable exception mode after saving special registers

Browse Source 
To store some registers first, avoid stuck due to live lock after disabling exception mode
This commit is contained in:
baohongde 2020-05-30 17:29:25 +08:00 committed by maojianxin
parent 5e6824e3ea
commit 44985f00d3
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
components/bt/hli_vectors.S
View File

@ -39,11 +39,6 @@ _l4_save_ctx:
.type xt_highint4,@function .type xt_highint4,@function
.align 4 .align 4
xt_highint4: xt_highint4:
/* disable exception mode, window overflow */
movi a0, PS_INTLEVEL(5) | PS_EXCM /*TOCHECK*/
wsr a0, PS
rsync
movi a0, _l4_save_ctx movi a0, _l4_save_ctx
/* save 4 lower registers */ /* save 4 lower registers */
s32i a1, a0, 4 s32i a1, a0, 4
@ -69,6 +64,11 @@ xt_highint4:
rsr a2, EPC1 rsr a2, EPC1
s32i a2, a0, 24 s32i a2, a0, 24
/* disable exception mode, window overflow */
movi a0, PS_INTLEVEL(5) | PS_EXCM /*TOCHECK*/
wsr a0, PS
rsync
/* Save the remaining physical registers. /* Save the remaining physical registers.
* 4 registers are already saved, which leaves 60 registers to save. * 4 registers are already saved, which leaves 60 registers to save.
* (FIXME: consider the case when the CPU is configured with physical 32 registers) * (FIXME: consider the case when the CPU is configured with physical 32 registers)