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Merge branch 'feat/flash_p4' into 'master'

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ci(spi_flash): Enable spi_flash related tests on esp32p4

Closes IDF-7499 and IDF-8984

See merge request espressif/esp-idf!28099
This commit is contained in:
C.S.M 2024-01-08 14:28:09 +08:00
commit 43c87716c9
33 changed files with 685 additions and 5253 deletions
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17
components/bootloader_support/bootloader_flash/src/bootloader_flash.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -13,16 +13,21 @@
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
#include "hal/spi_flash_ll.h"
#include "rom/spi_flash.h"
#if CONFIG_IDF_TARGET_ESP32
# include "soc/spi_struct.h"
# include "soc/spi_reg.h"
/* SPI flash controller */
# define SPIFLASH SPI1
# define SPI0 SPI0
#else
# include "hal/spimem_flash_ll.h"
# include "soc/spi_mem_struct.h"
# include "soc/spi_mem_reg.h"
/* SPI flash controller */
# define SPIFLASH SPIMEM1
# define SPI0 SPIMEM0
#endif
// This dependency will be removed in the future. IDF-5025
@ -581,10 +586,12 @@ IRAM_ATTR uint32_t bootloader_flash_execute_command_common(
uint32_t old_user_reg = SPIFLASH.user.val;
uint32_t old_user1_reg = SPIFLASH.user1.val;
uint32_t old_user2_reg = SPIFLASH.user2.val;
// Clear ctrl regs.
SPIFLASH.ctrl.val = 0;
#if CONFIG_IDF_TARGET_ESP32
SPIFLASH.ctrl.val = SPI_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
spi_flash_ll_set_wp_level(&SPIFLASH, true);
#else
SPIFLASH.ctrl.val = SPI_MEM_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
spimem_flash_ll_set_wp_level(&SPIFLASH, true);
#endif
//command phase
SPIFLASH.user.usr_command = 1;
@ -634,6 +641,7 @@ IRAM_ATTR uint32_t bootloader_flash_execute_command_common(
//set unused bits to 0
ret &= ~(UINT32_MAX << miso_len);
}
esp_rom_printf("val is %x\n", SPIFLASH.ctrl.val);
return ret;
}
@ -832,8 +840,8 @@ bool IRAM_ATTR bootloader_flash_is_octal_mode_enabled(void)
esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
{
esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPI0);
#if CONFIG_IDF_TARGET_ESP32
uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
if (spi_ctrl & SPI_FREAD_QIO) {
spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
} else if (spi_ctrl & SPI_FREAD_QUAD) {
@ -848,7 +856,6 @@ esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
spi_mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
}
#else
uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
if (spi_ctrl & SPI_MEM_FREAD_QIO) {
spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {

8
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -30,9 +30,9 @@ void bootloader_flash_update_id()
void IRAM_ATTR bootloader_flash_cs_timing_config()
{
SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
SET_PERI_REG_MASK(SPI_MEM_C_USER_REG, SPI_MEM_C_CS_HOLD_M | SPI_MEM_C_CS_SETUP_M);
SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_HOLD_TIME_V, 0, SPI_MEM_C_CS_HOLD_TIME_S);
SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_SETUP_TIME_V, 0, SPI_MEM_C_CS_SETUP_TIME_S);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)

47
components/esp_rom/include/esp32p4/rom/spi_flash.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -15,23 +15,34 @@
extern "C" {
#endif
#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1)
#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1)
#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1)
#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1)
#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1)
#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1)
#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1)
#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1)
#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1)
#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1)
#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1)
#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1)
#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1)
#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1)
#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1)
#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1)
#define PERIPHS_SPI_FLASH_CMD SPI1_MEM_C_CMD_REG
#define PERIPHS_SPI_FLASH_ADDR SPI1_MEM_C_ADDR_REG
#define PERIPHS_SPI_FLASH_CTRL SPI1_MEM_C_CTRL_REG
#define PERIPHS_SPI_FLASH_CTRL1 SPI1_MEM_C_CTRL1_REG
#define PERIPHS_SPI_FLASH_STATUS SPI1_MEM_C_RD_STATUS_REG
#define PERIPHS_SPI_FLASH_USRREG SPI1_MEM_C_USER_REG
#define PERIPHS_SPI_FLASH_USRREG1 SPI1_MEM_C_USER1_REG
#define PERIPHS_SPI_FLASH_USRREG2 SPI1_MEM_C_USER2_REG
#define PERIPHS_SPI_FLASH_C0 SPI1_MEM_C_W0_REG
#define PERIPHS_SPI_FLASH_C1 SPI1_MEM_C_W1_REG
#define PERIPHS_SPI_FLASH_C2 SPI1_MEM_C_W2_REG
#define PERIPHS_SPI_FLASH_C3 SPI1_MEM_C_W3_REG
#define PERIPHS_SPI_FLASH_C4 SPI1_MEM_C_W4_REG
#define PERIPHS_SPI_FLASH_C5 SPI1_MEM_C_W5_REG
#define PERIPHS_SPI_FLASH_C6 SPI1_MEM_C_W6_REG
#define PERIPHS_SPI_FLASH_C7 SPI1_MEM_C_W7_REG
#define PERIPHS_SPI_FLASH_TX_CRC SPI1_MEM_C_TX_CRC_REG
#define SPI_MEM_FREAD_QIO SPI1_MEM_C_FREAD_QIO
#define SPI_MEM_FREAD_DIO SPI1_MEM_C_FREAD_DIO
#define SPI_MEM_FREAD_QUAD SPI1_MEM_C_FREAD_QUAD
#define SPI_MEM_FREAD_DUAL SPI1_MEM_C_FREAD_DUAL
#define SPI_MEM_FWRITE_QIO SPI1_MEM_C_FWRITE_QIO
#define SPI_MEM_FWRITE_DIO SPI1_MEM_C_FWRITE_DIO
#define SPI_MEM_FWRITE_QUAD SPI1_MEM_C_FWRITE_QUAD
#define SPI_MEM_FWRITE_DUAL SPI1_MEM_C_FWRITE_DUAL
#define SPI_MEM_FASTRD_MODE SPI1_MEM_C_FASTRD_MODE
#define SPI0_R_QIO_DUMMY_CYCLELEN 5
#define SPI0_R_QIO_ADDR_BITSLEN 23

22
components/hal/esp32/include/hal/spi_flash_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -447,6 +447,26 @@ static inline void spi_flash_ll_set_extra_address(spi_dev_t *dev, uint32_t extra
// Not supported on ESP32.
}
/**
* @brief Write protect signal output when SPI is idle
* @param level 1: 1: output high, 0: output low
*/
static inline void spi_flash_ll_set_wp_level(spi_dev_t *dev, bool level)
{
dev->ctrl.wp = level;
}
/**
* @brief Get the ctrl value of mspi
*
* @return uint32_t The value of ctrl register
*/
static inline uint32_t spi_flash_ll_get_ctrl_val(spi_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}
#endif

1
components/hal/esp32c2/include/hal/spi_flash_ll.h
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@ -91,6 +91,7 @@ typedef union {
#define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#endif

22
components/hal/esp32c2/include/hal/spimem_flash_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -647,6 +647,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
return div_parameter;
}
/**
* @brief Write protect signal output when SPI is idle
* @param level 1: 1: output high, 0: output low
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp = level;
}
/**
* @brief Get the ctrl value of mspi
*
* @return uint32_t The value of ctrl register
*/
static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}
#endif

1
components/hal/esp32c3/include/hal/spi_flash_ll.h
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@ -91,6 +91,7 @@ typedef union {
#define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#endif

22
components/hal/esp32c3/include/hal/spimem_flash_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -662,6 +662,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
return div_parameter;
}
/**
* @brief Write protect signal output when SPI is idle
* @param level 1: 1: output high, 0: output low
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp = level;
}
/**
* @brief Get the ctrl value of mspi
*
* @return uint32_t The value of ctrl register
*/
static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}
#endif

1
components/hal/esp32c5/include/hal/spi_flash_ll.h
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@ -94,6 +94,7 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#endif

22
components/hal/esp32c5/include/hal/spimem_flash_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -651,6 +651,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
return div_parameter;
}
/**
* @brief Write protect signal output when SPI is idle
* @param level 1: 1: output high, 0: output low
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp = level;
}
/**
* @brief Get the ctrl value of mspi
*
* @return uint32_t The value of ctrl register
*/
static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}
#endif

1
components/hal/esp32c6/include/hal/spi_flash_ll.h
View File

@ -92,6 +92,7 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#endif

22
components/hal/esp32c6/include/hal/spimem_flash_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -681,6 +681,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
return div_parameter;
}
/**
* @brief Write protect signal output when SPI is idle
* @param level 1: 1: output high, 0: output low
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp = level;
}
/**
* @brief Get the ctrl value of mspi
*
* @return uint32_t The value of ctrl register
*/
static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}
#endif

1
components/hal/esp32h2/include/hal/spi_flash_ll.h
View File

@ -92,6 +92,7 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#endif

22
components/hal/esp32h2/include/hal/spimem_flash_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -683,6 +683,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
return div_parameter;
}
/**
* @brief Write protect signal output when SPI is idle
* @param level 1: 1: output high, 0: output low
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp = level;
}
/**
* @brief Get the ctrl value of mspi
*
* @return uint32_t The value of ctrl register
*/
static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}
#endif

22
components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -15,7 +15,7 @@
#include <stdbool.h>
#include <string.h>
#include "soc/hp_system_reg.h"
#include "soc/spi_mem_reg.h"
#include "soc/spi_mem_c_reg.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "hal/assert.h"
@ -61,7 +61,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
{
// Our hardware only support flash encryption
HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_SPI_XTS_DESTINATION, type);
REG_SET_FIELD(SPI_MEM_C_XTS_DESTINATION_REG, SPI_MEM_C_XTS_DESTINATION, type);
}
/**
@ -72,7 +72,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
{
// Desired block should not be larger than the block size.
REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_SPI_XTS_LINESIZE, size >> 5);
REG_SET_FIELD(SPI_MEM_C_XTS_LINESIZE_REG, SPI_MEM_C_XTS_LINESIZE, size >> 5);
}
/**
@ -87,7 +87,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
{
uint32_t plaintext_offs = (address % SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
HAL_ASSERT(plaintext_offs + size <= SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size);
memcpy((void *)(SPI_MEM_C_XTS_PLAIN_BASE_REG + plaintext_offs), buffer, size);
}
/**
@ -97,7 +97,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
*/
static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
{
REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS, flash_addr);
REG_SET_FIELD(SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG, SPI_MEM_C_XTS_PHYSICAL_ADDRESS, flash_addr);
}
/**
@ -105,7 +105,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
*/
static inline void spi_flash_encrypt_ll_calculate_start(void)
{
REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_SPI_XTS_TRIGGER, 1);
REG_SET_FIELD(SPI_MEM_C_XTS_TRIGGER_REG, SPI_XTS_TRIGGER, 1);
}
/**
@ -113,7 +113,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_SPI_XTS_STATE) == 0x1) {
while(REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) == 0x1) {
}
}
@ -122,8 +122,8 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
*/
static inline void spi_flash_encrypt_ll_done(void)
{
REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_SPI_XTS_RELEASE);
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_SPI_XTS_STATE) != 0x3) {
REG_SET_BIT(SPI_MEM_C_XTS_RELEASE_REG, SPI_MEM_C_XTS_RELEASE);
while(REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) != 0x3) {
}
}
@ -132,7 +132,7 @@ static inline void spi_flash_encrypt_ll_done(void)
*/
static inline void spi_flash_encrypt_ll_destroy(void)
{
REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_SPI_XTS_DESTROY);
REG_SET_BIT(SPI_MEM_C_XTS_DESTROY_REG, SPI_MEM_C_XTS_DESTROY);
}
/**

1
components/hal/esp32p4/include/hal/spi_flash_ll.h
View File

@ -92,6 +92,7 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#endif

43
components/hal/esp32p4/include/hal/spimem_flash_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -20,7 +20,8 @@
#include <string.h>
#include "soc/spi_periph.h"
#include "soc/spi_mem_struct.h"
#include "soc/spi1_mem_c_struct.h"
#include "soc/spi1_mem_c_reg.h"
#include "hal/assert.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
@ -208,7 +209,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool
*/
static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf)
{
dev->flash_sus_ctrl.frd_sus_2b = 0;
dev->flash_sus_ctrl.fmem_rd_sus_2b = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf);
}
@ -454,8 +455,8 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
{
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
ctrl.val &= ~(SPI1_MEM_C_FREAD_QIO_M | SPI1_MEM_C_FREAD_QUAD_M | SPI1_MEM_C_FREAD_DIO_M | SPI1_MEM_C_FREAD_DUAL_M);
ctrl.val |= SPI1_MEM_C_FASTRD_MODE_M;
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
@ -565,7 +566,7 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
*/
static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
{
dev->cache_fctrl.usr_addr_4byte = 0;
dev->cache_fctrl.cache_usr_addr_4byte = 0;
dev->rd_status.wb_mode = extra_addr;
}
@ -612,10 +613,7 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_
*/
static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
{
if (hold_n > 0) {
dev->ctrl2.cs_hold_time = hold_n - 1;
}
dev->user.cs_hold = hold_n > 0;
// Not supported on esp32p4
}
/**
@ -626,10 +624,7 @@ static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
*/
static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
{
if (cs_setup_time > 0) {
dev->ctrl2.cs_setup_time = cs_setup_time - 1;
}
dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
// Not supported on esp32p4
}
/**
@ -664,6 +659,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
return div_parameter;
}
/**
* @brief Write protect signal output when SPI is idle
* @param level 1: 1: output high, 0: output low
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp_reg = level;
}
/**
* @brief Get the ctrl value of mspi
*
* @return uint32_t The value of ctrl register
*/
static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}
#endif

1
components/hal/esp32s2/include/hal/spi_flash_ll.h
View File

@ -94,6 +94,7 @@ typedef union {
#define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#endif

21
components/hal/esp32s2/include/hal/spimem_flash_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -596,6 +596,25 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
return div_parameter;
}
/**
* @brief Write protect signal output when SPI is idle
* @param level 1: 1: output high, 0: output low
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp = level;
}
/**
* @brief Get the ctrl value of mspi
*
* @return uint32_t The value of ctrl register
*/
static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}

2
components/hal/esp32s3/include/hal/spi_flash_ll.h
View File

@ -91,6 +91,8 @@ typedef union {
#define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#endif
#ifdef __cplusplus

22
components/hal/esp32s3/include/hal/spimem_flash_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -683,6 +683,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
return div_parameter;
}
/**
* @brief Write protect signal output when SPI is idle
* @param level 1: 1: output high, 0: output low
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp = level;
}
/**
* @brief Get the ctrl value of mspi
*
* @return uint32_t The value of ctrl register
*/
static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
{
return dev->ctrl.val;
}
#ifdef __cplusplus
}
#endif

2
components/soc/esp32p4/include/soc/spi1_mem_c_reg.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

241
components/soc/esp32p4/include/soc/spi1_mem_c_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -393,10 +393,10 @@ typedef union {
*/
typedef union {
struct {
/** usr_mosi_dbitlen : R/W; bitpos: [9:0]; default: 0;
/** usr_mosi_bit_len : R/W; bitpos: [9:0]; default: 0;
* The length in bits of write-data. The register value shall be (bit_num-1).
*/
uint32_t usr_mosi_dbitlen:10;
uint32_t usr_mosi_bit_len:10;
uint32_t reserved_10:22;
};
uint32_t val;
@ -407,10 +407,10 @@ typedef union {
*/
typedef union {
struct {
/** usr_miso_dbitlen : R/W; bitpos: [9:0]; default: 0;
/** usr_miso_bit_len : R/W; bitpos: [9:0]; default: 0;
* The length in bits of read-data. The register value shall be (bit_num-1).
*/
uint32_t usr_miso_dbitlen:10;
uint32_t usr_miso_bit_len:10;
uint32_t reserved_10:22;
};
uint32_t val;
@ -807,217 +807,6 @@ typedef union {
uint32_t val;
} spi1_mem_c_tx_crc_reg_t;
/** Group: Memory data buffer register */
/** Type of w0 register
* SPI1 memory data buffer0
*/
typedef union {
struct {
/** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf0:32;
};
uint32_t val;
} spi1_mem_c_w0_reg_t;
/** Type of w1 register
* SPI1 memory data buffer1
*/
typedef union {
struct {
/** buf1 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf1:32;
};
uint32_t val;
} spi1_mem_c_w1_reg_t;
/** Type of w2 register
* SPI1 memory data buffer2
*/
typedef union {
struct {
/** buf2 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf2:32;
};
uint32_t val;
} spi1_mem_c_w2_reg_t;
/** Type of w3 register
* SPI1 memory data buffer3
*/
typedef union {
struct {
/** buf3 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf3:32;
};
uint32_t val;
} spi1_mem_c_w3_reg_t;
/** Type of w4 register
* SPI1 memory data buffer4
*/
typedef union {
struct {
/** buf4 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf4:32;
};
uint32_t val;
} spi1_mem_c_w4_reg_t;
/** Type of w5 register
* SPI1 memory data buffer5
*/
typedef union {
struct {
/** buf5 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf5:32;
};
uint32_t val;
} spi1_mem_c_w5_reg_t;
/** Type of w6 register
* SPI1 memory data buffer6
*/
typedef union {
struct {
/** buf6 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf6:32;
};
uint32_t val;
} spi1_mem_c_w6_reg_t;
/** Type of w7 register
* SPI1 memory data buffer7
*/
typedef union {
struct {
/** buf7 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf7:32;
};
uint32_t val;
} spi1_mem_c_w7_reg_t;
/** Type of w8 register
* SPI1 memory data buffer8
*/
typedef union {
struct {
/** buf8 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf8:32;
};
uint32_t val;
} spi1_mem_c_w8_reg_t;
/** Type of w9 register
* SPI1 memory data buffer9
*/
typedef union {
struct {
/** buf9 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf9:32;
};
uint32_t val;
} spi1_mem_c_w9_reg_t;
/** Type of w10 register
* SPI1 memory data buffer10
*/
typedef union {
struct {
/** buf10 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf10:32;
};
uint32_t val;
} spi1_mem_c_w10_reg_t;
/** Type of w11 register
* SPI1 memory data buffer11
*/
typedef union {
struct {
/** buf11 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf11:32;
};
uint32_t val;
} spi1_mem_c_w11_reg_t;
/** Type of w12 register
* SPI1 memory data buffer12
*/
typedef union {
struct {
/** buf12 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf12:32;
};
uint32_t val;
} spi1_mem_c_w12_reg_t;
/** Type of w13 register
* SPI1 memory data buffer13
*/
typedef union {
struct {
/** buf13 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf13:32;
};
uint32_t val;
} spi1_mem_c_w13_reg_t;
/** Type of w14 register
* SPI1 memory data buffer14
*/
typedef union {
struct {
/** buf14 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf14:32;
};
uint32_t val;
} spi1_mem_c_w14_reg_t;
/** Type of w15 register
* SPI1 memory data buffer15
*/
typedef union {
struct {
/** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf15:32;
};
uint32_t val;
} spi1_mem_c_w15_reg_t;
/** Group: Interrupt registers */
/** Type of int_ena register
* SPI1 interrupt enable register
@ -1208,7 +997,7 @@ typedef union {
typedef struct spi1_mem_c_dev_s {
volatile spi1_mem_c_cmd_reg_t cmd;
volatile spi1_mem_c_addr_reg_t addr;
volatile uint32_t addr;
volatile spi1_mem_c_ctrl_reg_t ctrl;
volatile spi1_mem_c_ctrl1_reg_t ctrl1;
volatile spi1_mem_c_ctrl2_reg_t ctrl2;
@ -1224,22 +1013,7 @@ typedef struct spi1_mem_c_dev_s {
volatile spi1_mem_c_tx_crc_reg_t tx_crc;
volatile spi1_mem_c_cache_fctrl_reg_t cache_fctrl;
uint32_t reserved_040[6];
volatile spi1_mem_c_w0_reg_t w0;
volatile spi1_mem_c_w1_reg_t w1;
volatile spi1_mem_c_w2_reg_t w2;
volatile spi1_mem_c_w3_reg_t w3;
volatile spi1_mem_c_w4_reg_t w4;
volatile spi1_mem_c_w5_reg_t w5;
volatile spi1_mem_c_w6_reg_t w6;
volatile spi1_mem_c_w7_reg_t w7;
volatile spi1_mem_c_w8_reg_t w8;
volatile spi1_mem_c_w9_reg_t w9;
volatile spi1_mem_c_w10_reg_t w10;
volatile spi1_mem_c_w11_reg_t w11;
volatile spi1_mem_c_w12_reg_t w12;
volatile spi1_mem_c_w13_reg_t w13;
volatile spi1_mem_c_w14_reg_t w14;
volatile spi1_mem_c_w15_reg_t w15;
volatile uint32_t data_buf[16];
volatile spi1_mem_c_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
volatile spi1_mem_c_flash_sus_ctrl_reg_t flash_sus_ctrl;
volatile spi1_mem_c_flash_sus_cmd_reg_t flash_sus_cmd;
@ -1259,7 +1033,6 @@ typedef struct spi1_mem_c_dev_s {
volatile spi1_mem_c_date_reg_t date;
} spi1_mem_c_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(spi1_mem_c_dev_t) == 0x400, "Invalid size of spi1_mem_c_dev_t structure");
#endif

746
components/soc/esp32p4/include/soc/spi_mem_c_struct.h
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File diff suppressed because it is too large Load Diff

3443
components/soc/esp32p4/include/soc/spi_mem_reg.h
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File diff suppressed because it is too large Load Diff

1132
components/soc/esp32p4/include/soc/spi_mem_struct.h
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File diff suppressed because it is too large Load Diff

2
components/soc/include/soc/spi_periph.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

13
components/spi_flash/spi_flash_wrap.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -12,6 +12,7 @@
#include "spi_flash_defs.h"
#include "esp_rom_sys.h"
#include "esp_rom_spiflash.h"
#include "rom/spi_flash.h"
#include "spi_flash_override.h"
#include "esp_private/spi_flash_os.h"
@ -87,9 +88,9 @@ esp_err_t spi_flash_wrap_enable_77(spi_flash_wrap_size_t wrap_size)
{
uint8_t wrap_code = (uint8_t) (((__builtin_ctz(wrap_size) - 3) * 2) << 4);
// According to the special format, we need enable QIO_FWRITE for command 77h and clear it after this command is done.
REG_SET_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO);
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO);
bootloader_flash_execute_command_common(CMD_WRAP, 0, 0, 6, 8, wrap_code, 0);
REG_CLR_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO);
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO);
return ESP_OK;
}
@ -110,9 +111,9 @@ esp_err_t spi_flash_wrap_clear_c0(void)
esp_err_t spi_flash_wrap_clear_77(void)
{
// According to the special format, we need enable QIO_FWRITE for command 77h and clear it after this command is done.
REG_SET_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO);
REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO);
bootloader_flash_execute_command_common(CMD_WRAP, 0, 0, 6, 8, 0x10, 0);
REG_CLR_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO);
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO);
return ESP_OK;
}
@ -153,7 +154,7 @@ esp_err_t spi_flash_wrap_disable(void)
bool spi_flash_support_wrap_size(uint32_t wrap_size)
{
// Only QIO mode supports wrap.
if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO)) {
if (!REG_GET_BIT(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO)) {
ESP_EARLY_LOGE(FLASH_WRAP_TAG, "flash wrap is only supported in QIO mode");
abort();
}

7
components/spi_flash/test_apps/.build-test-rules.yml
View File

@ -1,10 +1,6 @@
# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
components/spi_flash/test_apps/esp_flash:
disable:
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: target esp32p4 is not supported yet # TODO: IDF-7499
depends_filepatterns:
- components/bootloader_support/bootloader_flash/**/*
depends_components:
@ -28,9 +24,6 @@ components/spi_flash/test_apps/flash_encryption:
components/spi_flash/test_apps/flash_suspend:
disable:
- if: SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND != 1
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: target esp32p4 is not supported yet # TODO: IDF-7499
disable_test:
- if: IDF_TARGET != "esp32c3"
temporary: true

4
components/spi_flash/test_apps/esp_flash/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

20
components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
@ -97,6 +97,24 @@
#define FSPI_PIN_NUM_WP 5
#define FSPI_PIN_NUM_CS 17
// Just use the same pins for HSPI
#define HSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI
#define HSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO
#define HSPI_PIN_NUM_CLK FSPI_PIN_NUM_CLK
#define HSPI_PIN_NUM_HD FSPI_PIN_NUM_HD
#define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP
#define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS
#elif CONFIG_IDF_TARGET_ESP32P4
// Normal IOMUX pins
#define FSPI_PIN_NUM_MOSI 8
#define FSPI_PIN_NUM_MISO 10
#define FSPI_PIN_NUM_CLK 9
#define FSPI_PIN_NUM_HD 6
#define FSPI_PIN_NUM_WP 11
#define FSPI_PIN_NUM_CS 7
// Just use the same pins for HSPI
#define HSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI
#define HSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO

2
components/spi_flash/test_apps/esp_flash/main/test_spi_flash.c
View File

@ -122,7 +122,7 @@ TEST_CASE("flash write and erase work both on PRO CPU and on APP CPU", "[spi_fla
}
// TODO: This test is disabled on S3 with legacy impl - IDF-3505
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3, ESP32C3)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32P4)
#if portNUM_PROCESSORS > 1
TEST_CASE("spi_flash deadlock with high priority busy-waiting task", "[spi_flash][esp_flash]")

1
components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py
View File

@ -6,7 +6,6 @@ from pytest_embedded import Dut
@pytest.mark.supported_targets
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='esp32p4 support TBD') # TODO: IDF-8984
@pytest.mark.generic
@pytest.mark.parametrize(
'config',