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esp-eth: emac: Reset Tx DMA channel owner on init
Reset ethernet TX DMA descriptors sets owner to CPU, so re-installing the ethernet driver will now not result in packet loss Merges https://github.com/espressif/esp-idf/pull/7752
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@ -1,16 +1,8 @@
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// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
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/*
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//
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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// Licensed under the Apache License, Version 2.0 (the "License");
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*
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// you may not use this file except in compliance with the License.
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* SPDX-License-Identifier: Apache-2.0
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// You may obtain a copy of the License at
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*/
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include <string.h>
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#include "sdkconfig.h"
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_attr.h"
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@ -166,7 +158,7 @@ void emac_hal_reset_desc_chain(emac_hal_context_t *hal)
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/* init rx chain */
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/* init rx chain */
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for (int i = 0; i < CONFIG_ETH_DMA_RX_BUFFER_NUM; i++) {
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for (int i = 0; i < CONFIG_ETH_DMA_RX_BUFFER_NUM; i++) {
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/* Set Own bit of the Rx descriptor Status: DMA */
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/* Set Own bit of the Rx descriptor Status: DMA */
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hal->rx_desc[i].RDES0.Own = 1;
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hal->rx_desc[i].RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
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/* Set Buffer1 size and Second Address Chained bit */
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/* Set Buffer1 size and Second Address Chained bit */
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hal->rx_desc[i].RDES1.SecondAddressChained = 1;
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hal->rx_desc[i].RDES1.SecondAddressChained = 1;
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hal->rx_desc[i].RDES1.ReceiveBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
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hal->rx_desc[i].RDES1.ReceiveBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
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@ -182,7 +174,8 @@ void emac_hal_reset_desc_chain(emac_hal_context_t *hal)
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/* init tx chain */
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/* init tx chain */
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for (int i = 0; i < CONFIG_ETH_DMA_TX_BUFFER_NUM; i++) {
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for (int i = 0; i < CONFIG_ETH_DMA_TX_BUFFER_NUM; i++) {
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/* Set Second Address Chained bit */
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/* Set Own bit of the Tx descriptor Status: CPU */
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hal->tx_desc[i].TDES0.Own = EMAC_LL_DMADESC_OWNER_CPU;
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hal->tx_desc[i].TDES0.SecondAddressChained = 1;
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hal->tx_desc[i].TDES0.SecondAddressChained = 1;
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hal->tx_desc[i].TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
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hal->tx_desc[i].TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
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/* Enable Ethernet DMA Tx Descriptor interrupt */
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/* Enable Ethernet DMA Tx Descriptor interrupt */
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