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hal: Adds cache hal
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KonstantinKondrashov
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95
components/hal/esp32/include/hal/cache_ll.h
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95
components/hal/esp32/include/hal/cache_ll.h
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/dport_reg.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Enable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be enabled
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* @param enable 1: enable; 0: disable
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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(void) mask;
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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uint32_t bus_mask = 0;
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if (cache_id == 0) {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
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} else {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
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}
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}
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/**
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* Disable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be enabled
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* @param enable 1: enable; 0: disable
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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(void) mask;
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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uint32_t bus_mask = 0;
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if (cache_id == 0) {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
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} else {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
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}
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}
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#ifdef __cplusplus
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}
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#endif
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84
components/hal/esp32s3/include/hal/cache_ll.h
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84
components/hal/esp32s3/include/hal/cache_ll.h
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include "soc/extmem_reg.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Enable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be enabled
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
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HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
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uint32_t ibus_mask = 0;
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if (cache_id == 0) {
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0;
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} else {
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0;
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}
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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if (cache_id == 1) {
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0;
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} else {
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0;
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}
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REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask);
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}
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/**
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* Disable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be disabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
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HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
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uint32_t ibus_mask = 0;
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if (cache_id == 0) {
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0;
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} else {
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0;
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}
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REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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if (cache_id == 1) {
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0;
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} else {
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0;
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}
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REG_SET_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask);
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}
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#ifdef __cplusplus
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}
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#endif
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33
components/hal/include/hal/cache_types.h
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33
components/hal/include/hal/cache_types.h
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/*
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* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "esp_bit_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Ibuses and Dbuses.
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*
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* @note
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* These enumurations are abstract concepts. Virtual address reside in one of these buses.
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* Therefore, use `cache_ll_l1_get_bus(cache_id, vaddr_start, len)` to convert your vaddr into buses first
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*/
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typedef enum {
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CACHE_BUS_IBUS0 = BIT(0),
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CACHE_BUS_IBUS1 = BIT(1),
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CACHE_BUS_IBUS2 = BIT(2),
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CACHE_BUS_DBUS0 = BIT(3),
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CACHE_BUS_DBUS1 = BIT(4),
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CACHE_BUS_DBUS2 = BIT(5),
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} cache_bus_mask_t;
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#ifdef __cplusplus
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}
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#endif
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