alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

uart: fix esp32c3 uart output garbage value after resetting

Browse Source
This commit is contained in:
Wangjialin 2021-03-16 00:50:31 +08:00 committed by Chen Yi Qun
parent cba6f1ae66
commit 427fe1bcde
5 changed files with 30 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
components/driver/uart.c
View File

@ -197,10 +197,19 @@ static void uart_module_enable(uart_port_t uart_num)
{
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
if (uart_context[uart_num].hw_enabled != true) {
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
periph_module_reset(uart_periph_signal[uart_num].module);
}
periph_module_enable(uart_periph_signal[uart_num].module);
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
// Workaround for ESP32C3: enable core reset
// before enabling uart module clock
// to prevent uart output garbage value.
#if SOC_UART_REQUIRE_CORE_RESET
uart_hal_set_reset_core(&(uart_context[uart_num].hal), true);
periph_module_reset(uart_periph_signal[uart_num].module);
uart_hal_set_reset_core(&(uart_context[uart_num].hal), false);
#else
periph_module_reset(uart_periph_signal[uart_num].module);
#endif
}
uart_context[uart_num].hw_enabled = true;
}
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));

5
components/esp32c3/system_api_esp32c3.c
View File

@ -31,6 +31,7 @@
#include "soc/rtc.h"
#include "soc/syscon_reg.h"
#include "soc/system_reg.h"
#include "soc/uart_reg.h"
#include "hal/wdt_hal.h"
/* "inner" restart function for after RTOS, interrupts & anything else on this
@ -99,6 +100,10 @@ void IRAM_ATTR esp_restart_noos(void)
REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
// Reset uart0 core first, then reset apb side.
// rom will clear this bit, as well as SYSTEM_UART_RST
SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M);
// Reset timer/spi/uart
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);

5
components/hal/esp32c3/include/hal/uart_ll.h
View File

@ -58,9 +58,8 @@ typedef enum {
UART_INTR_CMD_CHAR_DET = (0x1 << 18),
} uart_intr_t;
static inline void uart_ll_reset_core(uart_dev_t *hw) {
hw->clk_conf.rst_core = 1;
hw->clk_conf.rst_core = 0;
static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) {
hw->clk_conf.rst_core = core_rst_en;
}
static inline void uart_ll_sclk_enable(uart_dev_t *hw) {

10
components/hal/include/hal/uart_hal.h
View File

@ -124,6 +124,16 @@ typedef struct {
*/
#define uart_hal_is_tx_idle(hal) uart_ll_is_tx_idle((hal)->dev)
/**
* @brief Configure the UART core reset
*
* @param hal Context of the HAL layer
* @param Set true to enable the core reset, otherwise set it false
*
* @return None
*/
#define uart_hal_set_reset_core(hal, core_rst_en) uart_ll_set_reset_core((hal)->dev, core_rst_en)
/**
* @brief Read data from the UART rxfifo
*

1
components/soc/esp32c3/include/soc/soc_caps.h
View File

@ -229,6 +229,7 @@
#define SOC_UART_SUPPORT_RTC_CLK (1)
#define SOC_UART_SUPPORT_XTAL_CLK (1)
#define SOC_UART_REQUIRE_CORE_RESET (1)
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)