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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
fix(spi): Correct REG_SPI_BASE(i) macro for all targets
The existing formula can never match these registers. Closes https://github.com/espressif/esp-idf/pull/12559 Closes https://github.com/espressif/esp-idf/pull/12562
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@ -75,6 +75,7 @@
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#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000)
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#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
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#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
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//Registers Operation {{
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//Registers Operation {{
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@ -1,24 +1,16 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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/*
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//
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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// Licensed under the Apache License, Version 2.0 (the "License");
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*
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// you may not use this file except in compliance with the License.
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* SPDX-License-Identifier: Apache-2.0
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// You may obtain a copy of the License at
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*/
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SPI_REG_H_
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#ifndef _SOC_SPI_REG_H_
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#define _SOC_SPI_REG_H_
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#define _SOC_SPI_REG_H_
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#include "soc.h"
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#ifdef __cplusplus
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#ifdef __cplusplus
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extern "C" {
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extern "C" {
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#endif
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#endif
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#include "soc.h"
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#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
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#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
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/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
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/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
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@ -21,10 +21,8 @@ PROVIDE ( TIMERG0 = 0x6001F000 );
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PROVIDE ( TIMERG1 = 0x60020000 );
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PROVIDE ( TIMERG1 = 0x60020000 );
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PROVIDE ( SYSTIMER = 0x60023000 );
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PROVIDE ( SYSTIMER = 0x60023000 );
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PROVIDE ( GPSPI2 = 0x60024000 );
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PROVIDE ( GPSPI2 = 0x60024000 );
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PROVIDE ( GPSPI3 = 0x60025000 );
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PROVIDE ( SYSCON = 0x60026000 );
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PROVIDE ( SYSCON = 0x60026000 );
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PROVIDE ( TWAI = 0x6002B000 );
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PROVIDE ( TWAI = 0x6002B000 );
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PROVIDE ( GPSPI4 = 0x60037000 );
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PROVIDE ( APB_SARADC = 0x60040000 );
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PROVIDE ( APB_SARADC = 0x60040000 );
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PROVIDE ( USB_SERIAL_JTAG = 0x60043000 );
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PROVIDE ( USB_SERIAL_JTAG = 0x60043000 );
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PROVIDE ( GDMA = 0x6003F000 );
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PROVIDE ( GDMA = 0x6003F000 );
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@ -90,6 +90,7 @@
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#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
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#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
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#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
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//Convenient way to replace the register ops when ulp riscv projects
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//Convenient way to replace the register ops when ulp riscv projects
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@ -1,25 +1,16 @@
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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/*
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//
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* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
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// Licensed under the Apache License, Version 2.0 (the "License");
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*
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// you may not use this file except in compliance with the License.
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* SPDX-License-Identifier: Apache-2.0
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// You may obtain a copy of the License at
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*/
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SPI_MEM_REG_H_
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#ifndef _SOC_SPI_MEM_REG_H_
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#define _SOC_SPI_MEM_REG_H_
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#define _SOC_SPI_MEM_REG_H_
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#include "soc.h"
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#ifdef __cplusplus
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#ifdef __cplusplus
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extern "C" {
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extern "C" {
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#endif
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#endif
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#include "soc.h"
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
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#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000)
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#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000)
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/* SPI_MEM_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */
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/* SPI_MEM_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */
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@ -1,25 +1,16 @@
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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/*
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//
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* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
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// Licensed under the Apache License, Version 2.0 (the "License");
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*
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// you may not use this file except in compliance with the License.
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* SPDX-License-Identifier: Apache-2.0
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// You may obtain a copy of the License at
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*/
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SPI_REG_H_
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#ifndef _SOC_SPI_REG_H_
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#define _SOC_SPI_REG_H_
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#define _SOC_SPI_REG_H_
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#include "soc.h"
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#ifdef __cplusplus
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#ifdef __cplusplus
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extern "C" {
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extern "C" {
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#endif
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#endif
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#include "soc.h"
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#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 )))
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#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000)
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#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000)
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/* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */
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/* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */
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@ -119,6 +119,7 @@
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#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
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#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
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#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
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//Convenient way to replace the register ops when ulp riscv projects
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//Convenient way to replace the register ops when ulp riscv projects
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@ -37,7 +37,6 @@ PROVIDE ( SYSCON = 0x60026000 );
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PROVIDE ( I2C1 = 0x60027000 );
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PROVIDE ( I2C1 = 0x60027000 );
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PROVIDE ( SDMMC = 0x60028000 );
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PROVIDE ( SDMMC = 0x60028000 );
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PROVIDE ( TWAI = 0x6002B000 );
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PROVIDE ( TWAI = 0x6002B000 );
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PROVIDE ( GPSPI4 = 0x60037000 );
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PROVIDE ( GDMA = 0x6003F000 );
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PROVIDE ( GDMA = 0x6003F000 );
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PROVIDE ( UART2 = 0x6002E000 );
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PROVIDE ( UART2 = 0x6002E000 );
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PROVIDE ( DMA = 0x6003F000 );
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PROVIDE ( DMA = 0x6003F000 );
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