rmt: update soc data with regtool for esp32s3

components/hal/esp32s3/include/hal/rmt_ll.h

@@ -1,4 +1,4 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -13,11 +13,9 @@
 // limitations under the License.
 #pragma once
 
-#include <stdint.h>
 #include <stddef.h>
 #include <stdbool.h>
 #include "soc/rmt_struct.h"
-#include "soc/soc_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -51,7 +49,7 @@ static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev)
 
 static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable)
 {
-    dev->sys_conf.fifo_mask = enable;
+    dev->sys_conf.apb_fifo_mask = enable;
 }
 
 static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b)
@@ -87,132 +85,132 @@ static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t ch
 
 static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
 {
-    dev->tx_conf[channel].mem_rd_rst = 1;
-    dev->tx_conf[channel].mem_rd_rst = 0;
-    dev->tx_conf[channel].mem_rst = 1;
-    dev->tx_conf[channel].mem_rst = 0;
+    dev->chnconf0[channel].mem_rd_rst_n = 1;
+    dev->chnconf0[channel].mem_rd_rst_n = 0;
+    dev->chnconf0[channel].apb_mem_rst_n = 1;
+    dev->chnconf0[channel].apb_mem_rst_n = 0;
 }
 
 static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
 {
-    dev->rx_conf[channel].conf1.mem_wr_rst = 1;
-    dev->rx_conf[channel].conf1.mem_wr_rst = 0;
-    dev->rx_conf[channel].conf1.mem_rst = 1;
-    dev->rx_conf[channel].conf1.mem_rst = 0;
+    dev->chmconf[channel].conf1.mem_wr_rst_m = 1;
+    dev->chmconf[channel].conf1.mem_wr_rst_m = 0;
+    dev->chmconf[channel].conf1.apb_mem_rst_m = 1;
+    dev->chmconf[channel].conf1.apb_mem_rst_m = 0;
 }
 
 static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)
 {
-    dev->tx_conf[channel].conf_update = 1;
-    dev->tx_conf[channel].tx_start = 1;
+    dev->chnconf0[channel].conf_update_n = 1;
+    dev->chnconf0[channel].tx_start_n = 1;
 }
 
 static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel)
 {
-    dev->tx_conf[channel].tx_stop = 1;
-    dev->tx_conf[channel].conf_update = 1;
+    dev->chnconf0[channel].tx_stop_n = 1;
+    dev->chnconf0[channel].conf_update_n = 1;
 }
 
 static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->rx_conf[channel].conf1.rx_en = enable;
-    dev->rx_conf[channel].conf1.conf_update = 1;
+    dev->chmconf[channel].conf1.rx_en_m = enable;
+    dev->chmconf[channel].conf1.conf_update_m = 1;
 }
 
 static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
 {
-    dev->tx_conf[channel].mem_size = block_num;
+    dev->chnconf0[channel].mem_size_n = block_num;
 }
 
 static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
 {
-    dev->rx_conf[channel].conf0.mem_size = block_num;
+    dev->chmconf[channel].conf0.mem_size_m = block_num;
 }
 
 static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->tx_conf[channel].mem_size;
+    return dev->chnconf0[channel].mem_size_n;
 }
 
 static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->rx_conf[channel].conf0.mem_size;
+    return dev->chmconf[channel].conf0.mem_size_m;
 }
 
 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->tx_conf[channel].div_cnt = div;
+    dev->chnconf0[channel].div_cnt_n = div;
 }
 
 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->rx_conf[channel].conf0.div_cnt = div;
+    dev->chmconf[channel].conf0.div_cnt_m = div;
 }
 
 static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->tx_conf[channel].div_cnt;
+    return dev->chnconf0[channel].div_cnt_n;
 }
 
 static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->rx_conf[channel].conf0.div_cnt;
+    return dev->chmconf[channel].conf0.div_cnt_m;
 }
 
 static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->tx_conf[channel].mem_tx_wrap_en = enable;
+    dev->chnconf0[channel].mem_tx_wrap_en_n = enable;
 }
 
 static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->rx_conf[channel].conf0.idle_thres = thres;
+    dev->chmconf[channel].conf0.idle_thres_m = thres;
 }
 
 static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->rx_conf[channel].conf0.idle_thres;
+    return dev->chmconf[channel].conf0.idle_thres_m;
 }
 
 static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
 {
-    dev->rx_conf[channel].conf1.mem_owner = owner;
+    dev->chmconf[channel].conf1.mem_owner_m = owner;
 }
 
 static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->rx_conf[channel].conf1.mem_owner;
+    return dev->chmconf[channel].conf1.mem_owner_m;
 }
 
 static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->tx_conf[channel].tx_conti_mode = enable;
+    dev->chnconf0[channel].tx_conti_mode_n = enable;
 }
 
 static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->tx_conf[channel].tx_conti_mode;
+    return dev->chnconf0[channel].tx_conti_mode_n;
 }
 
 static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count)
 {
-    dev->tx_lim[channel].tx_loop_num = count;
+    dev->chn_tx_lim[channel].tx_loop_num_chn = count;
 }
 
 static inline void rmt_ll_tx_reset_loop(rmt_dev_t *dev, uint32_t channel)
 {
-    dev->tx_lim[channel].loop_count_reset = 1;
-    dev->tx_lim[channel].loop_count_reset = 0;
+    dev->chn_tx_lim[channel].loop_count_reset_chn = 1;
+    dev->chn_tx_lim[channel].loop_count_reset_chn = 0;
 }
 
 static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->tx_lim[channel].tx_loop_cnt_en = enable;
+    dev->chn_tx_lim[channel].tx_loop_cnt_en_chn = enable;
 }
 
 static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable)
 {
-    dev->tx_sim.en = enable;
+    dev->tx_sim.tx_sim_en = enable;
 }
 
 static inline void rmt_ll_tx_add_to_sync_group(rmt_dev_t *dev, uint32_t channel)
@@ -227,57 +225,57 @@ static inline void rmt_ll_tx_remove_from_sync_group(rmt_dev_t *dev, uint32_t cha
 
 static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->rx_conf[channel].conf1.rx_filter_en = enable;
+    dev->chmconf[channel].conf1.rx_filter_en_m = enable;
 }
 
 static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->rx_conf[channel].conf1.rx_filter_thres = thres;
+    dev->chmconf[channel].conf1.rx_filter_thres_m = thres;
 }
 
 static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->tx_conf[channel].idle_out_en = enable;
+    dev->chnconf0[channel].idle_out_en_n = enable;
 }
 
 static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->tx_conf[channel].idle_out_en;
+    return dev->chnconf0[channel].idle_out_en_n;
 }
 
 static inline void rmt_ll_tx_set_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
 {
-    dev->tx_conf[channel].idle_out_lv = level;
+    dev->chnconf0[channel].idle_out_lv_n = level;
 }
 
 static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->tx_conf[channel].idle_out_lv;
+    return dev->chnconf0[channel].idle_out_lv_n;
 }
 
 static inline uint32_t rmt_ll_rx_get_channel_status(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->rx_status[channel].val;
+    return dev->chmstatus[channel].val;
 }
 
 static inline uint32_t rmt_ll_tx_get_channel_status(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->tx_status[channel].val;
+    return dev->chnstatus[channel].val;
 }
 
 static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
 {
-    dev->tx_lim[channel].limit = limit;
+    dev->chn_tx_lim[channel].tx_lim_chn = limit;
 }
 
 static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
 {
-    dev->rx_lim[channel].rx_lim = limit;
+    dev->chm_rx_lim[channel].chm_rx_lim_reg = limit;
 }
 
 static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->rx_lim[channel].rx_lim;
+    return dev->chm_rx_lim[channel].chm_rx_lim_reg;
 }
 
 static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable)
@@ -426,57 +424,57 @@ static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
 {
     // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register)
     // We take care of the "read-modify-write" procedure by ourselves.
-    typeof(dev->tx_carrier[0]) reg;
-    reg.high = high_ticks;
-    reg.low = low_ticks;
-    dev->tx_carrier[channel].val = reg.val;
+    rmt_chncarrier_duty_reg_t reg;
+    reg.carrier_high_chn = high_ticks;
+    reg.carrier_low_chn = low_ticks;
+    dev->chncarrier_duty[channel].val = reg.val;
 }
 
 static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
 {
-    typeof(dev->rx_carrier[0]) reg;
-    reg.high_thres = high_ticks;
-    reg.low_thres = low_ticks;
-    dev->rx_carrier[channel].val = reg.val;
+    rmt_chm_rx_carrier_rm_reg_t reg;
+    reg.carrier_high_thres_chm = high_ticks;
+    reg.carrier_low_thres_chm = low_ticks;
+    dev->chm_rx_carrier_rm[channel].val = reg.val;
 }
 
 static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks )
 {
-    *high_ticks = dev->tx_carrier[channel].high;
-    *low_ticks = dev->tx_carrier[channel].low;
+    *high_ticks = dev->chncarrier_duty[channel].carrier_high_chn;
+    *low_ticks = dev->chncarrier_duty[channel].carrier_low_chn;
 }
 
 static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->rx_carrier[channel].high_thres;
-    *low_ticks = dev->rx_carrier[channel].low_thres;
+    *high_ticks = dev->chm_rx_carrier_rm[channel].carrier_high_thres_chm;
+    *low_ticks = dev->chm_rx_carrier_rm[channel].carrier_low_thres_chm;
 }
 
 static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->tx_conf[channel].carrier_en = enable;
+    dev->chnconf0[channel].carrier_en_n = enable;
 }
 
 static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->rx_conf[channel].conf0.carrier_en = enable;
+    dev->chmconf[channel].conf0.carrier_en_m = enable;
 }
 
 static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
 {
-    dev->tx_conf[channel].carrier_out_lv = level;
+    dev->chnconf0[channel].carrier_out_lv_n = level;
 }
 
 static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
 {
-    dev->rx_conf[channel].conf0.carrier_out_lv = level;
+    dev->chmconf[channel].conf0.carrier_out_lv_m = level;
 }
 
 // set true, enable carrier in all RMT state (idle, reading, sending)
 // set false, enable carrier only in sending state (i.e. there're effective data in RAM to be sent)
 static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->tx_conf[channel].carrier_eff_en = !enable;
+    dev->chnconf0[channel].carrier_eff_en_n = !enable;
 }
 
 //Writes items to the specified TX channel memory with the given offset and length.
@@ -492,7 +490,7 @@ static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const v
 
 static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->rx_conf[channel].conf1.mem_rx_wrap_en = enable;
+    dev->chmconf[channel].conf1.mem_rx_wrap_en_m = enable;
 }
 
 #ifdef __cplusplus