From 402ccacc1011b58ffef8288c3d9521b8e140daa4 Mon Sep 17 00:00:00 2001 From: Armando Date: Fri, 22 Jan 2021 20:23:54 +0800 Subject: [PATCH] system: update edma reset in system_api_esp32c3/s3.c --- components/esp32c3/system_api_esp32c3.c | 6 +----- components/esp32s3/system_api_esp32s3.c | 5 ++++- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/components/esp32c3/system_api_esp32c3.c b/components/esp32c3/system_api_esp32c3.c index e054f72240..703a68e5b0 100644 --- a/components/esp32c3/system_api_esp32c3.c +++ b/components/esp32c3/system_api_esp32c3.c @@ -100,16 +100,12 @@ void IRAM_ATTR esp_restart_noos(void) // Reset timer/spi/uart SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, - SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SPI3_DMA_RST | SYSTEM_SPI2_DMA_RST); + SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST); REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - // Reset dma SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - // Set CPU back to XTAL source, no PLL, same as hard reset #if !CONFIG_IDF_ENV_FPGA rtc_clk_cpu_freq_set_xtal(); diff --git a/components/esp32s3/system_api_esp32s3.c b/components/esp32s3/system_api_esp32s3.c index a562f37dfe..924da6fd2b 100644 --- a/components/esp32s3/system_api_esp32s3.c +++ b/components/esp32s3/system_api_esp32s3.c @@ -98,13 +98,16 @@ void IRAM_ATTR esp_restart_noos(void) // Reset timer/spi/uart SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, - SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SPI3_DMA_RST | SYSTEM_SPI2_DMA_RST); + SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST); REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); // Reset dma SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); + SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + // Set CPU back to XTAL source, no PLL, same as hard reset #if !CONFIG_IDF_ENV_FPGA rtc_clk_cpu_freq_set_xtal();