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feat(all): Use PRIx macro in all logs

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This commit is contained in:
Konstantin Kondrashov 2024-03-07 17:43:45 +02:00
parent 08d1460f15
commit 3f89072af1
57 changed files with 194 additions and 194 deletions
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6
components/app_trace/app_trace.c
View File

@ -196,7 +196,7 @@ esp_err_t esp_apptrace_read(esp_apptrace_dest_t dest, void *buf, uint32_t *size,
*size = 0;
uint8_t *ptr = ch->hw->get_down_buffer(ch->hw_data, &act_sz, &tmo);
if (ptr && act_sz > 0) {
ESP_APPTRACE_LOGD("Read %d bytes from host", act_sz);
ESP_APPTRACE_LOGD("Read %" PRIu32 " bytes from host", act_sz);
memcpy(buf, ptr, act_sz);
res = ch->hw->put_down_buffer(ch->hw_data, ptr, &tmo);
*size = act_sz;
@ -329,7 +329,7 @@ int esp_apptrace_vprintf_to(esp_apptrace_dest_t dest, uint32_t user_tmo, const c
}
esp_apptrace_tmo_init(&tmo, user_tmo);
ESP_APPTRACE_LOGD("fmt %x", fmt);
ESP_APPTRACE_LOGD("fmt %p", fmt);
while ((p = (uint8_t *)strchr((char *)p, '%')) && nargs < ESP_APPTRACE_MAX_VPRINTF_ARGS) {
p++;
if (*p != '%' && *p != 0) {
@ -355,7 +355,7 @@ int esp_apptrace_vprintf_to(esp_apptrace_dest_t dest, uint32_t user_tmo, const c
uint32_t arg = va_arg(ap, uint32_t);
*(uint32_t *)pout = arg;
pout += sizeof(uint32_t);
ESP_APPTRACE_LOGD("arg %x", arg);
ESP_APPTRACE_LOGD("arg %" PRIx32, arg);
}
int ret = ch->hw->put_up_buffer(ch->hw_data, p, &tmo);

26
components/app_trace/app_trace_membufs_proto.c
View File

@ -100,7 +100,7 @@ static esp_err_t esp_apptrace_membufs_swap(esp_apptrace_membufs_proto_data_t *pr
if (proto->hw->host_data_pending() && hdr->block_sz > 0) {
// TODO: add support for multiple blocks from host, currently there is no need for that
uint8_t *p = proto->blocks[new_block_num].start + proto->blocks[new_block_num].sz;
ESP_APPTRACE_LOGD("Recvd %d bytes from host (@ 0x%x) [%x %x %x %x %x %x %x %x .. %x %x %x %x %x %x %x %x]",
ESP_APPTRACE_LOGD("Recvd %" PRIu16 " bytes from host (@ %p) [%x %x %x %x %x %x %x %x .. %x %x %x %x %x %x %x %x]",
hdr->block_sz, proto->blocks[new_block_num].start,
*(proto->blocks[new_block_num].start+0), *(proto->blocks[new_block_num].start+1),
*(proto->blocks[new_block_num].start+2), *(proto->blocks[new_block_num].start+3),
@ -109,7 +109,7 @@ static esp_err_t esp_apptrace_membufs_swap(esp_apptrace_membufs_proto_data_t *pr
*(p-8), *(p-7), *(p-6), *(p-5), *(p-4), *(p-3), *(p-2), *(p-1));
uint32_t sz = esp_apptrace_membufs_down_buffer_write_nolock(proto, (uint8_t *)(hdr+1), hdr->block_sz);
if (sz != hdr->block_sz) {
ESP_APPTRACE_LOGE("Failed to write %d bytes to down buffer (%d %d)!", hdr->block_sz - sz, hdr->block_sz, sz);
ESP_APPTRACE_LOGE("Failed to write %" PRIu32 " bytes to down buffer (%" PRIu16 " %" PRIu32 ")!", hdr->block_sz - sz, hdr->block_sz, sz);
}
hdr->block_sz = 0;
}
@ -196,7 +196,7 @@ static uint32_t esp_apptrace_membufs_down_buffer_write_nolock(esp_apptrace_membu
uint32_t total_sz = 0;
while (total_sz < size) {
ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock WRS %d-%d-%d %d", proto->rb_down.wr, proto->rb_down.rd,
ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock WRS %" PRIu32 "-%" PRIu32 "-%" PRIu32 " %" PRIu32, proto->rb_down.wr, proto->rb_down.rd,
proto->rb_down.cur_size, size);
uint32_t wr_sz = esp_apptrace_rb_write_size_get(&proto->rb_down);
if (wr_sz == 0) {
@ -206,15 +206,15 @@ static uint32_t esp_apptrace_membufs_down_buffer_write_nolock(esp_apptrace_membu
if (wr_sz > size - total_sz) {
wr_sz = size - total_sz;
}
ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %d", wr_sz);
ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %" PRIu32, wr_sz);
uint8_t *ptr = esp_apptrace_rb_produce(&proto->rb_down, wr_sz);
if (!ptr) {
assert(false && "Failed to produce bytes to down buffer!");
}
ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %d to 0x%x from 0x%x", wr_sz, ptr, data + total_sz + wr_sz);
ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %" PRIu32 " to %p from %p", wr_sz, ptr, data + total_sz + wr_sz);
memcpy(ptr, data + total_sz, wr_sz);
total_sz += wr_sz;
ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %d/%d", wr_sz, total_sz);
ESP_APPTRACE_LOGD("esp_apptrace_trax_down_buffer_write_nolock wr %" PRIu32 "/%" PRIu32 "", wr_sz, total_sz);
}
return total_sz;
}
@ -278,7 +278,7 @@ uint8_t *esp_apptrace_membufs_up_buffer_get(esp_apptrace_membufs_proto_data_t *p
uint8_t *buf_ptr = NULL;
if (size > ESP_APPTRACE_USR_DATA_LEN_MAX(proto)) {
ESP_APPTRACE_LOGE("Too large user data size %d!", size);
ESP_APPTRACE_LOGE("Too large user data size %" PRIu32 "!", size);
return NULL;
}
@ -308,21 +308,21 @@ uint8_t *esp_apptrace_membufs_up_buffer_get(esp_apptrace_membufs_proto_data_t *p
#endif
if (ESP_APPTRACE_INBLOCK_MARKER(proto) + ESP_APPTRACE_USR_BLOCK_RAW_SZ(size) > ESP_APPTRACE_INBLOCK(proto)->sz) {
#if CONFIG_APPTRACE_PENDING_DATA_SIZE_MAX > 0
ESP_APPTRACE_LOGD("Block full. Get %d bytes from PEND buffer", size);
ESP_APPTRACE_LOGD("Block full. Get %" PRIu32 " bytes from PEND buffer", size);
buf_ptr = esp_apptrace_rb_produce(&proto->rb_pend, ESP_APPTRACE_USR_BLOCK_RAW_SZ(size));
#endif
if (buf_ptr == NULL) {
int pended_buf;
ESP_APPTRACE_LOGD(" full. Get %d bytes from pend buffer", size);
ESP_APPTRACE_LOGD(" full. Get %" PRIu32 " bytes from pend buffer", size);
buf_ptr = esp_apptrace_membufs_wait4buf(proto, ESP_APPTRACE_USR_BLOCK_RAW_SZ(size), tmo, &pended_buf);
if (buf_ptr && !pended_buf) {
ESP_APPTRACE_LOGD("Got %d bytes from block", size);
ESP_APPTRACE_LOGD("Got %" PRIu32 " bytes from block", size);
// update cur block marker
ESP_APPTRACE_INBLOCK_MARKER_UPD(proto, ESP_APPTRACE_USR_BLOCK_RAW_SZ(size));
}
}
} else {
ESP_APPTRACE_LOGD("Get %d bytes from buffer", size);
ESP_APPTRACE_LOGD("Get %" PRIu32 " bytes from buffer", size);
// fit to curr nlock
buf_ptr = ESP_APPTRACE_INBLOCK(proto)->start + ESP_APPTRACE_INBLOCK_MARKER(proto);
// update cur block marker
@ -352,12 +352,12 @@ esp_err_t esp_apptrace_membufs_flush_nolock(esp_apptrace_membufs_proto_data_t *p
int res = ESP_OK;
if (ESP_APPTRACE_INBLOCK_MARKER(proto) < min_sz) {
ESP_APPTRACE_LOGI("Ignore flush request for min %d bytes. Bytes in block: %d.", min_sz, ESP_APPTRACE_INBLOCK_MARKER(proto));
ESP_APPTRACE_LOGI("Ignore flush request for min %" PRIu32 " bytes. Bytes in block: %" PRIu32, min_sz, ESP_APPTRACE_INBLOCK_MARKER(proto));
return ESP_OK;
}
// switch block while size of data (including that in pending buffer) is more than min size
while (ESP_APPTRACE_INBLOCK_MARKER(proto) > min_sz) {
ESP_APPTRACE_LOGD("Try to flush %d bytes. Wait until block switch for %lld us", ESP_APPTRACE_INBLOCK_MARKER(proto), tmo->tmo);
ESP_APPTRACE_LOGD("Try to flush %" PRIu32 " bytes. Wait until block switch for %" PRIi64 " us", ESP_APPTRACE_INBLOCK_MARKER(proto), tmo->tmo);
res = esp_apptrace_membufs_swap_waitus(proto, tmo);
if (res != ESP_OK) {
if (tmo->tmo != ESP_APPTRACE_TMO_INFINITE)

2
components/app_trace/host_file_io.c
View File

@ -122,7 +122,7 @@ static esp_err_t esp_apptrace_file_rsp_recv(esp_apptrace_dest_t dest, uint8_t *b
ESP_EARLY_LOGE(TAG, "Failed to read (%d)!", ret);
return ret;
}
ESP_EARLY_LOGV(TAG, "%s read %d bytes", __FUNCTION__, rd_size);
ESP_EARLY_LOGV(TAG, "%s read %" PRIu32 " bytes", __FUNCTION__, rd_size);
tot_rd += rd_size;
}

4
components/app_trace/port/riscv/port.c
View File

@ -159,7 +159,7 @@ static esp_err_t esp_apptrace_riscv_init(esp_apptrace_riscv_data_t *hw_data)
ESP_APPTRACE_LOGI("Apptrace initialized on CPU%d. Tracing control block @ %p.", core_id, &s_tracing_ctrl[core_id]);
s_tracing_ctrl[core_id].mem_blocks = hw_data->membufs.blocks;
for (int i = 0; i < 2; i++) {
ESP_APPTRACE_LOGD("Mem buf[%d] %d bytes @ %p (%p/%p)", i,
ESP_APPTRACE_LOGD("Mem buf[%d] %" PRIu32 " bytes @ %p (%p/%p)", i,
s_tracing_ctrl[core_id].mem_blocks[i].sz, s_tracing_ctrl[core_id].mem_blocks[i].start,
&(s_tracing_ctrl[core_id].mem_blocks[i].start), &(s_tracing_ctrl[core_id].mem_blocks[i].sz));
}
@ -325,7 +325,7 @@ static esp_err_t esp_apptrace_riscv_buffer_swap_start(uint32_t curr_block_id)
uint32_t acked_block = ESP_APPTRACE_RISCV_BLOCK_ID_GET(ctrl_reg);
uint32_t host_to_read = ESP_APPTRACE_RISCV_BLOCK_LEN_GET(ctrl_reg);
if (host_to_read != 0 || acked_block != (curr_block_id & ESP_APPTRACE_RISCV_BLOCK_ID_MSK)) {
ESP_APPTRACE_LOGD("[%d]: Can not switch %x %d %x %x/%lx", esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
ESP_APPTRACE_LOGD("[%d]: Can not switch %" PRIx32 " %" PRIu32 " %" PRIx32 " %" PRIx32 "/%" PRIx32, esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
curr_block_id & ESP_APPTRACE_RISCV_BLOCK_ID_MSK, curr_block_id);
res = ESP_ERR_NO_MEM;
goto _on_err;

4
components/app_trace/port/xtensa/port.c
View File

@ -288,7 +288,7 @@ static inline void esp_apptrace_trax_select_memory_block(int block_num)
: TRACEMEM_CORE0_MUX_BLK_BITS(TRACEMEM_MUX_BLK1_NUM);
block_bits |= block_num ? TRACEMEM_CORE1_MUX_BLK_BITS(TRACEMEM_MUX_BLK0_NUM)
: TRACEMEM_CORE1_MUX_BLK_BITS(TRACEMEM_MUX_BLK1_NUM);
ESP_EARLY_LOGV(TAG, "Select block %d @ %p (bits 0x%x)", block_num, s_trax_blocks[block_num], block_bits);
ESP_EARLY_LOGV(TAG, "Select block %d @ %p (bits 0x%" PRIx32 ")", block_num, s_trax_blocks[block_num], block_bits);
DPORT_WRITE_PERI_REG(SENSITIVE_INTERNAL_SRAM_USAGE_2_REG, block_bits);
#endif
}
@ -498,7 +498,7 @@ static esp_err_t esp_apptrace_trax_buffer_swap_start(uint32_t curr_block_id)
uint32_t acked_block = ESP_APPTRACE_TRAX_BLOCK_ID_GET(ctrl_reg);
uint32_t host_to_read = ESP_APPTRACE_TRAX_BLOCK_LEN_GET(ctrl_reg);
if (host_to_read != 0 || acked_block != (curr_block_id & ESP_APPTRACE_TRAX_BLOCK_ID_MSK)) {
ESP_APPTRACE_LOGD("HC[%d]: Can not switch %x %d %x %x/%lx", esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
ESP_APPTRACE_LOGD("HC[%d]: Can not switch %" PRIx32 " %" PRIu32 " %" PRIx32 " %" PRIx32 "/%" PRIx32, esp_cpu_get_core_id(), ctrl_reg, host_to_read, acked_block,
curr_block_id & ESP_APPTRACE_TRAX_BLOCK_ID_MSK, curr_block_id);
res = ESP_ERR_NO_MEM;
goto _on_err;

44
components/app_trace/test_apps/main/test_trace.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -135,9 +135,9 @@ static bool esp_apptrace_test_timer_isr_crash(gptimer_handle_t timer, const gpti
memset(tim_arg->data.buf + 2 * sizeof(uint32_t), tim_arg->data.wr_cnt & tim_arg->data.mask, tim_arg->data.buf_sz - 2 * sizeof(uint32_t));
int res = ESP_APPTRACE_TEST_WRITE_FROM_ISR(tim_arg->data.buf, tim_arg->data.buf_sz);
if (res != ESP_OK) {
esp_rom_printf("tim-%x: Failed to write trace %d %x!\n", tim_arg->gptimer, res, tim_arg->data.wr_cnt & tim_arg->data.mask);
esp_rom_printf("tim-%p: Failed to write trace %d %" PRIx32 "!\n", tim_arg->gptimer, res, tim_arg->data.wr_cnt & tim_arg->data.mask);
} else {
esp_rom_printf("tim-%x: Written chunk%d %d bytes, %x\n",
esp_rom_printf("tim-%p: Written chunk%" PRIu32 " %" PRIu32 " bytes, %" PRIx32 "\n",
timer, tim_arg->data.wr_cnt, tim_arg->data.buf_sz, tim_arg->data.wr_cnt & tim_arg->data.mask);
tim_arg->data.wr_cnt++;
}
@ -153,7 +153,7 @@ static void esp_apptrace_dummy_task(void *p)
esp_apptrace_test_task_arg_t *arg = (esp_apptrace_test_task_arg_t *) p;
TickType_t tmo_ticks = arg->data.period / (1000 * portTICK_PERIOD_MS);
ESP_APPTRACE_TEST_LOGI("%x: run dummy task (period %u us, %u timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->timers_num);
ESP_APPTRACE_TEST_LOGI("%p: run dummy task (period %" PRIu32 " us, %" PRIu32 " timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->timers_num);
for (int i = 0; i < arg->timers_num; i++) {
gptimer_config_t timer_config = {
@ -163,7 +163,7 @@ static void esp_apptrace_dummy_task(void *p)
};
TEST_ESP_OK(gptimer_new_timer(&timer_config, &arg->timers[i].gptimer));
*(uint32_t *)arg->timers[i].data.buf = (uint32_t)arg->timers[i].gptimer | (1 << 31);
ESP_APPTRACE_TEST_LOGI("%x: start timer %x period %u us", xTaskGetCurrentTaskHandle(), arg->timers[i].gptimer, arg->timers[i].data.period);
ESP_APPTRACE_TEST_LOGI("%p: start timer %p period %" PRIu32 " us", xTaskGetCurrentTaskHandle(), arg->timers[i].gptimer, arg->timers[i].data.period);
gptimer_alarm_config_t alarm_config = {
.reload_count = 0,
.alarm_count = arg->timers[i].data.period,
@ -180,7 +180,7 @@ static void esp_apptrace_dummy_task(void *p)
int i = 0;
while (!arg->stop) {
ESP_APPTRACE_TEST_LOGD("%x: dummy task work %d.%d", xTaskGetCurrentTaskHandle(), esp_cpu_get_core_id(), i++);
ESP_APPTRACE_TEST_LOGD("%p: dummy task work %d.%d", xTaskGetCurrentTaskHandle(), esp_cpu_get_core_id(), i++);
if (tmo_ticks) {
vTaskDelay(tmo_ticks);
}
@ -202,7 +202,7 @@ static void esp_apptrace_test_task(void *p)
int res;
TickType_t tmo_ticks = arg->data.period / (1000 * portTICK_PERIOD_MS);
ESP_APPTRACE_TEST_LOGI("%x: run (period %u us, stamp mask %x, %u timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->data.mask, arg->timers_num);
ESP_APPTRACE_TEST_LOGI("%p: run (period %" PRIu32 " us, stamp mask %" PRIx8 ", %" PRIu32 " timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->data.mask, arg->timers_num);
for (int i = 0; i < arg->timers_num; i++) {
gptimer_config_t timer_config = {
@ -212,7 +212,7 @@ static void esp_apptrace_test_task(void *p)
};
TEST_ESP_OK(gptimer_new_timer(&timer_config, &arg->timers[i].gptimer));
*(uint32_t *)arg->timers[i].data.buf = ((uint32_t)arg->timers[i].gptimer) | (1 << 31) | (esp_cpu_get_core_id() ? 0x1 : 0);
ESP_APPTRACE_TEST_LOGI("%x: start timer %x period %u us", xTaskGetCurrentTaskHandle(), arg->timers[i].gptimer, arg->timers[i].data.period);
ESP_APPTRACE_TEST_LOGI("%p: start timer %p period %" PRIu32 " us", xTaskGetCurrentTaskHandle(), arg->timers[i].gptimer, arg->timers[i].data.period);
gptimer_alarm_config_t alarm_config = {
.reload_count = 0,
.alarm_count = arg->timers[i].data.period,
@ -242,14 +242,14 @@ static void esp_apptrace_test_task(void *p)
}
if (res) {
if (1) { //arg->data.wr_err++ < ESP_APPTRACE_TEST_PRN_WRERR_MAX) {
ESP_APPTRACE_TEST_LOGE("%x: Failed to write trace %d %x!", xTaskGetCurrentTaskHandle(), res, arg->data.wr_cnt & arg->data.mask);
ESP_APPTRACE_TEST_LOGE("%p: Failed to write trace %d %" PRIx32 "!", xTaskGetCurrentTaskHandle(), res, arg->data.wr_cnt & arg->data.mask);
if (arg->data.wr_err == ESP_APPTRACE_TEST_PRN_WRERR_MAX) {
ESP_APPTRACE_TEST_LOGE("\n");
}
}
} else {
if (0) {
ESP_APPTRACE_TEST_LOGD("%x:%x: Written chunk%d %d bytes, %x", xTaskGetCurrentTaskHandle(), *ts, arg->data.wr_cnt, arg->data.buf_sz, arg->data.wr_cnt & arg->data.mask);
ESP_APPTRACE_TEST_LOGD("%p:%" PRIx32 ": Written chunk%" PRIu32 " %" PRIu32 " bytes, %" PRIx32, xTaskGetCurrentTaskHandle(), *ts, arg->data.wr_cnt, arg->data.buf_sz, arg->data.wr_cnt & arg->data.mask);
}
arg->data.wr_err = 0;
}
@ -273,7 +273,7 @@ static void esp_apptrace_test_task_crash(void *p)
{
esp_apptrace_test_task_arg_t *arg = (esp_apptrace_test_task_arg_t *) p;
ESP_APPTRACE_TEST_LOGE("%x: run (period %u us, stamp mask %x, %u timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->data.mask, arg->timers_num);
ESP_APPTRACE_TEST_LOGE("%p: run (period %" PRIu32 " us, stamp mask %" PRIx8 ", %" PRIu32 " timers)", xTaskGetCurrentTaskHandle(), arg->data.period, arg->data.mask, arg->timers_num);
arg->data.wr_cnt = 0;
*(uint32_t *)arg->data.buf = (uint32_t)xTaskGetCurrentTaskHandle();
@ -283,9 +283,9 @@ static void esp_apptrace_test_task_crash(void *p)
memset(arg->data.buf + sizeof(uint32_t), arg->data.wr_cnt & arg->data.mask, arg->data.buf_sz - sizeof(uint32_t));
int res = ESP_APPTRACE_TEST_WRITE(arg->data.buf, arg->data.buf_sz);
if (res) {
ESP_APPTRACE_TEST_LOGE("%x: Failed to write trace %d %x!", xTaskGetCurrentTaskHandle(), res, arg->data.wr_cnt & arg->data.mask);
ESP_APPTRACE_TEST_LOGE("%p: Failed to write trace %d %" PRIx32 "!", xTaskGetCurrentTaskHandle(), res, arg->data.wr_cnt & arg->data.mask);
} else {
ESP_APPTRACE_TEST_LOGD("%x: Written chunk%d %d bytes, %x", xTaskGetCurrentTaskHandle(), arg->data.wr_cnt, arg->data.buf_sz, arg->data.wr_cnt & arg->data.mask);
ESP_APPTRACE_TEST_LOGD("%p: Written chunk%" PRIu32 " %" PRIu32 " bytes, %" PRIx32, xTaskGetCurrentTaskHandle(), arg->data.wr_cnt, arg->data.buf_sz, arg->data.wr_cnt & arg->data.mask);
}
arg->data.wr_cnt++;
}
@ -315,7 +315,7 @@ static void esp_apptrace_test_ts_init(void)
.resolution_hz = 10000000,
};
TEST_ESP_OK(gptimer_new_timer(&timer_config, &ts_gptimer));
ESP_APPTRACE_TEST_LOGI("Use timer %x for TS", ts_gptimer);
ESP_APPTRACE_TEST_LOGI("Use timer %p for TS", ts_gptimer);
TEST_ESP_OK(gptimer_enable(ts_gptimer));
TEST_ESP_OK(gptimer_start(ts_gptimer));
}
@ -368,7 +368,7 @@ static void esp_apptrace_test(esp_apptrace_test_cfg_t *test_cfg)
TaskHandle_t thnd;
sprintf(name, "apptrace_test%d", i);
xTaskCreatePinnedToCore(test_cfg->tasks[i].task_func, name, 2048, &test_cfg->tasks[i], test_cfg->tasks[i].prio, &thnd, test_cfg->tasks[i].core);
ESP_APPTRACE_TEST_LOGI("Created task %x", thnd);
ESP_APPTRACE_TEST_LOGI("Created task %p", thnd);
}
xTaskCreatePinnedToCore(esp_apptrace_dummy_task, "dummy0", 2048, &dummy_task_arg, dummy_task_arg.prio, NULL, 0);
#if CONFIG_FREERTOS_UNICORE == 0
@ -641,7 +641,7 @@ static void esp_logtrace_task(void *p)
{
esp_logtrace_task_t *arg = (esp_logtrace_task_t *) p;
ESP_APPTRACE_TEST_LOGI("%x: run log test task", xTaskGetCurrentTaskHandle());
ESP_APPTRACE_TEST_LOGI("%p: run log test task", xTaskGetCurrentTaskHandle());
int i = 0;
while (1) {
@ -662,7 +662,7 @@ static void esp_logtrace_task(void *p)
ESP_APPTRACE_TEST_LOGE("Failed to flush printf buf (%d)!", ret);
}
ESP_APPTRACE_TEST_LOGI("%x: finished", xTaskGetCurrentTaskHandle());
ESP_APPTRACE_TEST_LOGI("%p: finished", xTaskGetCurrentTaskHandle());
xSemaphoreGive(arg->done);
vTaskDelay(1);
@ -681,13 +681,13 @@ TEST_CASE("Log trace test (2 tasks)", "[trace][ignore]")
};
xTaskCreatePinnedToCore(esp_logtrace_task, "logtrace0", 2048, &arg1, 3, &thnd, 0);
ESP_APPTRACE_TEST_LOGI("Created task %x", thnd);
ESP_APPTRACE_TEST_LOGI("Created task %p", thnd);
#if CONFIG_FREERTOS_UNICORE == 0
xTaskCreatePinnedToCore(esp_logtrace_task, "logtrace1", 2048, &arg2, 3, &thnd, 1);
#else
xTaskCreatePinnedToCore(esp_logtrace_task, "logtrace1", 2048, &arg2, 3, &thnd, 0);
#endif
ESP_APPTRACE_TEST_LOGI("Created task %x", thnd);
ESP_APPTRACE_TEST_LOGI("Created task %p", thnd);
xSemaphoreTake(arg1.done, portMAX_DELAY);
vSemaphoreDelete(arg1.done);
@ -760,7 +760,7 @@ static void esp_sysviewtrace_test_task(void *p)
xSemaphoreGive(*arg->sync);
}
}
ESP_APPTRACE_TEST_LOGI("%x: finished", xTaskGetCurrentTaskHandle());
ESP_APPTRACE_TEST_LOGI("%p: finished", xTaskGetCurrentTaskHandle());
xSemaphoreGive(arg->done);
vTaskDelay(1);
@ -809,13 +809,13 @@ TEST_CASE("SysView trace test 1", "[trace][ignore]")
TEST_ESP_OK(gptimer_new_timer(&timer_config, &tim_arg2.gptimer));
xTaskCreatePinnedToCore(esp_sysviewtrace_test_task, "svtrace0", 2048, &arg1, 3, &thnd, 0);
ESP_APPTRACE_TEST_LOGI("Created task %x", thnd);
ESP_APPTRACE_TEST_LOGI("Created task %p", thnd);
#if CONFIG_FREERTOS_UNICORE == 0
xTaskCreatePinnedToCore(esp_sysviewtrace_test_task, "svtrace1", 2048, &arg2, 5, &thnd, 1);
#else
xTaskCreatePinnedToCore(esp_sysviewtrace_test_task, "svtrace1", 2048, &arg2, 5, &thnd, 0);
#endif
ESP_APPTRACE_TEST_LOGI("Created task %x", thnd);
ESP_APPTRACE_TEST_LOGI("Created task %p", thnd);
xSemaphoreTake(arg1.done, portMAX_DELAY);
vSemaphoreDelete(arg1.done);

14
components/bootloader_support/bootloader_flash/src/bootloader_flash.c
View File

@ -187,7 +187,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
return NULL; /* can't map twice */
}
if (size > MMAP_MMU_SIZE) {
ESP_EARLY_LOGE(TAG, "bootloader_mmap excess size %x", size);
ESP_EARLY_LOGE(TAG, "bootloader_mmap excess size %" PRIx32, size);
return NULL;
}
@ -214,13 +214,13 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
#endif
//---------------Do mapping------------------------
ESP_EARLY_LOGD(TAG, "rodata starts from paddr=0x%08x, size=0x%x, will be mapped to vaddr=0x%08x", src_paddr, size, MMU_BLOCK0_VADDR);
ESP_EARLY_LOGD(TAG, "rodata starts from paddr=0x%08" PRIx32 ", size=0x%" PRIx32 ", will be mapped to vaddr=0x%08" PRIx32, src_paddr, size, (uint32_t)MMU_BLOCK0_VADDR);
#if CONFIG_IDF_TARGET_ESP32
uint32_t count = GET_REQUIRED_MMU_PAGES(size, src_paddr);
int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_paddr_aligned, 64, count);
ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", src_paddr_aligned, MMU_BLOCK0_VADDR, count * SPI_FLASH_MMU_PAGE_SIZE);
ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", src_paddr_aligned, (uint32_t)MMU_BLOCK0_VADDR, count * SPI_FLASH_MMU_PAGE_SIZE);
if (e != 0) {
ESP_EARLY_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
ESP_EARLY_LOGE(TAG, "cache_flash_mmu_set failed: %d", e);
Cache_Read_Enable(0);
return NULL;
}
@ -231,7 +231,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
*/
uint32_t actual_mapped_len = 0;
mmu_hal_map_region(0, MMU_TARGET_FLASH0, MMU_BLOCK0_VADDR, src_paddr_aligned, size_after_paddr_aligned, &actual_mapped_len);
ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", src_paddr_aligned, MMU_BLOCK0_VADDR, actual_mapped_len);
ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", src_paddr_aligned, (uint32_t)MMU_BLOCK0_VADDR, actual_mapped_len);
#endif
/**
@ -326,7 +326,7 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
#endif
//---------------Do mapping------------------------
ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08" PRIx32 " (was 0x%08" PRIx32 ")", map_at, current_read_mapping);
#if CONFIG_IDF_TARGET_ESP32
//Should never fail if we only map a SPI_FLASH_MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
@ -735,7 +735,7 @@ esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
// If the RDID value is a valid XMC one, may skip the flow
const bool fast_check = true;
if (fast_check && is_xmc_chip_strict(g_rom_flashchip.device_id)) {
BOOTLOADER_FLASH_LOG(D, "XMC chip detected by RDID (%08X), skip.", g_rom_flashchip.device_id);
BOOTLOADER_FLASH_LOG(D, "XMC chip detected by RDID (%08" PRIX32 "), skip.", g_rom_flashchip.device_id);
return ESP_OK;
}

15
components/bootloader_support/src/bootloader_utility.c
View File

@ -416,8 +416,7 @@ static bool try_load_partition(const esp_partition_pos_t *partition, esp_image_m
}
#ifdef BOOTLOADER_BUILD
if (bootloader_load_image(partition, data) == ESP_OK) {
ESP_LOGI(TAG, "Loaded app from partition at offset 0x%x",
partition->offset);
ESP_LOGI(TAG, "Loaded app from partition at offset 0x%" PRIx32, partition->offset);
return true;
}
#endif
@ -811,7 +810,7 @@ static void set_cache_and_start_app(
//-----------------------MAP DROM--------------------------
uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK;
uint32_t drom_addr_aligned = drom_addr & MMU_FLASH_MASK;
ESP_EARLY_LOGV(TAG, "rodata starts from paddr=0x%08x, vaddr=0x%08x, size=0x%x", drom_addr, drom_load_addr, drom_size);
ESP_EARLY_LOGV(TAG, "rodata starts from paddr=0x%08" PRIx32 ", vaddr=0x%08" PRIx32 ", size=0x%" PRIx32, drom_addr, drom_load_addr, drom_size);
//The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
drom_size = (drom_load_addr - drom_load_addr_aligned) + drom_size;
#if CONFIG_IDF_TARGET_ESP32
@ -820,17 +819,17 @@ static void set_cache_and_start_app(
ESP_EARLY_LOGV(TAG, "rc=%d", rc);
rc = cache_flash_mmu_set(1, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
ESP_EARLY_LOGV(TAG, "rc=%d", rc);
ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, drom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, drom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
#else
uint32_t actual_mapped_len = 0;
mmu_hal_map_region(0, MMU_TARGET_FLASH0, drom_load_addr_aligned, drom_addr_aligned, drom_size, &actual_mapped_len);
ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, actual_mapped_len);
ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, actual_mapped_len);
#endif
//-----------------------MAP IROM--------------------------
uint32_t irom_load_addr_aligned = irom_load_addr & MMU_FLASH_MASK;
uint32_t irom_addr_aligned = irom_addr & MMU_FLASH_MASK;
ESP_EARLY_LOGV(TAG, "text starts from paddr=0x%08x, vaddr=0x%08x, size=0x%x", irom_addr, irom_load_addr, irom_size);
ESP_EARLY_LOGV(TAG, "text starts from paddr=0x%08" PRIx32 ", vaddr=0x%08" PRIx32 ", size=0x%" PRIx32, irom_addr, irom_load_addr, irom_size);
//The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
irom_size = (irom_load_addr - irom_load_addr_aligned) + irom_size;
#if CONFIG_IDF_TARGET_ESP32
@ -839,10 +838,10 @@ static void set_cache_and_start_app(
ESP_EARLY_LOGV(TAG, "rc=%d", rc);
rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
ESP_LOGV(TAG, "rc=%d", rc);
ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, irom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, irom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
#else
mmu_hal_map_region(0, MMU_TARGET_FLASH0, irom_load_addr_aligned, irom_addr_aligned, irom_size, &actual_mapped_len);
ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, actual_mapped_len);
ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, actual_mapped_len);
#endif
//----------------------Enable corresponding buses----------------

2
components/bootloader_support/src/esp32/flash_encryption_secure_features.c
View File

@ -35,7 +35,7 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
crypt_config = EFUSE_FLASH_CRYPT_CONFIG;
esp_efuse_write_field_blob(ESP_EFUSE_ENCRYPT_CONFIG, &crypt_config, 4);
} else if (crypt_config != EFUSE_FLASH_CRYPT_CONFIG) {
ESP_LOGE(TAG, "EFUSE_ENCRYPT_CONFIG should be set 0xF but it is 0x%x", crypt_config);
ESP_LOGE(TAG, "EFUSE_ENCRYPT_CONFIG should be set 0xF but it is 0x%" PRIx32, crypt_config);
}
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC

4
components/bootloader_support/src/flash_encryption/flash_encrypt.c
View File

@ -423,7 +423,7 @@ static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partit
return ESP_OK;
} else {
/* should_encrypt */
ESP_LOGI(TAG, "Encrypting partition %d at offset 0x%x (length 0x%x)...", index, partition->pos.offset, size);
ESP_LOGI(TAG, "Encrypting partition %d at offset 0x%" PRIx32 " (length 0x%" PRIx32 ")...", index, partition->pos.offset, size);
err = esp_flash_encrypt_region(partition->pos.offset, size);
ESP_LOGI(TAG, "Done encrypting");
@ -441,7 +441,7 @@ esp_err_t esp_flash_encrypt_region(uint32_t src_addr, size_t data_length)
uint32_t buf[FLASH_SECTOR_SIZE / sizeof(uint32_t)];
if (src_addr % FLASH_SECTOR_SIZE != 0) {
ESP_LOGE(TAG, "esp_flash_encrypt_region bad src_addr 0x%x", src_addr);
ESP_LOGE(TAG, "esp_flash_encrypt_region bad src_addr 0x%" PRIx32, src_addr);
return ESP_FAIL;
}

2
components/bootloader_support/src/secure_boot_v1/secure_boot.c
View File

@ -63,7 +63,7 @@ static bool secure_boot_generate(uint32_t image_len){
/* generate digest from image contents */
image = bootloader_mmap(ESP_BOOTLOADER_OFFSET, image_len);
if (!image) {
ESP_LOGE(TAG, "bootloader_mmap(0x1000, 0x%x) failed", image_len);
ESP_LOGE(TAG, "bootloader_mmap(0x1000, 0x%" PRIx32 ") failed", image_len);
return false;
}
for (size_t i = 0; i < image_len; i+= sizeof(digest.iv)) {

8
components/bootloader_support/src/secure_boot_v1/secure_boot_signatures_bootloader.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -33,7 +33,7 @@ esp_err_t esp_secure_boot_verify_signature(uint32_t src_addr, uint32_t length)
uint8_t verified_digest[ESP_SECURE_BOOT_DIGEST_LEN] = { 0 }; /* ignored in this function */
const esp_secure_boot_sig_block_t *sigblock;
ESP_LOGD(TAG, "verifying signature src_addr 0x%x length 0x%x", src_addr, length);
ESP_LOGD(TAG, "verifying signature src_addr 0x%" PRIx32 " length 0x%" PRIx32, src_addr, length);
esp_err_t err = bootloader_sha256_flash_contents(src_addr, length, digest);
if (err != ESP_OK) {
@ -43,7 +43,7 @@ esp_err_t esp_secure_boot_verify_signature(uint32_t src_addr, uint32_t length)
// Map the signature block
sigblock = (const esp_secure_boot_sig_block_t *) bootloader_mmap(src_addr + length, sizeof(esp_secure_boot_sig_block_t));
if(!sigblock) {
ESP_LOGE(TAG, "bootloader_mmap(0x%x, 0x%x) failed", src_addr + length, sizeof(esp_secure_boot_sig_block_t));
ESP_LOGE(TAG, "bootloader_mmap(0x%" PRIx32 ", 0x%x) failed", src_addr + length, sizeof(esp_secure_boot_sig_block_t));
return ESP_FAIL;
}
// Verify the signature
@ -71,7 +71,7 @@ esp_err_t esp_secure_boot_verify_ecdsa_signature_block(const esp_secure_boot_sig
}
if (sig_block->version != 0) {
ESP_LOGE(TAG, "image has invalid signature version field 0x%08x (image without a signature?)", sig_block->version);
ESP_LOGE(TAG, "image has invalid signature version field 0x%08" PRIx32 " (image without a signature?)", sig_block->version);
return ESP_FAIL;
}

4
components/bootloader_support/src/secure_boot_v2/secure_boot.c
View File

@ -70,7 +70,7 @@ static esp_err_t s_calculate_image_public_key_digests(uint32_t flash_offset, uin
uint8_t __attribute__((aligned(4))) key_digest[ESP_SECURE_BOOT_DIGEST_LEN] = {0};
size_t sig_block_addr = flash_offset + ALIGN_UP(flash_size, FLASH_SECTOR_SIZE);
ESP_LOGD(TAG, "calculating public key digests for sig blocks of image offset 0x%x (sig block offset 0x%x)", flash_offset, sig_block_addr);
ESP_LOGD(TAG, "calculating public key digests for sig blocks of image offset 0x%" PRIx32 " (sig block offset 0x%x)", flash_offset, sig_block_addr);
bzero(public_key_digests, sizeof(esp_image_sig_public_key_digests_t));
@ -130,7 +130,7 @@ static esp_err_t s_calculate_image_public_key_digests(uint32_t flash_offset, uin
}
if (ret == ESP_OK && public_key_digests->num_digests > 0) {
ESP_LOGI(TAG, "Digests successfully calculated, %d valid signatures (image offset 0x%x)",
ESP_LOGI(TAG, "Digests successfully calculated, %d valid signatures (image offset 0x%" PRIx32 ")",
public_key_digests->num_digests, flash_offset);
}

8
components/bootloader_support/src/secure_boot_v2/secure_boot_signatures_bootloader.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -31,18 +31,18 @@ esp_err_t esp_secure_boot_verify_signature(uint32_t src_addr, uint32_t length)
/* Rounding off length to the upper 4k boundary */
uint32_t padded_length = ALIGN_UP(length, FLASH_SECTOR_SIZE);
ESP_LOGD(TAG, "verifying signature src_addr 0x%x length 0x%x", src_addr, length);
ESP_LOGD(TAG, "verifying signature src_addr 0x%" PRIx32 " length 0x%" PRIx32, src_addr, length);
/* Calculate digest of main image */
esp_err_t err = bootloader_sha256_flash_contents(src_addr, padded_length, digest);
if (err != ESP_OK) {
ESP_LOGE(TAG, "Digest calculation failed 0x%x, 0x%x", src_addr, padded_length);
ESP_LOGE(TAG, "Digest calculation failed 0x%" PRIx32 ", 0x%" PRIx32, src_addr, padded_length);
return err;
}
const ets_secure_boot_signature_t *sig_block = bootloader_mmap(src_addr + padded_length, sizeof(ets_secure_boot_signature_t));
if (sig_block == NULL) {
ESP_LOGE(TAG, "Failed to mmap data at offset 0x%x", src_addr + padded_length);
ESP_LOGE(TAG, "Failed to mmap data at offset 0x%" PRIx32, src_addr + padded_length);
return ESP_FAIL;
}

2
components/driver/deprecated/i2s_legacy.c
View File

@ -272,7 +272,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
BaseType_t tmp = 0;
uint32_t finish_desc = 0;
if ((status & I2S_LL_EVENT_TX_DSCR_ERR) || (status & I2S_LL_EVENT_RX_DSCR_ERR)) {
ESP_EARLY_LOGE(TAG, "dma error, interrupt status: 0x%08x", status);
ESP_EARLY_LOGE(TAG, "dma error, interrupt status: 0x%08" PRIx32, status);
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_DMA_ERROR;
if (xQueueIsQueueFullFromISR(p_i2s->i2s_queue)) {

2
components/driver/test_apps/touch_sensor_v2/main/test_touch_v2.c
View File

@ -735,7 +735,7 @@ static esp_err_t test_touch_check_ch_intr_timeout(touch_pad_t pad_num)
touch_pad_timeout_resume();
break;
} else {
esp_rom_printf("-timeout %x T[%"PRIu32"] status %"PRIx32", evt_msk %x -\n",
esp_rom_printf("-timeout %" PRIx32 " T[%"PRIu32"] status %"PRIx32", evt_msk %x -\n",
s_touch_timeout_mask, evt.pad_num, evt.pad_status, evt.intr_mask);
touch_pad_timeout_resume();
}

8
components/driver/twai/twai.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -107,11 +107,11 @@ static void twai_alert_handler(twai_obj_t *p_twai_obj, uint32_t alert_code, int
#ifndef CONFIG_TWAI_ISR_IN_IRAM //Only log if ISR is not in IRAM
if (p_twai_obj->alerts_enabled & TWAI_ALERT_AND_LOG) {
if (alert_code >= ALERT_LOG_LEVEL_ERROR) {
ESP_EARLY_LOGE(TWAI_TAG, "Alert %d", alert_code);
ESP_EARLY_LOGE(TWAI_TAG, "Alert %" PRIu32, alert_code);
} else if (alert_code >= ALERT_LOG_LEVEL_WARNING) {
ESP_EARLY_LOGW(TWAI_TAG, "Alert %d", alert_code);
ESP_EARLY_LOGW(TWAI_TAG, "Alert %" PRIu32, alert_code);
} else {
ESP_EARLY_LOGI(TWAI_TAG, "Alert %d", alert_code);
ESP_EARLY_LOGI(TWAI_TAG, "Alert %" PRIu32, alert_code);
}
}
#endif //CONFIG_TWAI_ISR_IN_IRAM

2
components/efuse/esp32c3/esp_efuse_utility.c
View File

@ -78,7 +78,7 @@ esp_err_t esp_efuse_utility_check_errors(void)
if (error_reg & data_reg) {
// For 0001 situation (4x coding scheme):
// an error bit points that data bit is wrong in case the data bit equals 1. (need to reboot in this case).
ESP_EARLY_LOGE(TAG, "Error in EFUSE_RD_REPEAT_DATA%d_REG of BLOCK0 (error_reg=0x%08x, data_reg=0x%08x). Need to reboot", i, error_reg, data_reg);
ESP_EARLY_LOGE(TAG, "Error in EFUSE_RD_REPEAT_DATA%d_REG of BLOCK0 (error_reg=0x%08" PRIx32 ", data_reg=0x%08" PRIx32 "). Need to reboot", i, error_reg, data_reg);
efuse_hal_read();
return ESP_FAIL;
}

10
components/efuse/src/esp_efuse_utility.c
View File

@ -225,15 +225,15 @@ void esp_efuse_utility_debug_dump_single_block(int num_block, bool from_read)
if (from_read) {
for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, num_reg++) {
#ifdef CONFIG_EFUSE_VIRTUAL
esp_rom_printf("0x%08x ", virt_blocks[num_block][num_reg]);
esp_rom_printf("0x%08" PRIx32, virt_blocks[num_block][num_reg]);
#else
esp_rom_printf("0x%08x ", REG_READ(addr_rd_block));
esp_rom_printf("0x%08" PRIx32, REG_READ(addr_rd_block));
(void) num_reg;
#endif
}
} else {
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, num_reg++) {
esp_rom_printf("0x%08x ", REG_READ(addr_wr_block));
esp_rom_printf("0x%08" PRIx32, REG_READ(addr_wr_block));
}
}
esp_rom_printf("\n");
@ -261,7 +261,7 @@ esp_err_t esp_efuse_utility_write_reg(esp_efuse_block_t efuse_block, unsigned in
esp_err_t err = ESP_OK;
uint32_t reg = esp_efuse_utility_read_reg(efuse_block, num_reg);
if (reg & reg_to_write) {
ESP_EARLY_LOGE(TAG, "Repeated programming of programmed bits is strictly forbidden 0x%08x", reg & reg_to_write);
ESP_EARLY_LOGE(TAG, "Repeated programming of programmed bits is strictly forbidden 0x%08" PRIx32, reg & reg_to_write);
err = ESP_ERR_EFUSE_REPEATED_PROG;
} else {
write_reg(efuse_block, num_reg, reg_to_write);
@ -451,7 +451,7 @@ void esp_efuse_utility_erase_efuses_in_flash(void)
bool esp_efuse_utility_load_efuses_from_flash(void)
{
ESP_EARLY_LOGW(TAG, "[Virtual] try loading efuses from flash: 0x%x (offset)", esp_efuse_flash_offset);
ESP_EARLY_LOGW(TAG, "[Virtual] try loading efuses from flash: 0x%" PRIx32 " (offset)", esp_efuse_flash_offset);
if (esp_efuse_flash_offset == 0) {
ESP_EARLY_LOGE(TAG, "[Virtual] no efuse partition in partition_table? (Flash is not updated)");

4
components/esp_adc/test_apps/adc/main/test_adc_driver.c
View File

@ -196,13 +196,13 @@ TEST_CASE("ADC continuous big conv_frame_size test", "[adc_continuous]")
uint32_t cnt = 0;
ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
TEST_ESP_OK(adc_continuous_read(handle, result, ADC_FRAME_TEST_SIZE, &ret_num, ADC_MAX_DELAY));
esp_rom_printf("ret_num: %d\n", ret_num);
esp_rom_printf("ret_num: %" PRIu32 "\n", ret_num);
for (int i = 0; i < ret_num; i += SOC_ADC_DIGI_RESULT_BYTES) {
adc_digi_output_data_t *p = (adc_digi_output_data_t*)&result[i];
sum += ADC_DRIVER_TEST_GET_DATA(p);
cnt++;
}
esp_rom_printf("avg: %d\n", sum / cnt);
esp_rom_printf("avg: %" PRIu32 "\n", sum / cnt);
TEST_ASSERT_INT_WITHIN(ADC_TEST_LOW_THRESH, ADC_TEST_LOW_VAL, sum / cnt);
}

2
components/esp_app_format/esp_app_desc.c
View File

@ -115,7 +115,7 @@ ESP_SYSTEM_INIT_FN(init_show_app_info, CORE, BIT(0), 20)
ESP_EARLY_LOGI(TAG, "App version: %s", esp_app_desc.version);
#endif
#ifdef CONFIG_BOOTLOADER_APP_SECURE_VERSION
ESP_EARLY_LOGI(TAG, "Secure version: %d", esp_app_desc.secure_version);
ESP_EARLY_LOGI(TAG, "Secure version: %" PRIu32, esp_app_desc.secure_version);
#endif
#ifdef CONFIG_APP_COMPILE_TIME_DATE
ESP_EARLY_LOGI(TAG, "Compile time: %s %s", esp_app_desc.date, esp_app_desc.time);

2
components/esp_driver_ana_cmpr/ana_cmpr.c
View File

@ -226,7 +226,7 @@ esp_err_t ana_cmpr_set_internal_reference(ana_cmpr_handle_t cmpr, const ana_cmpr
analog_cmpr_ll_set_internal_ref_voltage(cmpr->dev, ref_cfg->ref_volt);
portEXIT_CRITICAL_SAFE(&s_spinlock);
ESP_EARLY_LOGD(TAG, "unit %d internal voltage level %"PRIu32, (int)cmpr->unit, ref_cfg->ref_volt);
ESP_EARLY_LOGD(TAG, "unit %d internal voltage level %" PRIu32, (int)cmpr->unit, (uint32_t)ref_cfg->ref_volt);
return ESP_OK;
}

6
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
View File

@ -105,7 +105,7 @@ TEST_CASE("GPIO_config_parameters_test", "[gpio]")
static void gpio_isr_edge_handler(void *arg)
{
uint32_t gpio_num = (uint32_t) arg;
esp_rom_printf("GPIO[%d] intr on core %d, val: %d\n", gpio_num, esp_cpu_get_core_id(), gpio_get_level(gpio_num));
esp_rom_printf("GPIO[%" PRIu32 "] intr on core %d, val: %d\n", gpio_num, esp_cpu_get_core_id(), gpio_get_level(gpio_num));
edge_intr_times++;
}
@ -114,7 +114,7 @@ static void gpio_isr_level_handler(void *arg)
{
uint32_t gpio_num = (uint32_t) arg;
disable_intr_times++;
esp_rom_printf("GPIO[%d] intr, val: %d, disable_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), disable_intr_times);
esp_rom_printf("GPIO[%" PRIu32 "] intr, val: %d, disable_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), disable_intr_times);
gpio_intr_disable(gpio_num);
}
@ -123,7 +123,7 @@ static void gpio_isr_level_handler2(void *arg)
{
uint32_t gpio_num = (uint32_t) arg;
level_intr_times++;
esp_rom_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), level_intr_times);
esp_rom_printf("GPIO[%" PRIu32 "] intr, val: %d, level_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), level_intr_times);
if (gpio_get_level(gpio_num)) {
gpio_set_level(gpio_num, 0);
} else {

2
components/esp_driver_gpio/test_apps/gpio_extensions/main/test_hysteresis.c
View File

@ -30,7 +30,7 @@
static void test_gpio_hysteresis_intr_handler(void *args)
{
esp_rom_printf("%d\n", ++ * ((uint32_t *)args));
esp_rom_printf("%" PRIu32 "\n", ++ * ((uint32_t *)args));
}
// This case is now tested only manually

2
components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cap.c
View File

@ -184,7 +184,7 @@ TEST_CASE("mcpwm_capture_software_catch", "[mcpwm]")
// check user data
TEST_ASSERT_EQUAL(2, test_callback_data.cap_data_index);
uint32_t delta = test_callback_data.cap_data[1] - test_callback_data.cap_data[0];
esp_rom_printf("duration=%u ticks\r\n", delta);
esp_rom_printf("duration=%" PRIu32 " ticks\r\n", delta);
uint32_t clk_src_res;
TEST_ESP_OK(mcpwm_capture_timer_get_resolution(cap_timer, &clk_src_res));
clk_src_res /= 1000; // convert to kHz

2
components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_timer.c
View File

@ -104,7 +104,7 @@ IRAM_ATTR static bool test_on_stop(mcpwm_timer_handle_t timer, const mcpwm_timer
{
test_mcpwm_timer_user_data_t *udata = (test_mcpwm_timer_user_data_t *)user_data;
BaseType_t high_task_wakeup = pdFALSE;
esp_rom_printf("timer stopped at %u\r\n", edata->count_value);
esp_rom_printf("timer stopped at %" PRIu32 "\r\n", edata->count_value);
TEST_ASSERT_EQUAL(0, edata->count_value);
xEventGroupSetBitsFromISR(udata->event_group, TEST_MCPWM_TIMER_EVENT_BIT_STOP, &high_task_wakeup);
return high_task_wakeup == pdTRUE;

2
components/esp_driver_sdio/src/sdio_slave.c
View File

@ -558,7 +558,7 @@ static void sdio_intr_send(void *arg)
}
assert(returned_cnt == 0);
ESP_EARLY_LOGV(TAG, "end: %x", finished_arg);
ESP_EARLY_LOGV(TAG, "end: %p", finished_arg);
ret = xQueueSendFromISR(context.ret_queue, &finished_arg, &yield);
assert(ret == pdTRUE);
}

4
components/esp_hw_support/adc_share_hw_ctrl.c
View File

@ -61,7 +61,7 @@ static uint32_t s_adc_cali_param[SOC_ADC_PERIPH_NUM][SOC_ADC_ATTEN_NUM] = {};
void adc_calc_hw_calibration_code(adc_unit_t adc_n, adc_atten_t atten)
{
if (s_adc_cali_param[adc_n][atten]) {
ESP_EARLY_LOGV(TAG, "Use calibrated val ADC%d atten=%d: %04X", adc_n + 1, atten, s_adc_cali_param[adc_n][atten]);
ESP_EARLY_LOGV(TAG, "Use calibrated val ADC%d atten=%d: %04" PRIX32, adc_n + 1, atten, s_adc_cali_param[adc_n][atten]);
return ;
}
@ -93,7 +93,7 @@ void adc_calc_hw_calibration_code(adc_unit_t adc_n, adc_atten_t atten)
#endif //SOC_ADC_SELF_HW_CALI_SUPPORTED
s_adc_cali_param[adc_n][atten] = init_code;
ESP_EARLY_LOGV(TAG, "Calib(V%d) ADC%d atten=%d: %04X", version, adc_n + 1, atten, init_code);
ESP_EARLY_LOGV(TAG, "Calib(V%d) ADC%d atten=%d: %04" PRIX32, version, adc_n + 1, atten, init_code);
}
void IRAM_ATTR adc_set_hw_calibration_code(adc_unit_t adc_n, adc_atten_t atten)

6
components/esp_hw_support/mspi_timing_by_mspi_delay.c
View File

@ -457,13 +457,13 @@ static uint32_t s_select_best_tuning_config_dtr(const mspi_timing_config_t *conf
max_freq = temp_max_freq;
best_point = current_point;
}
ESP_EARLY_LOGD(TAG, "sample point %"PRIu32", max pll is %"PRIu32" mhz, min pll is %"PRIu32"\n", current_point, temp_max_freq, temp_min_freq);
ESP_EARLY_LOGD(TAG, "sample point %" PRIu32 ", max pll is %" PRIu32 " mhz, min pll is %" PRIu32, current_point, temp_max_freq, temp_min_freq);
}
if (max_freq == 0) {
ESP_EARLY_LOGW(TAG, "freq scan tuning fail, best point is fallen back to index %"PRIu32"", end + 1 - consecutive_length);
ESP_EARLY_LOGW(TAG, "freq scan tuning fail, best point is fallen back to index %" PRIu32, end + 1 - consecutive_length);
best_point = end + 1 - consecutive_length;
} else {
ESP_EARLY_LOGD(TAG, "freq scan success, max pll is %"PRIu32"mhz, best point is index %"PRIu32"", max_freq, best_point);
ESP_EARLY_LOGD(TAG, "freq scan success, max pll is %" PRIu32 "mhz, best point is index %" PRIu32, max_freq, best_point);
}
return best_point;

4
components/esp_hw_support/mspi_timing_tuning.c
View File

@ -233,9 +233,9 @@ static void s_sweep_for_success_sample_points(uint8_t *reference_data, void *con
}
}
ESP_EARLY_LOGD(TAG, "test nums: %d, test result: [id][good/bad][good_times]:", s_tuning_cfg_drv.sweep_test_nums);
ESP_EARLY_LOGD(TAG, "test nums: %" PRIu32 ", test result: [id][good/bad][good_times]:", s_tuning_cfg_drv.sweep_test_nums);
for (config_idx = 0; config_idx < timing_config->available_config_num; config_idx++) {
ESP_EARLY_LOGD(TAG, "[%"PRIu32"][%s][%d] ", config_idx, out_array[config_idx] == s_tuning_cfg_drv.sweep_test_nums ? "good" : "bad", out_array[config_idx]);
ESP_EARLY_LOGD(TAG, "[%"PRIu32"][%s][%" PRIu32 "] ", config_idx, out_array[config_idx] == s_tuning_cfg_drv.sweep_test_nums ? "good" : "bad", out_array[config_idx]);
}
}

4
components/esp_hw_support/port/esp32c6/pmu_param.c
View File

@ -470,7 +470,7 @@ uint32_t get_act_hp_dbias(void)
}
} else {
hp_cali_dbias = HP_CALI_DBIAS_DEFAULT;
ESP_HW_LOGD(TAG, "hp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %d\n", blk_version);
ESP_HW_LOGD(TAG, "hp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %" PRIu32 "\n", blk_version);
}
}
@ -494,7 +494,7 @@ uint32_t get_act_lp_dbias(void)
}
} else {
lp_cali_dbias = LP_CALI_DBIAS_DEFAULT;
ESP_HW_LOGD(TAG, "lp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %d\n", blk_version);
ESP_HW_LOGD(TAG, "lp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %" PRIu32 "\n", blk_version);
}
} else {
ESP_HW_LOGD(TAG, "blk_version is less than 3, act dbias not burnt in efuse\n");

2
components/esp_hw_support/port/esp32p4/mspi_timing_config.c
View File

@ -23,7 +23,7 @@ void mspi_timing_config_set_psram_clock(uint32_t psram_freq_mhz, mspi_timing_spe
{
uint32_t freqdiv = MSPI_TIMING_MPLL_FREQ_MHZ / MSPI_TIMING_CORE_CLOCK_DIV / psram_freq_mhz;
assert(freqdiv > 0);
ESP_EARLY_LOGD(TAG, "psram_freq_mhz: %d mhz, bus clock div: %d", psram_freq_mhz, freqdiv);
ESP_EARLY_LOGD(TAG, "psram_freq_mhz: %" PRIu32 " mhz, bus clock div: %" PRIu32, psram_freq_mhz, freqdiv);
PERIPH_RCC_ATOMIC() {
//MSPI2 and MSPI3 share the register for core clock. So we only set MSPI2 here.
psram_ctrlr_ll_set_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, MSPI_TIMING_CORE_CLOCK_DIV);

44
components/esp_hw_support/port/esp32s3/esp_memprot.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -1053,19 +1053,19 @@ esp_err_t esp_mprot_set_prot(const esp_memp_config_t *memp_config)
if (memprot_ll_get_iram0_split_line_main_I_D_regval() != check_val) {
esp_rom_printf(
"Fatal error: Main I/D split line configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
"Fatal error: Main I/D split line configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
check_val, memprot_ll_get_iram0_split_line_main_I_D_regval());
abort();
}
if (memprot_ll_get_iram0_split_line_main_I_0_regval() != check_val) {
esp_rom_printf(
"Fatal error: IRAM0 I_0 split line configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
"Fatal error: IRAM0 I_0 split line configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
check_val, memprot_ll_get_iram0_split_line_main_I_0_regval());
abort();
}
if (memprot_ll_get_iram0_split_line_main_I_1_regval() != check_val) {
esp_rom_printf(
"Fatal error: IRAM0 I_1 split line configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
"Fatal error: IRAM0 I_1 split line configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
check_val, memprot_ll_get_iram0_split_line_main_I_1_regval());
abort();
}
@ -1075,13 +1075,13 @@ esp_err_t esp_mprot_set_prot(const esp_memp_config_t *memp_config)
if (memprot_ll_get_dram0_split_line_main_D_0_regval() != check_val) {
esp_rom_printf(
"Fatal error: DRAM0 D_0 split line configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
"Fatal error: DRAM0 D_0 split line configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
check_val, memprot_ll_get_dram0_split_line_main_D_0_regval());
abort();
}
if (memprot_ll_get_dram0_split_line_main_D_1_regval() != check_val) {
esp_rom_printf(
"Fatal error: DRAM0 D_1 split line configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
"Fatal error: DRAM0 D_1 split line configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
check_val, memprot_ll_get_dram0_split_line_main_D_1_regval());
abort();
}
@ -1089,58 +1089,58 @@ esp_err_t esp_mprot_set_prot(const esp_memp_config_t *memp_config)
//IRAM0 perms
ESP_MEMPROT_ERR_CHECK(ret, esp_mprot_get_pms_area(MEMPROT_PMS_AREA_IRAM0_0, &check_val, DEFAULT_CPU_NUM))
if (check_val != (MEMPROT_OP_READ | MEMPROT_OP_EXEC)) {
esp_rom_printf("Fatal error: IRAM0 PMS AREA_0 configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
MEMPROT_OP_READ | MEMPROT_OP_EXEC, check_val);
esp_rom_printf("Fatal error: IRAM0 PMS AREA_0 configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
(uint32_t)MEMPROT_OP_READ | MEMPROT_OP_EXEC, check_val);
abort();
}
ESP_MEMPROT_ERR_CHECK(ret, esp_mprot_get_pms_area(MEMPROT_PMS_AREA_IRAM0_1, &check_val, DEFAULT_CPU_NUM))
if (check_val != (MEMPROT_OP_READ | MEMPROT_OP_EXEC)) {
esp_rom_printf("Fatal error: IRAM0 PMS AREA_1 configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
MEMPROT_OP_READ | MEMPROT_OP_EXEC, check_val);
esp_rom_printf("Fatal error: IRAM0 PMS AREA_1 configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
(uint32_t)MEMPROT_OP_READ | MEMPROT_OP_EXEC, check_val);
abort();
}
ESP_MEMPROT_ERR_CHECK(ret, esp_mprot_get_pms_area(MEMPROT_PMS_AREA_IRAM0_2, &check_val, DEFAULT_CPU_NUM))
if (check_val != (MEMPROT_OP_READ | MEMPROT_OP_EXEC)) {
esp_rom_printf("Fatal error: IRAM0 PMS AREA_2 configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
MEMPROT_OP_READ | MEMPROT_OP_EXEC, check_val);
esp_rom_printf("Fatal error: IRAM0 PMS AREA_2 configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
(uint32_t)MEMPROT_OP_READ | MEMPROT_OP_EXEC, check_val);
abort();
}
ESP_MEMPROT_ERR_CHECK(ret, esp_mprot_get_pms_area(MEMPROT_PMS_AREA_IRAM0_3, &check_val, DEFAULT_CPU_NUM))
if (check_val != MEMPROT_OP_NONE) {
esp_rom_printf("Fatal error: IRAM0 PMS AREA_3 configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
MEMPROT_OP_NONE, check_val);
esp_rom_printf("Fatal error: IRAM0 PMS AREA_3 configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
(uint32_t) MEMPROT_OP_NONE, check_val);
abort();
}
//DRAM0 perms
ESP_MEMPROT_ERR_CHECK(ret, esp_mprot_get_pms_area(MEMPROT_PMS_AREA_DRAM0_0, &check_val, DEFAULT_CPU_NUM))
if (check_val != MEMPROT_OP_READ) {
esp_rom_printf("Fatal error: DRAM0 PMS AREA_0 configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
MEMPROT_OP_READ, check_val);
esp_rom_printf("Fatal error: DRAM0 PMS AREA_0 configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
(uint32_t)MEMPROT_OP_READ, check_val);
abort();
}
ESP_MEMPROT_ERR_CHECK(ret, esp_mprot_get_pms_area(MEMPROT_PMS_AREA_DRAM0_1, &check_val, DEFAULT_CPU_NUM))
if (check_val != (MEMPROT_OP_READ | MEMPROT_OP_WRITE)) {
esp_rom_printf("Fatal error: DRAM0 PMS AREA_1 configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
MEMPROT_OP_READ | MEMPROT_OP_WRITE, check_val);
esp_rom_printf("Fatal error: DRAM0 PMS AREA_1 configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
(uint32_t)MEMPROT_OP_READ | MEMPROT_OP_WRITE, check_val);
abort();
}
ESP_MEMPROT_ERR_CHECK(ret, esp_mprot_get_pms_area(MEMPROT_PMS_AREA_DRAM0_2, &check_val, DEFAULT_CPU_NUM))
if (check_val != (MEMPROT_OP_READ | MEMPROT_OP_WRITE)) {
esp_rom_printf("Fatal error: DRAM0 PMS AREA_2 configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
MEMPROT_OP_READ | MEMPROT_OP_WRITE, check_val);
esp_rom_printf("Fatal error: DRAM0 PMS AREA_2 configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
(uint32_t)MEMPROT_OP_READ | MEMPROT_OP_WRITE, check_val);
abort();
}
ESP_MEMPROT_ERR_CHECK(ret, esp_mprot_get_pms_area(MEMPROT_PMS_AREA_DRAM0_3, &check_val, DEFAULT_CPU_NUM))
if (check_val != (MEMPROT_OP_READ | MEMPROT_OP_WRITE)) {
esp_rom_printf("Fatal error: DRAM0 PMS AREA_3 configuration corrupted (expected 0x%08X, stored 0x%08X)\n",
MEMPROT_OP_READ | MEMPROT_OP_WRITE, check_val);
esp_rom_printf("Fatal error: DRAM0 PMS AREA_3 configuration corrupted (expected 0x%08" PRIX32 ", stored 0x%08" PRIX32 ")\n",
(uint32_t)MEMPROT_OP_READ | MEMPROT_OP_WRITE, check_val);
abort();
}

2
components/esp_hw_support/port/esp_clk_tree_common.c
View File

@ -64,7 +64,7 @@ static uint32_t clk_tree_rtc_slow_calibration(uint32_t slowclk_cycles)
cal_val = (uint32_t)(cal_dividend / source_approx_freq);
}
if (cal_val) {
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %"PRIu32"", cal_val);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
// Update the calibration value of RTC_SLOW_CLK
esp_clk_slowclk_cal_set(cal_val);
}

2
components/esp_hw_support/port/regdma_link.c
View File

@ -792,7 +792,7 @@ void regdma_link_show_memories(void *link, int entry)
print_link_info(next, entry, 0);
} while ((next = regdma_link_get_next(next, entry)) != NULL);
} else {
ESP_EARLY_LOGW(TAG, "This REGDMA linked list is empty!\n");
ESP_EARLY_LOGW(TAG, "This REGDMA linked list is empty!");
}
}
#endif

4
components/esp_mm/esp_cache.c
View File

@ -32,7 +32,7 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
uint32_t addr_end = 0;
bool ovf = __builtin_add_overflow((uint32_t)addr, size, &addr_end);
ESP_EARLY_LOGV(TAG, "addr_end: 0x%x\n", addr_end);
ESP_EARLY_LOGV(TAG, "addr_end: 0x%" PRIx32, addr_end);
ESP_RETURN_ON_FALSE_ISR(!ovf, ESP_ERR_INVALID_ARG, TAG, "wrong size, total size overflow");
bool both_dir = (flags & ESP_CACHE_MSYNC_FLAG_DIR_C2M) && (flags & ESP_CACHE_MSYNC_FLAG_DIR_M2C);
@ -53,7 +53,7 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
uint32_t cache_line_size = cache_hal_get_cache_line_size(cache_level, cache_type);
if ((flags & ESP_CACHE_MSYNC_FLAG_UNALIGNED) == 0) {
bool aligned_addr = (((uint32_t)addr % cache_line_size) == 0) && ((size % cache_line_size) == 0);
ESP_RETURN_ON_FALSE_ISR(aligned_addr, ESP_ERR_INVALID_ARG, TAG, "start address: 0x%x, or the size: 0x%x is(are) not aligned with cache line size (0x%x)B", (uint32_t)addr, size, cache_line_size);
ESP_RETURN_ON_FALSE_ISR(aligned_addr, ESP_ERR_INVALID_ARG, TAG, "start address: 0x%" PRIx32 ", or the size: 0x%" PRIx32 " is(are) not aligned with cache line size (0x%" PRIx32 ")B", (uint32_t)addr, (uint32_t)size, cache_line_size);
}
if (flags & ESP_CACHE_MSYNC_FLAG_DIR_M2C) {

14
components/esp_mm/esp_mmu_map.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -233,7 +233,7 @@ void esp_mmu_map_init(void)
region_num++;
}
}
ESP_EARLY_LOGV(TAG, "after coalescing, %d regions are left", region_num);
ESP_EARLY_LOGV(TAG, "after coalescing, %" PRIu32 " regions are left", region_num);
//Initialise `s_mmu_ctx.mem_regions[]`, as we've done all static allocation, to prepare available virtual memory regions
uint32_t available_region_idx = 0;
@ -318,7 +318,7 @@ esp_err_t esp_mmu_map_reserve_block_with_caps(size_t size, mmu_mem_caps_t caps,
laddr = (uint32_t)s_mmu_ctx.mem_regions[found_region_id].free_head;
s_mmu_ctx.mem_regions[found_region_id].free_head += aligned_size;
s_mmu_ctx.mem_regions[found_region_id].max_slot_size -= aligned_size;
ESP_EARLY_LOGV(TAG, "found laddr is 0x%x", laddr);
ESP_EARLY_LOGV(TAG, "found laddr is 0x%" PRIx32, laddr);
uint32_t vaddr = 0;
if (caps & MMU_MEM_CAP_EXEC) {
@ -727,15 +727,15 @@ esp_err_t IRAM_ATTR esp_mmu_map_dump_mapped_blocks_private(void)
ESP_DRAM_LOGI(TAG, "block vaddr_start: 0x%x", mem_block->vaddr_start);
ESP_DRAM_LOGI(TAG, "block vaddr_end: 0x%x", mem_block->vaddr_end);
ESP_DRAM_LOGI(TAG, "block size: 0x%x", mem_block->size);
ESP_DRAM_LOGI(TAG, "block caps: 0x%x\n", mem_block->caps);
ESP_DRAM_LOGI(TAG, "block paddr_start: 0x%x\n", mem_block->paddr_start);
ESP_DRAM_LOGI(TAG, "block paddr_end: 0x%x\n", mem_block->paddr_end);
ESP_DRAM_LOGI(TAG, "block caps: 0x%x", mem_block->caps);
ESP_DRAM_LOGI(TAG, "block paddr_start: 0x%x", mem_block->paddr_start);
ESP_DRAM_LOGI(TAG, "block paddr_end: 0x%x", mem_block->paddr_end);
}
}
ESP_DRAM_LOGI(TAG, "region bus_id: 0x%x", s_mmu_ctx.mem_regions[i].bus_id);
ESP_DRAM_LOGI(TAG, "region start: 0x%x", s_mmu_ctx.mem_regions[i].start);
ESP_DRAM_LOGI(TAG, "region end: 0x%x", s_mmu_ctx.mem_regions[i].end);
ESP_DRAM_LOGI(TAG, "region caps: 0x%x\n", s_mmu_ctx.mem_regions[i].caps);
ESP_DRAM_LOGI(TAG, "region caps: 0x%x", s_mmu_ctx.mem_regions[i].caps);
}
return ESP_OK;

4
components/esp_psram/esp32/esp_psram_impl_quad.c
View File

@ -902,7 +902,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init
psram_io.psram_clk_io = D0WDR2_V3_PSRAM_CLK_IO;
psram_io.psram_cs_io = D0WDR2_V3_PSRAM_CS_IO;
} else {
ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %d", pkg_ver);
ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %" PRIu32, pkg_ver);
abort();
}
s_psram_cs_io = psram_io.psram_cs_io;
@ -985,7 +985,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init
*/
psram_read_id(spi_num, &s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) {
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported", (uint32_t)s_psram_id);
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08" PRIx32 ", PSRAM chip not found or not supported", (uint32_t)s_psram_id);
return ESP_ERR_NOT_SUPPORTED;
}
}

2
components/esp_psram/esp32s2/esp_psram_impl_quad.c
View File

@ -435,7 +435,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init
*/
psram_read_id(spi_num, &s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) {
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported", (uint32_t)s_psram_id);
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08" PRIx32 ", PSRAM chip not found or not supported", (uint32_t)s_psram_id);
return ESP_ERR_NOT_SUPPORTED;
}
}

2
components/esp_psram/esp32s3/esp_psram_impl_quad.c
View File

@ -320,7 +320,7 @@ esp_err_t esp_psram_impl_enable(void) //psram init
*/
psram_read_id(SPI1_NUM, &s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) {
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)s_psram_id);
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08" PRIx32 ", PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)s_psram_id);
return ESP_ERR_NOT_SUPPORTED;
}
}

22
components/esp_psram/esp_psram.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -123,7 +123,7 @@ esp_err_t esp_psram_init(void)
ret = esp_psram_impl_get_physical_size(&psram_physical_size);
assert(ret == ESP_OK);
ESP_EARLY_LOGI(TAG, "Found %dMB PSRAM device", psram_physical_size / (1024 * 1024));
ESP_EARLY_LOGI(TAG, "Found %" PRIu32 "MB PSRAM device", psram_physical_size / (1024 * 1024));
ESP_EARLY_LOGI(TAG, "Speed: %dMHz", CONFIG_SPIRAM_SPEED);
#if CONFIG_IDF_TARGET_ESP32
#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
@ -159,7 +159,7 @@ esp_err_t esp_psram_init(void)
}
start_page += used_page;
psram_available_size -= MMU_PAGE_TO_BYTES(used_page);
ESP_EARLY_LOGV(TAG, "after copy .text, used page is %d, start_page is %d, psram_available_size is %d B", used_page, start_page, psram_available_size);
ESP_EARLY_LOGV(TAG, "after copy .text, used page is %" PRIu32 ", start_page is %" PRIu32 ", psram_available_size is %" PRIu32 " B", used_page, start_page, psram_available_size);
#endif //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
//------------------------------------Copy Flash .rodata to PSRAM-------------------------------------//
@ -171,7 +171,7 @@ esp_err_t esp_psram_init(void)
}
start_page += used_page;
psram_available_size -= MMU_PAGE_TO_BYTES(used_page);
ESP_EARLY_LOGV(TAG, "after copy .rodata, used page is %d, start_page is %d, psram_available_size is %d B", used_page, start_page, psram_available_size);
ESP_EARLY_LOGV(TAG, "after copy .rodata, used page is %" PRIu32 ", start_page is %" PRIu32 ", psram_available_size is %" PRIu32 " B", used_page, start_page, psram_available_size);
#endif //#if CONFIG_SPIRAM_RODATA
//----------------------------------Map the PSRAM physical range to MMU-----------------------------//
@ -202,7 +202,7 @@ esp_err_t esp_psram_init(void)
mmu_hal_map_region(0, MMU_TARGET_PSRAM0, (intptr_t)v_start_8bit_aligned, MMU_PAGE_TO_BYTES(start_page), size_to_map, &actual_mapped_len);
#endif
start_page += BYTES_TO_MMU_PAGE(actual_mapped_len);
ESP_EARLY_LOGV(TAG, "8bit-aligned-region: actual_mapped_len is 0x%x bytes", actual_mapped_len);
ESP_EARLY_LOGV(TAG, "8bit-aligned-region: actual_mapped_len is 0x%" PRIx32 " bytes", actual_mapped_len);
cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)v_start_8bit_aligned, actual_mapped_len);
cache_ll_l1_enable_bus(0, bus_mask);
@ -218,7 +218,7 @@ esp_err_t esp_psram_init(void)
s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size = size_to_map;
s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start = (intptr_t)v_start_8bit_aligned;
s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_end = (intptr_t)v_start_8bit_aligned + size_to_map;
ESP_EARLY_LOGV(TAG, "8bit-aligned-range: 0x%x B, starting from: 0x%x", s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].size, v_start_8bit_aligned);
ESP_EARLY_LOGV(TAG, "8bit-aligned-range: 0x%x B, starting from: %p", s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].size, v_start_8bit_aligned);
total_mapped_size += size_to_map;
#if CONFIG_IDF_TARGET_ESP32S2
@ -242,7 +242,7 @@ esp_err_t esp_psram_init(void)
assert(ret == ESP_OK);
mmu_hal_map_region(0, MMU_TARGET_PSRAM0, (intptr_t)v_start_32bit_aligned, MMU_PAGE_TO_BYTES(start_page), size_to_map, &actual_mapped_len);
ESP_EARLY_LOGV(TAG, "32bit-aligned-region: actual_mapped_len is 0x%x bytes", actual_mapped_len);
ESP_EARLY_LOGV(TAG, "32bit-aligned-region: actual_mapped_len is 0x%" PRIx32 " bytes", actual_mapped_len);
cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)v_start_32bit_aligned, actual_mapped_len);
cache_ll_l1_enable_bus(0, bus_mask);
@ -253,7 +253,7 @@ esp_err_t esp_psram_init(void)
s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].size = size_to_map;
s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_start = (intptr_t)v_start_32bit_aligned;
s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_end = (intptr_t)v_start_32bit_aligned + size_to_map;
ESP_EARLY_LOGV(TAG, "32bit-aligned-range: 0x%x B, starting from: 0x%x", s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].size, v_start_32bit_aligned);
ESP_EARLY_LOGV(TAG, "32bit-aligned-range: 0x%x B, starting from: %p", s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].size, v_start_32bit_aligned);
total_mapped_size += size_to_map;
}
#endif // #if CONFIG_IDF_TARGET_ESP32S2
@ -270,14 +270,14 @@ esp_err_t esp_psram_init(void)
#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
//should never be negative number
uint32_t ext_bss_size = ((intptr_t)&_ext_ram_bss_end - (intptr_t)&_ext_ram_bss_start);
ESP_EARLY_LOGV(TAG, "ext_bss_size is %d", ext_bss_size);
ESP_EARLY_LOGV(TAG, "ext_bss_size is %" PRIu32, ext_bss_size);
s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start += ext_bss_size;
s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size -= ext_bss_size;
#endif //#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
uint32_t ext_noinit_size = ((intptr_t)&_ext_ram_noinit_end - (intptr_t)&_ext_ram_noinit_start);
ESP_EARLY_LOGV(TAG, "ext_noinit_size is %d", ext_noinit_size);
ESP_EARLY_LOGV(TAG, "ext_noinit_size is %" PRIu32, ext_noinit_size);
s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start += ext_noinit_size;
s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size -= ext_noinit_size;
#endif
@ -417,7 +417,7 @@ static bool s_test_psram(intptr_t v_start, size_t size, intptr_t reserved_start,
}
}
if (errct) {
ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, size / 32, initial_err + v_start);
ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X", errct, size / 32, initial_err + v_start);
return false;
} else {
ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK");

10
components/esp_psram/mmu_psram_flash.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -56,7 +56,7 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size
flash_pages += Cache_Count_Flash_Pages(CACHE_IBUS, &page0_mapped);
#endif
if ((flash_pages + page_id) > BYTES_TO_MMU_PAGE(psram_size)) {
ESP_EARLY_LOGE(TAG, "PSRAM space not enough for the Flash instructions, need %d B, from %d B to %d B",
ESP_EARLY_LOGE(TAG, "PSRAM space not enough for the Flash instructions, need %" PRIu32 " B, from %" PRIu32 " B to %" PRIu32 " B",
MMU_PAGE_TO_BYTES(flash_pages), MMU_PAGE_TO_BYTES(start_page), MMU_PAGE_TO_BYTES(flash_pages + page_id));
return ESP_FAIL;
}
@ -77,7 +77,7 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size
#elif CONFIG_IDF_TARGET_ESP32S3
page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_IBUS, SOC_IRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
#endif
ESP_EARLY_LOGV(TAG, "after copy instruction, page_id is %d", page_id);
ESP_EARLY_LOGV(TAG, "after copy instruction, page_id is %" PRIu32, page_id);
ESP_EARLY_LOGI(TAG, "Instructions copied and mapped to SPIRAM");
*out_page = page_id - start_page;
@ -101,7 +101,7 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si
flash_pages += Cache_Count_Flash_Pages(CACHE_DBUS, &page0_mapped);
#endif
if ((flash_pages + page_id) > BYTES_TO_MMU_PAGE(psram_size)) {
ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the instructions, need to copy to %d B.", MMU_PAGE_TO_BYTES(flash_pages + page_id));
ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the instructions, need to copy to %" PRIu32 " B.", MMU_PAGE_TO_BYTES(flash_pages + page_id));
return ESP_FAIL;
}
@ -124,7 +124,7 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si
page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_DBUS, SOC_DRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
#endif
ESP_EARLY_LOGV(TAG, "after copy rodata, page_id is %d", page_id);
ESP_EARLY_LOGV(TAG, "after copy rodata, page_id is %" PRIu32, page_id);
ESP_EARLY_LOGI(TAG, "Read only data copied and mapped to SPIRAM");
*out_page = page_id - start_page;

1
components/esp_rom/include/esp_rom_sys.h
View File

@ -7,6 +7,7 @@
#pragma once
#include "sdkconfig.h"
#include <stdint.h>
#include <inttypes.h>
#include "soc/reset_reasons.h"
#ifdef __cplusplus

2
components/esp_system/port/arch/xtensa/debug_helpers.c
View File

@ -44,7 +44,7 @@ static void IRAM_ATTR print_entry(uint32_t pc, uint32_t sp, bool panic)
panic_print_str(":0x");
panic_print_hex(sp);
} else {
esp_rom_printf(" 0x%08X:0x%08X", pc, sp);
esp_rom_printf(" 0x%08" PRIX32 ":0x%08" PRIX32, pc, sp);
}
}

2
components/esp_system/port/soc/esp32/clk.c
View File

@ -102,7 +102,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
esp_clk_slowclk_cal_set(cal_val);
}

2
components/esp_system/port/soc/esp32c2/clk.c
View File

@ -172,7 +172,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
esp_clk_slowclk_cal_set(cal_val);
}

2
components/esp_system/port/soc/esp32c3/clk.c
View File

@ -181,7 +181,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
esp_clk_slowclk_cal_set(cal_val);
}

2
components/esp_system/port/soc/esp32c5/clk.c
View File

@ -165,7 +165,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
esp_clk_slowclk_cal_set(cal_val);
}

2
components/esp_system/port/soc/esp32c6/clk.c
View File

@ -160,7 +160,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
esp_clk_slowclk_cal_set(cal_val);
}

2
components/esp_system/port/soc/esp32h2/clk.c
View File

@ -162,7 +162,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
esp_clk_slowclk_cal_set(cal_val);
}

2
components/esp_system/port/soc/esp32p4/clk.c
View File

@ -155,7 +155,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
esp_clk_slowclk_cal_set(cal_val);
}

2
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -188,7 +188,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
esp_clk_slowclk_cal_set(cal_val);
}

2
components/esp_system/port/soc/esp32s3/clk.c
View File

@ -177,7 +177,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
esp_clk_slowclk_cal_set(cal_val);
}

2
components/esp_system/test_apps/esp_system_unity_tests/main/test_ipc_isr.c
View File

@ -61,7 +61,7 @@ TEST_CASE("Test ipc_isr blocking IPC function calls get_cycle_count_other_cpu",
{
int val = 0x5a5a;
esp_ipc_isr_call_blocking(esp_test_ipc_isr_get_cycle_count_other_cpu, &val);
esp_rom_printf("CCOUNT CPU0 = %d\n", esp_cpu_get_cycle_count());
esp_rom_printf("CCOUNT CPU0 = %" PRIu32 "\n", esp_cpu_get_cycle_count());
esp_rom_printf("CCOUNT CPU1 = %d\n", val);
}

34
components/espcoredump/src/core_dump_binary.c
View File

@ -41,14 +41,14 @@ static esp_err_t esp_core_dump_save_task(core_dump_write_data_t *write_data, cor
// Save task stack
err = esp_core_dump_write_data(write_data, (void *)stk_paddr, stk_len);
if (err != ESP_OK) {
ESP_COREDUMP_LOGE("Failed to write stack for task (TCB:%x), stack_start=%x, error=%d!",
ESP_COREDUMP_LOGE("Failed to write stack for task (TCB:%p), stack_start=%" PRIx32 ", error=%d!",
task->tcb_addr,
stk_vaddr,
err);
return err;
}
ESP_COREDUMP_LOG_PROCESS("Task (TCB:%x) dump is saved.", task->tcb_addr);
ESP_COREDUMP_LOG_PROCESS("Task (TCB:%p) dump is saved.", task->tcb_addr);
return ESP_OK;
}
@ -59,7 +59,7 @@ static esp_err_t esp_core_dump_save_mem_segment(core_dump_write_data_t* write_da
esp_err_t err = ESP_FAIL;
if (!esp_core_dump_mem_seg_is_sane(seg->start, seg->size)) {
ESP_COREDUMP_LOGE("Failed to write memory segment, (%x, %lu)!",
ESP_COREDUMP_LOGE("Failed to write memory segment, (%" PRIx32 ", %" PRIu32 ")!",
seg->start, seg->size);
return ESP_FAIL;
}
@ -72,11 +72,11 @@ static esp_err_t esp_core_dump_save_mem_segment(core_dump_write_data_t* write_da
// Save memory contents
err = esp_core_dump_write_data(write_data, (void *)seg->start, seg->size);
if (err != ESP_OK) {
ESP_COREDUMP_LOGE("Failed to write memory segment, (%x, %lu), error=%d!",
ESP_COREDUMP_LOGE("Failed to write memory segment, (%" PRIx32 ", %" PRIu32 "), error=%d!",
seg->start, seg->size, err);
return err;
}
ESP_COREDUMP_LOG_PROCESS("Memory segment (%x, %lu) is saved.",
ESP_COREDUMP_LOG_PROCESS("Memory segment (%" PRIx32 ", %" PRIu32 ") is saved.",
seg->start, seg->size);
return ESP_OK;
}
@ -110,9 +110,9 @@ static esp_err_t esp_core_dump_write_binary(void)
hdr.tasks_num++;
if (task_iter.pxTaskHandle == esp_core_dump_get_current_task_handle()) {
cur_task = task_iter.pxTaskHandle;
ESP_COREDUMP_LOG_PROCESS("Task %x %x is first crashed task.", cur_task, task_hdr.tcb_addr);
ESP_COREDUMP_LOG_PROCESS("Task %p %p is first crashed task.", cur_task, task_hdr.tcb_addr);
}
ESP_COREDUMP_LOG_PROCESS("Stack len = %lu (%x %x)", task_hdr.stack_end - task_hdr.stack_start,
ESP_COREDUMP_LOG_PROCESS("Stack len = %" PRIu32 " (%" PRIx32 " %" PRIx32 ")", task_hdr.stack_end - task_hdr.stack_start,
task_hdr.stack_start, task_hdr.stack_end);
// Increase core dump size by task stack size
uint32_t stk_vaddr = 0;
@ -122,14 +122,14 @@ static esp_err_t esp_core_dump_write_binary(void)
// Add tcb size
data_len += (tcb_sz + sizeof(core_dump_task_header_t));
if (mem_seg.size > 0) {
ESP_COREDUMP_LOG_PROCESS("Add interrupted task stack %lu bytes @ %x",
ESP_COREDUMP_LOG_PROCESS("Add interrupted task stack %" PRIu32 " bytes @ %" PRIx32,
mem_seg.size, mem_seg.start);
data_len += esp_core_dump_get_memory_len(mem_seg.start, mem_seg.start + mem_seg.size);
data_len += sizeof(core_dump_mem_seg_header_t);
hdr.mem_segs_num++;
}
}
ESP_COREDUMP_LOGI("Found tasks: good %d, bad %d, mem segs %d", hdr.tasks_num, bad_tasks_num, hdr.mem_segs_num);
ESP_COREDUMP_LOGI("Found tasks: good %" PRIu32 ", bad %" PRIu32 ", mem segs %" PRIu32, hdr.tasks_num, bad_tasks_num, hdr.mem_segs_num);
// Check if current task TCB is broken
if (cur_task == NULL) {
@ -164,7 +164,7 @@ static esp_err_t esp_core_dump_write_binary(void)
// Add core dump header size
data_len += sizeof(core_dump_header_t);
ESP_COREDUMP_LOG_PROCESS("Core dump length=%lu, tasks processed: %d, broken tasks: %d",
ESP_COREDUMP_LOG_PROCESS("Core dump length=%" PRIu32 ", tasks processed: %" PRIu32 ", broken tasks: %" PRIu32,
data_len, hdr.tasks_num, bad_tasks_num);
// Prepare write
err = esp_core_dump_write_prepare(&write_data, &data_len);
@ -194,11 +194,11 @@ static esp_err_t esp_core_dump_write_binary(void)
// Save tasks
esp_core_dump_reset_tasks_snapshots_iter();
// Write first crashed task data first (not always first task in the snapshot)
ESP_COREDUMP_LOGD("Save first crashed task %x", cur_task);
ESP_COREDUMP_LOGD("Save first crashed task %p", cur_task);
if (esp_core_dump_get_task_snapshot(cur_task, &task_hdr, NULL)) {
err = esp_core_dump_save_task(&write_data, &task_hdr);
if (err != ESP_OK) {
ESP_COREDUMP_LOGE("Failed to save first crashed task %x, error=%d!",
ESP_COREDUMP_LOGE("Failed to save first crashed task %p, error=%d!",
task_hdr.tcb_addr, err);
return err;
}
@ -213,11 +213,11 @@ static esp_err_t esp_core_dump_write_binary(void)
if (task_iter.pxTaskHandle == cur_task) {
continue;
}
ESP_COREDUMP_LOGD("Save task %x (TCB:%x, stack:%x..%x)",
ESP_COREDUMP_LOGD("Save task %p (TCB:%p, stack:%" PRIx32 "..%" PRIx32 ")",
task_iter.pxTaskHandle, task_hdr.tcb_addr, task_hdr.stack_start, task_hdr.stack_end);
err = esp_core_dump_save_task(&write_data, &task_hdr);
if (err != ESP_OK) {
ESP_COREDUMP_LOGE("Failed to save core dump task %x, error=%d!",
ESP_COREDUMP_LOGE("Failed to save core dump task %p, error=%d!",
task_hdr.tcb_addr, err);
return err;
}
@ -232,7 +232,7 @@ static esp_err_t esp_core_dump_write_binary(void)
continue;
}
if (mem_seg.size > 0) {
ESP_COREDUMP_LOG_PROCESS("Save interrupted task stack %lu bytes @ %x",
ESP_COREDUMP_LOG_PROCESS("Save interrupted task stack %" PRIu32 " bytes @ %" PRIx32,
mem_seg.size, mem_seg.start);
err = esp_core_dump_save_mem_segment(&write_data, &mem_seg);
if (err != ESP_OK) {
@ -256,7 +256,7 @@ static esp_err_t esp_core_dump_write_binary(void)
if (data_sz > 0) {
mem_seg.start = start;
mem_seg.size = esp_core_dump_get_memory_len(start, start + data_sz);;
ESP_COREDUMP_LOG_PROCESS("Save user memory region %lu bytes @ %x",
ESP_COREDUMP_LOG_PROCESS("Save user memory region %" PRIu32 " bytes @ %" PRIx32,
mem_seg.size, mem_seg.start);
err = esp_core_dump_save_mem_segment(&write_data, &mem_seg);
if (err != ESP_OK) {
@ -275,7 +275,7 @@ static esp_err_t esp_core_dump_write_binary(void)
}
if (bad_tasks_num) {
ESP_COREDUMP_LOGE("Found %d broken tasks!", bad_tasks_num);
ESP_COREDUMP_LOGE("Found %" PRIu32 " broken tasks!", bad_tasks_num);
}
return err;
}

12
components/espcoredump/src/core_dump_common.c
View File

@ -85,7 +85,7 @@ FORCE_INLINE_ATTR void esp_core_dump_setup_stack(void)
* current stack pointer, in order to be able too restore it later.
* This function must be inlined. */
esp_core_dump_replace_sp(s_core_dump_sp, &s_stack_context);
ESP_COREDUMP_LOGI("Backing up stack @ %p and use core dump stack @ %p",
ESP_COREDUMP_LOGI("Backing up stack @ 0x%" PRIx32 " and use core dump stack @ %p",
s_stack_context.sp, esp_cpu_get_sp());
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
@ -120,12 +120,12 @@ FORCE_INLINE_ATTR void esp_core_dump_report_stack_usage(void)
{
#if CONFIG_ESP_COREDUMP_LOGS
uint32_t bytes_free = esp_core_dump_free_stack_space(s_coredump_stack);
ESP_COREDUMP_LOGI("Core dump used %u bytes on stack. %u bytes left free.",
ESP_COREDUMP_LOGI("Core dump used %" PRIu32 " bytes on stack. %" PRIu32 " bytes left free.",
s_core_dump_sp - s_coredump_stack - bytes_free, bytes_free);
#endif
/* Restore the stack pointer. */
ESP_COREDUMP_LOGI("Restoring stack @ %p", s_stack_context.sp);
ESP_COREDUMP_LOGI("Restoring stack @ 0x%" PRIx32, s_stack_context.sp);
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
esp_hw_stack_guard_monitor_stop();
#endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD
@ -196,7 +196,7 @@ static void esp_core_dump_switch_task_stack_to_isr(core_dump_task_header_t *task
}
task->stack_start = (uint32_t) s_exc_frame;
task->stack_end = esp_core_dump_get_isr_stack_end();
ESP_COREDUMP_LOG_PROCESS("Switched task %x to ISR stack [%x...%x]", task->tcb_addr,
ESP_COREDUMP_LOG_PROCESS("Switched task %p to ISR stack [%" PRIx32 "...%" PRIx32 "]", task->tcb_addr,
task->stack_start,
task->stack_end);
}
@ -226,11 +226,11 @@ bool esp_core_dump_get_task_snapshot(void *handle, core_dump_task_header_t *task
task->stack_start = (uint32_t) s_exc_frame;
}
if (!esp_core_dump_check_task(task)) {
ESP_COREDUMP_LOG_PROCESS("Task %x is broken!", handle);
ESP_COREDUMP_LOG_PROCESS("Task %p is broken!", handle);
return false;
}
if (handle == esp_core_dump_get_current_task_handle()) {
ESP_COREDUMP_LOG_PROCESS("Crashed task %x", handle);
ESP_COREDUMP_LOG_PROCESS("Crashed task %p", handle);
esp_core_dump_port_set_crashed_tcb((uint32_t)handle);
if (esp_core_dump_in_isr_context()) {
esp_core_dump_switch_task_stack_to_isr(task, interrupted_stack);

4
components/espcoredump/src/core_dump_crc.c
View File

@ -27,7 +27,7 @@ static void core_dump_crc_print(const char *msg, const uint8_t *checksum)
if (msg != NULL) {
ESP_COREDUMP_PRINT("%s=", msg);
}
ESP_COREDUMP_PRINT("'%08x'\r\n", *((const uint32_t*)checksum));
ESP_COREDUMP_PRINT("'%08" PRIx32 "'\r\n", *((const uint32_t*)checksum));
}
static uint32_t core_dump_crc_size(void)
@ -70,7 +70,7 @@ static uint32_t core_dump_crc_finish(core_dump_checksum_ctx cks_ctx, core_dump_c
*chs_ptr = (core_dump_checksum_bytes)&crc_ctx->crc;
}
ESP_COREDUMP_LOG_PROCESS("Total length of hashed data: %d", crc_ctx->total_bytes_checksum);
ESP_COREDUMP_LOG_PROCESS("Total length of hashed data: %" PRIu32, crc_ctx->total_bytes_checksum);
}
return core_dump_crc_size();