From d63beec0952db4e16f351e080267a1868b869548 Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Wed, 26 Jun 2024 20:38:39 +0800 Subject: [PATCH 1/7] change(esp_wifi): support legacy wifi power save for esp32c5 --- components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld | 2 +- components/esp_wifi/lib | 2 +- components/soc/esp32c5/include/soc/Kconfig.soc_caps.in | 8 ++++++++ components/soc/esp32c5/include/soc/soc_caps.h | 4 ++-- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld index 59e9a49df3..a72cb8e5b7 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld @@ -55,7 +55,7 @@ dbg_hal_check_clr_mplen_bitmap = 0x40000c6c; dbg_hal_check_set_mplen_bitmap = 0x40000c70; ic_get_trc = 0x40000c74; ic_mac_deinit = 0x40000c78; -ic_mac_init = 0x40000c7c; +/* ic_mac_init = 0x40000c7c; */ ic_interface_enabled = 0x40000c80; is_lmac_idle = 0x40000c84; ic_get_he_rts_threshold_bytes = 0x40000c88; diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index 6b249f7335..ad8411567d 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit 6b249f7335ed8e341c111a51b4d368d1825ac3c6 +Subproject commit ad8411567dc96a9d7fd13d275e6657c223287388 diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index b2236ecd95..6763369e58 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1251,6 +1251,10 @@ config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN bool default y +config SOC_PM_SUPPORT_WIFI_WAKEUP + bool + default y + config SOC_PM_SUPPORT_CPU_PD bool default y @@ -1283,6 +1287,10 @@ config SOC_PM_SUPPORT_HP_AON_PD bool default y +config SOC_PM_SUPPORT_MAC_BB_PD + bool + default y + config SOC_PM_SUPPORT_RTC_PERIPH_PD bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index fcd5bacef4..64c1da610d 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -539,7 +539,7 @@ #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) /*-------------------------- Power Management CAPS ----------------------------*/ -// #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) +#define SOC_PM_SUPPORT_WIFI_WAKEUP (1) // #define SOC_PM_SUPPORT_BEACON_WAKEUP (1) #define SOC_PM_SUPPORT_BT_WAKEUP (1) #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) @@ -552,7 +552,7 @@ #define SOC_PM_SUPPORT_VDDSDIO_PD (1) #define SOC_PM_SUPPORT_TOP_PD (1) #define SOC_PM_SUPPORT_HP_AON_PD (1) -// #define SOC_PM_SUPPORT_MAC_BB_PD (1) +#define SOC_PM_SUPPORT_MAC_BB_PD (1) #define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) // #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1) From 1604cef916e8e4a5daff1ef8e61f694bcd483f12 Mon Sep 17 00:00:00 2001 From: Lou Tianhao Date: Wed, 17 Apr 2024 20:09:55 +0800 Subject: [PATCH 2/7] chanage(example/power_save): add wifi band (2.4 GHz and 5 GHz) menuconfig option for esp32c5 --- examples/wifi/power_save/main/Kconfig.projbuild | 15 +++++++++++++++ examples/wifi/power_save/main/power_save.c | 12 ++++++++++++ 2 files changed, 27 insertions(+) diff --git a/examples/wifi/power_save/main/Kconfig.projbuild b/examples/wifi/power_save/main/Kconfig.projbuild index 21a9f4c49c..f0faf6cea7 100644 --- a/examples/wifi/power_save/main/Kconfig.projbuild +++ b/examples/wifi/power_save/main/Kconfig.projbuild @@ -37,6 +37,21 @@ menu "Example Configuration" For Station, If the station does not receive a beacon frame from the connected SoftAP during the inactive time, disconnect from SoftAP. Default 6s. + choice EXAMPLE_WIFI_BAND_MODE + prompt "wifi band" + default EXAMPLE_WIFI_BAND_MODE_2G + depends on SOC_WIFI_HE_SUPPORT_5G + help + WiFi band for the example to use. + + config EXAMPLE_WIFI_BAND_MODE_2G + bool "2G" + config EXAMPLE_WIFI_BAND_MODE_5G + bool "5G" + config EXAMPLE_WIFI_BAND_MODE_AUTO + bool "Auto" + endchoice + choice EXAMPLE_POWER_SAVE_MODE prompt "power save mode" default EXAMPLE_POWER_SAVE_MIN_MODEM diff --git a/examples/wifi/power_save/main/power_save.c b/examples/wifi/power_save/main/power_save.c index d804974d65..bb35a5c362 100644 --- a/examples/wifi/power_save/main/power_save.c +++ b/examples/wifi/power_save/main/power_save.c @@ -36,6 +36,15 @@ #define DEFAULT_PS_MODE WIFI_PS_NONE #endif /*CONFIG_POWER_SAVE_MODEM*/ +#if SOC_WIFI_HE_SUPPORT_5G +#if CONFIG_EXAMPLE_WIFI_BAND_MODE_2G +#define DEFAULT_WIFI_BAND_MODE WIFI_BAND_MODE_2G_ONLY +#elif CONFIG_EXAMPLE_WIFI_BAND_MODE_5G +#define DEFAULT_WIFI_BAND_MODE WIFI_BAND_MODE_5G_ONLY +#else +#define DEFAULT_WIFI_BAND_MODE WIFI_BAND_MODE_AUTO +#endif +#endif static const char *TAG = "power_save"; @@ -80,6 +89,9 @@ static void wifi_power_save(void) ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA)); ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &wifi_config)); ESP_ERROR_CHECK(esp_wifi_start()); +#if SOC_WIFI_HE_SUPPORT_5G + ESP_ERROR_CHECK(esp_wifi_set_band_mode(DEFAULT_WIFI_BAND_MODE)); +#endif ESP_ERROR_CHECK(esp_wifi_set_inactive_time(WIFI_IF_STA, DEFAULT_BEACON_TIMEOUT)); ESP_LOGI(TAG, "esp_wifi_set_ps()."); From eeb55c3f040d4667de190b7a7c4818ea6275cb32 Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Thu, 27 Jun 2024 11:54:57 +0800 Subject: [PATCH 3/7] change(example/power_save): modify to support dfs min frequency select to 48 MHz xtal --- .../wifi/power_save/main/Kconfig.projbuild | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/examples/wifi/power_save/main/Kconfig.projbuild b/examples/wifi/power_save/main/Kconfig.projbuild index f0faf6cea7..2b3d5ae567 100644 --- a/examples/wifi/power_save/main/Kconfig.projbuild +++ b/examples/wifi/power_save/main/Kconfig.projbuild @@ -89,7 +89,7 @@ menu "Example Configuration" depends on !IDF_TARGET_ESP32C2 config EXAMPLE_MAX_CPU_FREQ_240 bool "240 MHz" - depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 + depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C5 endchoice config EXAMPLE_MAX_CPU_FREQ_MHZ @@ -107,27 +107,39 @@ menu "Example Configuration" Minimum CPU frequency to use for dynamic frequency scaling. Should be set to XTAL frequency or XTAL frequency divided by integer. + config EXAMPLE_MIN_CPU_FREQ_48M + bool "48 MHz (use with 48MHz XTAL)" + depends on XTAL_FREQ_48 || (XTAL_FREQ_AUTO && IDF_TARGET_ESP32C5) config EXAMPLE_MIN_CPU_FREQ_40M bool "40 MHz (use with 40MHz XTAL)" depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO + config EXAMPLE_MIN_CPU_FREQ_24M + bool "24 MHz (use with 48MHz XTAL)" + depends on XTAL_FREQ_48 || (XTAL_FREQ_AUTO && IDF_TARGET_ESP32C5) config EXAMPLE_MIN_CPU_FREQ_20M bool "20 MHz (use with 40MHz XTAL)" depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO + config EXAMPLE_MIN_CPU_FREQ_12M + bool "12 MHz (use with 48MHz XTAL)" + depends on XTAL_FREQ_48 || (XTAL_FREQ_AUTO && IDF_TARGET_ESP32C5) config EXAMPLE_MIN_CPU_FREQ_10M bool "10 MHz (use with 40MHz XTAL)" depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO config EXAMPLE_MIN_CPU_FREQ_26M bool "26 MHz (use with 26MHz XTAL)" - depends on XTAL_FREQ_26 || XTAL_FREQ_AUTO + depends on XTAL_FREQ_26 || (XTAL_FREQ_AUTO && IDF_TARGET_ESP32C2) config EXAMPLE_MIN_CPU_FREQ_13M bool "13 MHz (use with 26MHz XTAL)" - depends on XTAL_FREQ_26 || XTAL_FREQ_AUTO + depends on XTAL_FREQ_26 || (XTAL_FREQ_AUTO && IDF_TARGET_ESP32C2) endchoice config EXAMPLE_MIN_CPU_FREQ_MHZ int + default 48 if EXAMPLE_MIN_CPU_FREQ_48M default 40 if EXAMPLE_MIN_CPU_FREQ_40M + default 24 if EXAMPLE_MIN_CPU_FREQ_24M default 20 if EXAMPLE_MIN_CPU_FREQ_20M + default 12 if EXAMPLE_MIN_CPU_FREQ_12M default 10 if EXAMPLE_MIN_CPU_FREQ_10M default 26 if EXAMPLE_MIN_CPU_FREQ_26M default 13 if EXAMPLE_MIN_CPU_FREQ_13M From dad039e27fc4603a73378cbb9e17b49f72542819 Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Thu, 14 Dec 2023 15:19:29 +0800 Subject: [PATCH 4/7] change(esp_hw_support): support wifi modem state for esp32c5 --- .../lowpower/port/esp32c5/sleep_clock.c | 35 +++++- components/esp_hw_support/sleep_modem.c | 108 ++++++++++++++---- components/esp_phy/include/esp_private/phy.h | 33 ++++-- components/esp_phy/src/phy_common.c | 54 +++++++++ components/esp_phy/src/phy_init.c | 13 ++- .../esp32c5/include/soc/Kconfig.soc_caps.in | 12 ++ .../include/soc/retention_periph_defs.h | 2 + components/soc/esp32c5/include/soc/soc_caps.h | 7 +- 8 files changed, 224 insertions(+), 40 deletions(-) diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c index c6c263cd7f..19c936fda5 100644 --- a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c @@ -6,6 +6,7 @@ #include "esp_private/sleep_clock.h" #include "soc/pcr_reg.h" +#include "soc/rtc.h" #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" #include "soc/i2c_ana_mst_reg.h" @@ -14,13 +15,43 @@ static const char *TAG = "sleep_clock"; esp_err_t sleep_clock_system_retention_init(void *arg) { -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP const static sleep_retention_entries_config_t pcr_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 74, 0, 0, 0xffffffff, 0xffffffff, 0x7f7, 0x0), .owner = ENTRY(0) | ENTRY(1) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), PCR_AHB_FREQ_CONF_REG, 0, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */ + [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP + [2] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(2), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 74, 0, 0, 0xffffffff, 0xffffffff, 0x7f7, 0x0), .owner = ENTRY(0) | ENTRY(1) }, +#endif }; esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention"); + + const static sleep_retention_entries_config_t modem_ahb_config[] = { + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), PCR_AHB_FREQ_CONF_REG, 3, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(1) }, /* Set AHB bus frequency to 40 MHz under PMU MODEM state */ + [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(1) }, + }; + err = sleep_retention_entries_create(modem_ahb_config, ARRAY_SIZE(modem_ahb_config), REGDMA_LINK_PRI_4, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); + ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention, 4 level priority"); + +#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && CONFIG_XTAL_FREQ_AUTO + uint32_t xtal_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get(); + if (xtal_freq_mhz == SOC_XTAL_FREQ_48M) { + + /* For the 48 MHz main XTAL, we need regdma to configured BBPLL by exec + * the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master + * command memory */ + sleep_retention_entries_config_t bbpll_config[] = { + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST enable */ + [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(6), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0), .owner = ENTRY(1) }, + [2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(7), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), .owner = ENTRY(1) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST disable */ + }; + extern uint32_t phy_ana_i2c_master_burst_bbpll_config(void); + bbpll_config[1].config.write_wait.value = phy_ana_i2c_master_burst_bbpll_config(); + err = sleep_retention_entries_create(bbpll_config, ARRAY_SIZE(bbpll_config), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); + ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for bbpll configure, 0 level priority"); + } #endif + ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization"); return ESP_OK; } diff --git a/components/esp_hw_support/sleep_modem.c b/components/esp_hw_support/sleep_modem.c index d01de62c71..a9f1d1e25d 100644 --- a/components/esp_hw_support/sleep_modem.c +++ b/components/esp_hw_support/sleep_modem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #include "esp_log.h" #include "esp_attr.h" #include "esp_sleep.h" +#include "esp_check.h" #include "soc/soc_caps.h" #include "esp_private/pm_impl.h" #include "esp_private/sleep_modem.h" @@ -136,13 +137,21 @@ void IRAM_ATTR mac_bb_power_up_cb_execute(void) #if SOC_PM_SUPPORT_PMU_MODEM_STATE -#define PMU_RF_PWR_REG (0x600b0154) #define SARADC_TSENS_REG (0x6000e058) #define SARADC_TSENS_PU (BIT(22)) +#if CONFIG_IDF_TARGET_ESP32C6 +#define PMU_RF_PWR_REG (0x600b0154) #define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a00c0) #define FECOEX_SET_CHAN_EN (BIT(14)) #define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc) #define FECOEX_SET_CHAN_DONE (BIT(8)) +#elif CONFIG_IDF_TARGET_ESP32C5 +#define PMU_RF_PWR_REG (0x600b0158) +#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a001c) +#define FECOEX_SET_CHAN_EN (BIT(17)) +#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028) +#define FECOEX_SET_CHAN_DONE (BIT(8)) +#endif #define FECOEX_AGC_CONF_REG (0x600a7030) #define FECOEX_AGC_DIS (BIT(29)) #define WDEVTXQ_BLOCK (0x600A4ca8) @@ -150,15 +159,6 @@ void IRAM_ATTR mac_bb_power_up_cb_execute(void) #define MODEM_FE_DATA_BASE (0x600a0400) #define MODEM_FE_CTRL_BASE (0x600a0800) -#define I2C_BURST_VAL(host, start, end) (((host) << 31) | ((end) << 22) | ((start) << 16)) - -typedef struct { - struct { - uint8_t start, end; /* the start and end index of phy i2c master command memory */ - uint8_t host_id; /* phy i2c master host id */ - } config[2]; -} phy_i2c_master_command_attribute_t; - typedef struct sleep_modem_config { struct { void *phy_link; @@ -174,18 +174,63 @@ typedef struct sleep_modem_config { static sleep_modem_config_t s_sleep_modem = { .wifi.phy_link = NULL, .wifi.flags = 0 }; +#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC +static esp_err_t sleep_modem_phy_wifi_init(void *arg) +{ + #define WIFIMAC_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC)) + + static sleep_retention_entries_config_t wifi_modem_config[] = { + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = WIFIMAC_ENTRY() }, /* I2C MST enable */ + + /* PMU or software to trigger enable RF PHY */ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration enable */ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG, 0xf3800000, 0xf3800000, 1, 0), .owner = WIFIMAC_ENTRY() }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0), .owner = WIFIMAC_ENTRY() }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0), .owner = WIFIMAC_ENTRY() }, + [5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), .owner = WIFIMAC_ENTRY() }, + [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() }, + [8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0), .owner = WIFIMAC_ENTRY() }, + [9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0), .owner = WIFIMAC_ENTRY() }, + [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0), .owner = WIFIMAC_ENTRY() }, + + /* PMU to trigger enable RXBLOCK */ + [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0), .owner = WIFIMAC_ENTRY() }, + + /* PMU or software to trigger disable RF PHY */ + [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1), .owner = WIFIMAC_ENTRY() }, + [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 1), .owner = WIFIMAC_ENTRY() }, + [16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 1), .owner = WIFIMAC_ENTRY() }, + [17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG, 0, 0x400000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG, 0, 0xf3800000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration disable */ + + [20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), .owner = WIFIMAC_ENTRY() }, /* I2C MST disable */ + + /* PMU to trigger disable RXBLOCK */ + [21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() }, + + [24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() }, + [25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() } + }; + extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on); + wifi_modem_config[4].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true); + wifi_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false); + esp_err_t err = sleep_retention_entries_create(wifi_modem_config, ARRAY_SIZE(wifi_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY); + ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link for wifi modem state"); + return ESP_OK; +} +#endif + esp_err_t sleep_modem_wifi_modem_state_init(void) { esp_err_t err = ESP_OK; - phy_i2c_master_command_attribute_t cmd; - - /* get RF on or off configuration info of i2c master command memory */ - extern void phy_i2c_master_mem_cfg(phy_i2c_master_command_attribute_t *); - phy_i2c_master_mem_cfg(&cmd); - - ESP_LOGD(TAG, "Modem link i2c master configuration: (%d,%d,%d), (%d,%d,%d)", cmd.config[0].host_id, cmd.config[0].start, - cmd.config[0].end, cmd.config[1].host_id, cmd.config[1].start, cmd.config[1].end); +#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC static regdma_link_config_t wifi_modem_config[] = { [0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0), [1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0), @@ -228,8 +273,9 @@ esp_err_t sleep_modem_wifi_modem_state_init(void) [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0), [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1) }; - wifi_modem_config[7].write_wait.value = I2C_BURST_VAL(cmd.config[1].host_id, cmd.config[1].start, cmd.config[1].end); - wifi_modem_config[18].write_wait.value = I2C_BURST_VAL(cmd.config[0].host_id, cmd.config[0].start, cmd.config[0].end); + extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on); + wifi_modem_config[7].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true); + wifi_modem_config[18].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false); void *link = NULL; if (s_sleep_modem.wifi.phy_link == NULL) { @@ -248,13 +294,33 @@ esp_err_t sleep_modem_wifi_modem_state_init(void) s_sleep_modem.wifi.flags = 0; } } +#elif SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC + if (s_sleep_modem.wifi.phy_link == NULL) { + sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_modem_phy_wifi_init, .arg = NULL } } }; + err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param); + if (err == ESP_OK) { + err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY); + if (err == ESP_OK) { + s_sleep_modem.wifi.phy_link = sleep_retention_find_link_by_id(REGDMA_PHY_LINK(0x00)); + s_sleep_modem.wifi.flags = 0; + } + } + } +#endif return err; } __attribute__((unused)) void sleep_modem_wifi_modem_state_deinit(void) { if (s_sleep_modem.wifi.phy_link) { +#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC regdma_link_destroy(s_sleep_modem.wifi.phy_link, 0); +#elif SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC + esp_err_t err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY); + if (err == ESP_OK) { + sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY); + } +#endif s_sleep_modem.wifi.phy_link = NULL; s_sleep_modem.wifi.flags = 0; } diff --git a/components/esp_phy/include/esp_private/phy.h b/components/esp_phy/include/esp_private/phy.h index bf8ed949a6..1489ac889b 100644 --- a/components/esp_phy/include/esp_private/phy.h +++ b/components/esp_phy/include/esp_private/phy.h @@ -13,17 +13,12 @@ extern "C" { #define ESP_CAL_DATA_CHECK_FAIL 1 -typedef enum { - PHY_I2C_MST_CMD_TYPE_OFF = 0, - PHY_I2C_MST_CMD_TYPE_ON, - PHY_I2C_MST_CMD_TYPE_MAX -} phy_i2c_master_command_type_t; - typedef struct { + uint8_t cmd_type; /* the command type of the current phy i2c master command memory config */ struct { uint8_t start, end; /* the start and end index of phy i2c master command memory */ uint8_t host_id; /* phy i2c master host id */ - } config[PHY_I2C_MST_CMD_TYPE_MAX]; + } config; } phy_i2c_master_command_attribute_t; /** @@ -88,13 +83,14 @@ void phy_xpd_tsens(void); void phy_init_flag(void); #endif -#if CONFIG_IDF_TARGET_ESP32C6 +#if SOC_PM_SUPPORT_PMU_MODEM_STATE /** * @brief Get the configuration info of PHY i2c master command memory. * - * @param attr the configuration info of PHY i2c master command memory + * @param[out] attr the configuration info of PHY i2c master command memory + * @param[out] size the count of PHY i2c master command memory configuration */ -void phy_i2c_master_mem_cfg(phy_i2c_master_command_attribute_t *attr); +void phy_i2c_master_command_mem_cfg(phy_i2c_master_command_attribute_t *attr, int *size); #endif /** @@ -217,6 +213,23 @@ void phy_ant_clr_update_flag(void); */ void phy_ant_update(void); +#if SOC_PM_SUPPORT_PMU_MODEM_STATE +/** + * @brief Get the REGDMA config value of the BBPLL in analog i2c master burst mode + * + * @return the BBPLL REGDMA configure value of i2c master burst mode + */ +uint32_t phy_ana_i2c_master_burst_bbpll_config(void); + +/** + * @brief Get the REGDMA config value of the RF PHY on or off in analog i2c master burst mode + * + * @param[in] on true for enable RF PHY, false for disable RF PHY. + * + * @return the RF on or off configure value of i2c master burst mode + */ +uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on); +#endif #ifdef __cplusplus } diff --git a/components/esp_phy/src/phy_common.c b/components/esp_phy/src/phy_common.c index cabd9ee1eb..2a3ed122b3 100644 --- a/components/esp_phy/src/phy_common.c +++ b/components/esp_phy/src/phy_common.c @@ -294,3 +294,57 @@ esp_err_t esp_phy_get_ant(esp_phy_ant_config_t *config) memcpy(config, &s_phy_ant_config, sizeof(esp_phy_ant_config_t)); return ESP_OK; } + +#if SOC_PM_SUPPORT_PMU_MODEM_STATE +typedef enum { + PHY_I2C_MST_CMD_TYPE_RF_OFF = 0, + PHY_I2C_MST_CMD_TYPE_RF_ON, + PHY_I2C_MST_CMD_TYPE_BBPLL_CFG, + PHY_I2C_MST_CMD_TYPE_MAX +} phy_i2c_master_command_type_t; + +static uint32_t phy_ana_i2c_master_burst_config(phy_i2c_master_command_attribute_t *attr, int size, phy_i2c_master_command_type_t type) +{ + #define I2C1_BURST_VAL(en, start, end) (((en) << 31) | ((end) << 22) | ((start) << 16)) + #define I2C0_BURST_VAL(en, start, end) (((en) << 15) | ((end) << 6) | ((start) << 0)) + + uint32_t brust = 0; + for (int i = 0; i < size; i++) { + if (attr[i].config.start == 0xff || attr[i].config.end == 0xff) /* ignore invalid configure */ + continue; + + if (attr[i].cmd_type == type) { + if (attr[i].config.host_id) { + brust |= I2C1_BURST_VAL(1, attr[i].config.start, attr[i].config.end); + } else { + brust |= I2C0_BURST_VAL(1, attr[i].config.start, attr[i].config.end); + } + } + } + return brust; +} + +uint32_t phy_ana_i2c_master_burst_bbpll_config(void) +{ + /* PHY supports 2 I2C masters, and the maximum number of configurations + * supported by the I2C master command memory is the command type + * (PHY_I2C_MST_CMD_TYPE_MAX) multiplied by 2 */ + phy_i2c_master_command_attribute_t cmd[2 * PHY_I2C_MST_CMD_TYPE_MAX]; + int size = sizeof(cmd) / sizeof(cmd[0]); + phy_i2c_master_command_mem_cfg(cmd, &size); + + return phy_ana_i2c_master_burst_config(cmd, size, PHY_I2C_MST_CMD_TYPE_BBPLL_CFG); +} + +uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on) +{ + /* PHY supports 2 I2C masters, and the maximum number of configurations + * supported by the I2C master command memory is the command type + * (PHY_I2C_MST_CMD_TYPE_MAX) multiplied by 2 */ + phy_i2c_master_command_attribute_t cmd[2 * PHY_I2C_MST_CMD_TYPE_MAX]; + int size = sizeof(cmd) / sizeof(cmd[0]); + phy_i2c_master_command_mem_cfg(cmd, &size); + + return phy_ana_i2c_master_burst_config(cmd, size, on ? PHY_I2C_MST_CMD_TYPE_RF_ON : PHY_I2C_MST_CMD_TYPE_RF_OFF); +} +#endif diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c index 554d1fa859..bc495b3031 100644 --- a/components/esp_phy/src/phy_init.c +++ b/components/esp_phy/src/phy_init.c @@ -45,7 +45,7 @@ #if CONFIG_IDF_TARGET_ESP32 #include "soc/dport_reg.h" -#elif CONFIG_IDF_TARGET_ESP32C6 +#elif SOC_PM_SUPPORT_PMU_MODEM_STATE #include "esp_private/sleep_modem.h" #endif #include "hal/efuse_hal.h" @@ -383,7 +383,7 @@ void esp_phy_modem_init(void) s_phy_digital_regs_mem = (uint32_t *)heap_caps_malloc(SOC_PHY_DIG_REGS_MEM_SIZE, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL); } #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA -#if CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP +#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP sleep_modem_wifi_modem_state_init(); #endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP _lock_release(&s_phy_access_lock); @@ -408,7 +408,7 @@ void esp_phy_modem_deinit(void) phy_init_flag(); #endif // CONFIG_IDF_TARGET_ESP32C3 #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA -#if CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP +#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP sleep_modem_wifi_modem_state_deinit(); #endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP } @@ -431,7 +431,12 @@ static esp_err_t sleep_retention_wifi_bb_init(void *arg) [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, 14, 0, 0), .owner = BIT(0) | BIT(1) }, /* TX */ [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, 136, 0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */ [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, 53, 0, 0), .owner = BIT(0) | BIT(1) }, /* BB */ - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, 58, 0, 0), .owner = BIT(0) | BIT(1) } /* FE COEX */ + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, 58, 0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */ +#ifndef SOC_PM_RETENTION_HAS_CLOCK_BUG + [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x000a8000, 39, 0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */ + [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, 41, 0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */ + [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, 87, 0, 0), .owner = BIT(0) | BIT(1) } /* FE CTRL */ +#endif }; esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB); ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB"); diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 6763369e58..9be97183ae 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1255,6 +1255,10 @@ config SOC_PM_SUPPORT_WIFI_WAKEUP bool default y +config SOC_PM_SUPPORT_BEACON_WAKEUP + bool + default y + config SOC_PM_SUPPORT_CPU_PD bool default y @@ -1295,6 +1299,10 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD bool default y +config SOC_PM_SUPPORT_PMU_MODEM_STATE + bool + default y + config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY bool default y @@ -1327,6 +1335,10 @@ config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE bool default y +config SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC + int + default 4 + config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION bool default y diff --git a/components/soc/esp32c5/include/soc/retention_periph_defs.h b/components/soc/esp32c5/include/soc/retention_periph_defs.h index ec8442305b..6fd2cdda6c 100644 --- a/components/soc/esp32c5/include/soc/retention_periph_defs.h +++ b/components/soc/esp32c5/include/soc/retention_periph_defs.h @@ -43,6 +43,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_BLE_MAC = 28, SLEEP_RETENTION_MODULE_BT_BB = 29, SLEEP_RETENTION_MODULE_802154_MAC = 30, + SLEEP_RETENTION_MODULE_MODEM_PHY = 31, SLEEP_RETENTION_MODULE_MAX = 31 } periph_retention_module_t; @@ -57,6 +58,7 @@ typedef enum periph_retention_module_bitmap { SLEEP_RETENTION_MODULE_BM_BLE_MAC = BIT(SLEEP_RETENTION_MODULE_BLE_MAC), SLEEP_RETENTION_MODULE_BM_BT_BB = BIT(SLEEP_RETENTION_MODULE_BT_BB), SLEEP_RETENTION_MODULE_BM_802154_MAC = BIT(SLEEP_RETENTION_MODULE_802154_MAC), + SLEEP_RETENTION_MODULE_BM_MODEM_PHY = BIT(SLEEP_RETENTION_MODULE_MODEM_PHY), /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */ diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 64c1da610d..2cad5a7f94 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -540,7 +540,7 @@ /*-------------------------- Power Management CAPS ----------------------------*/ #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) -// #define SOC_PM_SUPPORT_BEACON_WAKEUP (1) +#define SOC_PM_SUPPORT_BEACON_WAKEUP (1) #define SOC_PM_SUPPORT_BT_WAKEUP (1) #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*! Date: Tue, 3 Sep 2024 20:35:29 +0800 Subject: [PATCH 5/7] refactor(esp_hw_support): seperate sleep modem state support for each target --- .../include/esp_private/sleep_modem.h | 27 ++- .../esp_hw_support/lowpower/CMakeLists.txt | 4 + .../lowpower/port/esp32c5/sleep_modem_state.c | 120 +++++++++++++ .../lowpower/port/esp32c6/sleep_modem_state.c | 122 +++++++++++++ components/esp_hw_support/sleep_modem.c | 165 +----------------- 5 files changed, 275 insertions(+), 163 deletions(-) create mode 100644 components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c create mode 100644 components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c diff --git a/components/esp_hw_support/include/esp_private/sleep_modem.h b/components/esp_hw_support/include/esp_private/sleep_modem.h index 7922c24fc8..6ff4517766 100644 --- a/components/esp_hw_support/include/esp_private/sleep_modem.h +++ b/components/esp_hw_support/include/esp_private/sleep_modem.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -120,7 +120,7 @@ bool modem_domain_pd_allowed(void); uint32_t sleep_modem_reject_triggers(void); /** - * @brief Configure the parameters of the modem subsytem during the sleep process + * @brief Configure the parameters of the modem subsystem during the sleep process * * In light sleep mode, the wake-up early time of the WiFi module and the TBTT * interrupt early time (trigger enabling RF) are determined by the maximum and @@ -132,7 +132,7 @@ uint32_t sleep_modem_reject_triggers(void); * * @param max_freq_mhz the maximum frequency of system * @param min_freq_mhz the minimum frequency of system - * @param light_sleep_enable ture or false for enable or disable light sleep mode, respectively + * @param light_sleep_enable true or false for enable or disable light sleep mode, respectively * * @return * - ESP_OK on success @@ -225,6 +225,27 @@ void sleep_modem_wifi_modem_state_deinit(void); * - false not skip light sleep */ bool sleep_modem_wifi_modem_state_skip_light_sleep(void); + +/** + * @brief Function to initialize and create the modem state phy link + * @param link_head the pointer that point to the head of the created phy link + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM if no memory for link + * - ESP_ERR_INVALID_ARG if value is out of range + * - ESP_ERR_INVALID_STATE if the phy module retention state is invalid + */ +esp_err_t sleep_modem_state_phy_link_init(void **link_head); + +/** + * @brief Function to destroy and de-initialize modem state phy link + * @param link_head the phy link head will be destroyed + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if value is out of range + * - ESP_ERR_INVALID_STATE if the phy module retention state is invalid + */ +esp_err_t sleep_modem_state_phy_link_deinit(void *link_head); #endif #ifdef __cplusplus diff --git a/components/esp_hw_support/lowpower/CMakeLists.txt b/components/esp_hw_support/lowpower/CMakeLists.txt index 286b69d0d0..9525e68003 100644 --- a/components/esp_hw_support/lowpower/CMakeLists.txt +++ b/components/esp_hw_support/lowpower/CMakeLists.txt @@ -24,6 +24,10 @@ if((CONFIG_SOC_PM_SUPPORT_MODEM_PD OR CONFIG_SOC_PM_SUPPORT_TOP_PD) AND CONFIG_S list(APPEND srcs "port/${target}/sleep_clock.c") endif() +if(CONFIG_SOC_PM_SUPPORT_PMU_MODEM_STATE) + list(APPEND srcs "port/${target}/sleep_modem_state.c") +endif() + add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c new file mode 100644 index 0000000000..c2881711da --- /dev/null +++ b/components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c @@ -0,0 +1,120 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "esp_log.h" +#include "esp_check.h" + +#include "soc/soc_caps.h" +#include "soc/i2c_ana_mst_reg.h" +#include "soc/pmu_reg.h" + +#include "modem/modem_syscon_reg.h" +#include "modem/modem_lpcon_reg.h" + +#include "esp_private/sleep_modem.h" +#include "esp_private/sleep_retention.h" + +#if SOC_PM_SUPPORT_PMU_MODEM_STATE + +#define SARADC_TSENS_REG (0x6000e058) +#define SARADC_TSENS_PU (BIT(22)) +#define PMU_RF_PWR_REG (0x600b0158) + +#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a001c) +#define FECOEX_SET_CHAN_EN (BIT(17)) +#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028) +#define FECOEX_SET_CHAN_DONE (BIT(8)) +#define FECOEX_AGC_CONF_REG (0x600a7030) +#define FECOEX_AGC_DIS (BIT(29)) + +#define WDEVTXQ_BLOCK (0x600A4ca8) +#define WDEV_RXBLOCK (BIT(12)) +#define MODEM_FE_DATA_BASE (0x600a0400) +#define MODEM_FE_CTRL_BASE (0x600a0800) + +static __attribute__((unused)) const char *TAG = "sleep"; + +#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC +static esp_err_t sleep_modem_state_phy_wifi_init(void *arg) +{ + #define WIFIMAC_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC)) + + static sleep_retention_entries_config_t wifi_modem_config[] = { + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = WIFIMAC_ENTRY() }, /* I2C MST enable */ + + /* PMU or software to trigger enable RF PHY */ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration enable */ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG, 0xf3800000, 0xf3800000, 1, 0), .owner = WIFIMAC_ENTRY() }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0), .owner = WIFIMAC_ENTRY() }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0), .owner = WIFIMAC_ENTRY() }, + [5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), .owner = WIFIMAC_ENTRY() }, + [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() }, + [8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0), .owner = WIFIMAC_ENTRY() }, + [9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0), .owner = WIFIMAC_ENTRY() }, + [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0), .owner = WIFIMAC_ENTRY() }, + + /* PMU to trigger enable RXBLOCK */ + [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0), .owner = WIFIMAC_ENTRY() }, + + /* PMU or software to trigger disable RF PHY */ + [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1), .owner = WIFIMAC_ENTRY() }, + [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 1), .owner = WIFIMAC_ENTRY() }, + [16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 1), .owner = WIFIMAC_ENTRY() }, + [17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG, 0, 0x400000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG, 0, 0xf3800000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration disable */ + + [20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), .owner = WIFIMAC_ENTRY() }, /* I2C MST disable */ + + /* PMU to trigger disable RXBLOCK */ + [21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1), .owner = WIFIMAC_ENTRY() }, + [23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() }, + + [24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() }, + [25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() } + }; + extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on); + wifi_modem_config[4].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true); + wifi_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false); + esp_err_t err = sleep_retention_entries_create(wifi_modem_config, ARRAY_SIZE(wifi_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY); + ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link for wifi modem state"); + return ESP_OK; +} +#endif + +esp_err_t sleep_modem_state_phy_link_init(void **link_head) +{ + esp_err_t err = ESP_OK; + +#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC + sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_modem_state_phy_wifi_init, .arg = NULL } } }; + err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param); + if (err == ESP_OK) { + err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY); + if (err == ESP_OK) { + *link_head = sleep_retention_find_link_by_id(REGDMA_PHY_LINK(0x00)); + } + } +#endif + return err; +} + +esp_err_t sleep_modem_state_phy_link_deinit(void *link_head) +{ + esp_err_t err = ESP_OK; +#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC + err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY); + if (err == ESP_OK) { + sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY); + } +#endif + return err; +} + +#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */ diff --git a/components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c b/components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c new file mode 100644 index 0000000000..b374b70669 --- /dev/null +++ b/components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c @@ -0,0 +1,122 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "soc/soc_caps.h" +#include "soc/i2c_ana_mst_reg.h" +#include "soc/pmu_reg.h" + +#include "modem/modem_syscon_reg.h" +#include "modem/modem_lpcon_reg.h" + +#include "esp_private/esp_pau.h" +#include "esp_private/sleep_modem.h" +#include "esp_private/sleep_retention.h" + +#if SOC_PM_SUPPORT_PMU_MODEM_STATE + +#define SARADC_TSENS_REG (0x6000e058) +#define SARADC_TSENS_PU (BIT(22)) +#define PMU_RF_PWR_REG (0x600b0154) + +#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a00c0) +#define FECOEX_SET_CHAN_EN (BIT(14)) +#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc) +#define FECOEX_SET_CHAN_DONE (BIT(8)) +#define FECOEX_AGC_CONF_REG (0x600a7030) +#define FECOEX_AGC_DIS (BIT(29)) + +#define WDEVTXQ_BLOCK (0x600A4ca8) +#define WDEV_RXBLOCK (BIT(12)) +#define MODEM_FE_DATA_BASE (0x600a0400) +#define MODEM_FE_CTRL_BASE (0x600a0800) + +esp_err_t sleep_modem_state_phy_link_init(void **link_head) +{ + esp_err_t err = ESP_OK; + +#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC + static regdma_link_config_t wifi_modem_config[] = { + [0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0), + [1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0), + + [2] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), /* I2C MST enable */ + [3] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M, MODEM_LPCON_CLK_I2C_MST_SEL_160M_M, 1, 0), /* I2C MST sel 160m enable */ + + /* PMU or software to trigger enable RF PHY */ + [4] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), /* BBPLL calibration enable */ + [5] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG, 0xf0000000, 0xf0000000, 1, 0), + [6] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0), + [7] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0), + [8] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), + [9] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x07), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), + [10] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), + [11] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x4000, 1, 0), + [12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x4000, 1, 0), + [13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), PMU_DATE_REG, ~FECOEX_SET_CHAN_DONE, 0x100, 1, 0), + [14] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0c), PMU_DATE_REG, ~FECOEX_SET_CHAN_DONE, 0x100, 1, 0), + [15] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0d), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0), + [16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0), + [17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0), + + /* PMU to trigger enable RXBLOCK */ + [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0), + + /* PMU or software to trigger disable RF PHY */ + [19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1), + [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1), + [21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x4000, 0, 1), + [22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 0, 1), + [23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 0, 1), + [24] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x16), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 0, 1), + [25] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 0, 1), + [26] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), SARADC_TSENS_REG, 0, 0x400000, 0, 1), + [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_RF_PWR_REG, 0, 0xf0000000, 0, 1), + [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), /* BBPLL calibration disable */ + + [29] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), /* I2C MST disable */ + + /* PMU to trigger disable RXBLOCK */ + [30] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1c), PMU_DATE_REG, ~0, 0x6000, 0, 1), + [31] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1d), PMU_DATE_REG, ~0, 0x6000, 0, 1), + [32] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1e), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), + [33] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1f), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1), + [34] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x20), PMU_DATE_REG, ~0, 0x6000, 0, 1), + [35] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x21), PMU_DATE_REG, ~0, 0x6000, 0, 1), + [36] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x22), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), + + [37] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x23), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0), + [38] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x24), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1) + }; + extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on); + wifi_modem_config[7].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true); + wifi_modem_config[22].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false); + + void *link = NULL; + for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) { + void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link); + if (next) { + link = next; + } else { + regdma_link_destroy(link, 0); + err = ESP_ERR_NO_MEM; + } + } + if (err == ESP_OK) { + pau_regdma_set_modem_link_addr(link); + *link_head = link; + } +#endif + return err; +} + +esp_err_t sleep_modem_state_phy_link_deinit(void *link_head) +{ +#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC + regdma_link_destroy(link_head, 0); +#endif + return ESP_OK; +} + +#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */ diff --git a/components/esp_hw_support/sleep_modem.c b/components/esp_hw_support/sleep_modem.c index a9f1d1e25d..4c94f7229b 100644 --- a/components/esp_hw_support/sleep_modem.c +++ b/components/esp_hw_support/sleep_modem.c @@ -19,18 +19,12 @@ #include "esp_private/sleep_retention.h" #include "sdkconfig.h" -#if SOC_PM_MODEM_RETENTION_BY_REGDMA -#include "modem/modem_syscon_reg.h" -#include "modem/modem_lpcon_reg.h" -#include "soc/i2c_ana_mst_reg.h" -#include "esp_pau.h" -#endif - #if SOC_PM_SUPPORT_PMU_MODEM_STATE -#include "soc/pmu_reg.h" -#include "esp_private/esp_pau.h" #include "esp_private/esp_pmu.h" #endif +#if SOC_PM_MODEM_RETENTION_BY_REGDMA +#include "esp_pau.h" +#endif static __attribute__((unused)) const char *TAG = "sleep_modem"; @@ -137,28 +131,6 @@ void IRAM_ATTR mac_bb_power_up_cb_execute(void) #if SOC_PM_SUPPORT_PMU_MODEM_STATE -#define SARADC_TSENS_REG (0x6000e058) -#define SARADC_TSENS_PU (BIT(22)) -#if CONFIG_IDF_TARGET_ESP32C6 -#define PMU_RF_PWR_REG (0x600b0154) -#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a00c0) -#define FECOEX_SET_CHAN_EN (BIT(14)) -#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc) -#define FECOEX_SET_CHAN_DONE (BIT(8)) -#elif CONFIG_IDF_TARGET_ESP32C5 -#define PMU_RF_PWR_REG (0x600b0158) -#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a001c) -#define FECOEX_SET_CHAN_EN (BIT(17)) -#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028) -#define FECOEX_SET_CHAN_DONE (BIT(8)) -#endif -#define FECOEX_AGC_CONF_REG (0x600a7030) -#define FECOEX_AGC_DIS (BIT(29)) -#define WDEVTXQ_BLOCK (0x600A4ca8) -#define WDEV_RXBLOCK (BIT(12)) -#define MODEM_FE_DATA_BASE (0x600a0400) -#define MODEM_FE_CTRL_BASE (0x600a0800) - typedef struct sleep_modem_config { struct { void *phy_link; @@ -174,153 +146,26 @@ typedef struct sleep_modem_config { static sleep_modem_config_t s_sleep_modem = { .wifi.phy_link = NULL, .wifi.flags = 0 }; -#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC -static esp_err_t sleep_modem_phy_wifi_init(void *arg) -{ - #define WIFIMAC_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC)) - - static sleep_retention_entries_config_t wifi_modem_config[] = { - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = WIFIMAC_ENTRY() }, /* I2C MST enable */ - - /* PMU or software to trigger enable RF PHY */ - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration enable */ - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG, 0xf3800000, 0xf3800000, 1, 0), .owner = WIFIMAC_ENTRY() }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0), .owner = WIFIMAC_ENTRY() }, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0), .owner = WIFIMAC_ENTRY() }, - [5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), .owner = WIFIMAC_ENTRY() }, - [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() }, - [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() }, - [8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0), .owner = WIFIMAC_ENTRY() }, - [9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0), .owner = WIFIMAC_ENTRY() }, - [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0), .owner = WIFIMAC_ENTRY() }, - - /* PMU to trigger enable RXBLOCK */ - [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0), .owner = WIFIMAC_ENTRY() }, - - /* PMU or software to trigger disable RF PHY */ - [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1), .owner = WIFIMAC_ENTRY() }, - [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1), .owner = WIFIMAC_ENTRY() }, - [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 0, 1), .owner = WIFIMAC_ENTRY() }, - [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 1), .owner = WIFIMAC_ENTRY() }, - [16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 1), .owner = WIFIMAC_ENTRY() }, - [17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG, 0, 0x400000, 0, 1), .owner = WIFIMAC_ENTRY() }, - [18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG, 0, 0xf3800000, 0, 1), .owner = WIFIMAC_ENTRY() }, - [19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration disable */ - - [20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), .owner = WIFIMAC_ENTRY() }, /* I2C MST disable */ - - /* PMU to trigger disable RXBLOCK */ - [21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() }, - [22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1), .owner = WIFIMAC_ENTRY() }, - [23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() }, - - [24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() }, - [25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() } - }; - extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on); - wifi_modem_config[4].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true); - wifi_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false); - esp_err_t err = sleep_retention_entries_create(wifi_modem_config, ARRAY_SIZE(wifi_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY); - ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link for wifi modem state"); - return ESP_OK; -} -#endif esp_err_t sleep_modem_wifi_modem_state_init(void) { esp_err_t err = ESP_OK; -#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC - static regdma_link_config_t wifi_modem_config[] = { - [0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0), - [1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0), - - [2] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), /* I2C MST enable */ - [3] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M, MODEM_LPCON_CLK_I2C_MST_SEL_160M_M, 1, 0), /* I2C MST sel 160m enable */ - - /* PMU or software to trigger enable RF PHY */ - [4] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), /* BBPLL calibration enable */ - [5] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG, 0xf0000000, 0xf0000000, 1, 0), - [6] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0), - [7] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0), - [8] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x06), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), - [9] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x4000, 1, 0), - [10] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x4000, 1, 0), - [11] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0), - [12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0), - [13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0), - - /* PMU to trigger enable RXBLOCK */ - [14] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0), - - /* PMU or software to trigger disable RF PHY */ - [15] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1), - [16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1), - [17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x4000, 0, 1), - [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 0, 1), - [19] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x11), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 0, 1), - [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), SARADC_TSENS_REG, 0, 0x400000, 0, 1), - [21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), PMU_RF_PWR_REG, 0, 0xf0000000, 0, 1), - [22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), /* BBPLL calibration disable */ - - [23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), /* I2C MST disable */ - - /* PMU to trigger disable RXBLOCK */ - [24] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), - [25] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1), - [26] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x19), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), - - [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0), - [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1) - }; - extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on); - wifi_modem_config[7].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true); - wifi_modem_config[18].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false); - void *link = NULL; if (s_sleep_modem.wifi.phy_link == NULL) { - for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) { - void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link); - if (next) { - link = next; - } else { - regdma_link_destroy(link, 0); - err = ESP_ERR_NO_MEM; - } - } + err = sleep_modem_state_phy_link_init(&link); if (err == ESP_OK) { - pau_regdma_set_modem_link_addr(link); s_sleep_modem.wifi.phy_link = link; s_sleep_modem.wifi.flags = 0; } } -#elif SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC - if (s_sleep_modem.wifi.phy_link == NULL) { - sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_modem_phy_wifi_init, .arg = NULL } } }; - err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param); - if (err == ESP_OK) { - err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY); - if (err == ESP_OK) { - s_sleep_modem.wifi.phy_link = sleep_retention_find_link_by_id(REGDMA_PHY_LINK(0x00)); - s_sleep_modem.wifi.flags = 0; - } - } - } -#endif return err; } __attribute__((unused)) void sleep_modem_wifi_modem_state_deinit(void) { if (s_sleep_modem.wifi.phy_link) { -#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC - regdma_link_destroy(s_sleep_modem.wifi.phy_link, 0); -#elif SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC - esp_err_t err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY); - if (err == ESP_OK) { - sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY); - } -#endif + sleep_modem_state_phy_link_deinit(s_sleep_modem.wifi.phy_link); s_sleep_modem.wifi.phy_link = NULL; s_sleep_modem.wifi.flags = 0; } From 9588953e07117675b9fc963391e532ecd87a859f Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Fri, 13 Sep 2024 17:05:53 +0800 Subject: [PATCH 6/7] change(esp_phy): some fix for phy sleep --- components/esp_phy/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_phy/lib b/components/esp_phy/lib index 8608fcf54d..1f551c5367 160000 --- a/components/esp_phy/lib +++ b/components/esp_phy/lib @@ -1 +1 @@ -Subproject commit 8608fcf54d51e81f2e74ebf335fa33f61953f7c8 +Subproject commit 1f551c5367daa87a29e0c4f724d6cf809a1841ad From 072ea6bb4483e3508868592d7f4a8af7715344aa Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Mon, 2 Sep 2024 10:50:15 +0800 Subject: [PATCH 7/7] fix(ci): some modify for ci pass --- .../esp32c5/include/soc/Kconfig.soc_caps.in | 24 +++++++++---------- examples/wifi/.build-test-rules.yml | 2 +- examples/wifi/power_save/README.md | 4 ++-- .../wifi/power_save/main/Kconfig.projbuild | 1 + .../wifi/power_save/pytest_wifi_power_save.py | 1 + 5 files changed, 17 insertions(+), 15 deletions(-) diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 9be97183ae..0ac05a0ce3 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1239,6 +1239,14 @@ config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH int default 12 +config SOC_PM_SUPPORT_WIFI_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_BEACON_WAKEUP + bool + default y + config SOC_PM_SUPPORT_BT_WAKEUP bool default y @@ -1251,14 +1259,6 @@ config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN bool default y -config SOC_PM_SUPPORT_WIFI_WAKEUP - bool - default y - -config SOC_PM_SUPPORT_BEACON_WAKEUP - bool - default y - config SOC_PM_SUPPORT_CPU_PD bool default y @@ -1331,14 +1331,14 @@ config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE bool default y -config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE - bool - default y - config SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC int default 4 +config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE + bool + default y + config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION bool default y diff --git a/examples/wifi/.build-test-rules.yml b/examples/wifi/.build-test-rules.yml index 9e3af061dd..16229bb7ba 100644 --- a/examples/wifi/.build-test-rules.yml +++ b/examples/wifi/.build-test-rules.yml @@ -57,7 +57,7 @@ examples/wifi/itwt: examples/wifi/power_save: <<: *wifi_depends_default disable: - - if: (SOC_WIFI_SUPPORTED != 1) or (IDF_TARGET == "esp32c5") + - if: (SOC_WIFI_SUPPORTED != 1) disable_test: - if: IDF_TARGET == "esp32c61" temporary: true diff --git a/examples/wifi/power_save/README.md b/examples/wifi/power_save/README.md index 0b794afeff..473379d265 100644 --- a/examples/wifi/power_save/README.md +++ b/examples/wifi/power_save/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | # Wifi Power Save Example diff --git a/examples/wifi/power_save/main/Kconfig.projbuild b/examples/wifi/power_save/main/Kconfig.projbuild index 2b3d5ae567..877fe14b7b 100644 --- a/examples/wifi/power_save/main/Kconfig.projbuild +++ b/examples/wifi/power_save/main/Kconfig.projbuild @@ -101,6 +101,7 @@ menu "Example Configuration" choice EXAMPLE_MIN_CPU_FREQ prompt "Minimum CPU frequency" + default EXAMPLE_MIN_CPU_FREQ_48M if IDF_TARGET_ESP32C5 default EXAMPLE_MIN_CPU_FREQ_10M depends on PM_ENABLE help diff --git a/examples/wifi/power_save/pytest_wifi_power_save.py b/examples/wifi/power_save/pytest_wifi_power_save.py index c5eb2bfb22..86bab3979e 100644 --- a/examples/wifi/power_save/pytest_wifi_power_save.py +++ b/examples/wifi/power_save/pytest_wifi_power_save.py @@ -46,6 +46,7 @@ def _run_test(dut: Dut) -> None: @pytest.mark.esp32c3 @pytest.mark.esp32s3 @pytest.mark.esp32c6 +@pytest.mark.esp32c5 @pytest.mark.wifi_ap def test_wifi_power_save(dut: Dut) -> None: _run_test(dut)