diff --git a/components/efuse/esp32c3/esp_efuse_utility.c b/components/efuse/esp32c3/esp_efuse_utility.c
index 2e2c8a35ba..2a4f591f97 100644
--- a/components/efuse/esp32c3/esp_efuse_utility.c
+++ b/components/efuse/esp32c3/esp_efuse_utility.c
@@ -12,6 +12,7 @@
 #include "soc/efuse_periph.h"
 #include "esp32c3/clk.h"
 #include "esp32c3/rom/efuse.h"
+#include "hal/efuse_hal.h"
 
 static const char *TAG = "efuse";
 
@@ -57,7 +58,7 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = {
 // Update Efuse timing configuration
 static esp_err_t esp_efuse_set_timing(void)
 {
-    REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, 0x190);
+    efuse_hal_set_timing(0);
     return ESP_OK;
 }
 
diff --git a/components/efuse/esp32s2/esp_efuse_utility.c b/components/efuse/esp32s2/esp_efuse_utility.c
index 1572e051df..f1aed85766 100644
--- a/components/efuse/esp32s2/esp_efuse_utility.c
+++ b/components/efuse/esp32s2/esp_efuse_utility.c
@@ -12,6 +12,7 @@
 #include "sdkconfig.h"
 #include <sys/param.h>
 #include "esp32s2/rom/efuse.h"
+#include "hal/efuse_hal.h"
 
 static const char *TAG = "efuse";
 
@@ -58,7 +59,8 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = {
 static esp_err_t esp_efuse_set_timing(void)
 {
     uint32_t clock_hz = esp_clk_apb_freq();
-    return ets_efuse_set_timing(clock_hz) ? ESP_FAIL : ESP_OK;
+    efuse_hal_set_timing(clock_hz);
+    return ESP_OK;
 }
 
 static bool efuse_hal_is_coding_error_in_block(unsigned block)
diff --git a/components/efuse/esp32s3/esp_efuse_utility.c b/components/efuse/esp32s3/esp_efuse_utility.c
index b2bc5b0580..42761fecb1 100644
--- a/components/efuse/esp32s3/esp_efuse_utility.c
+++ b/components/efuse/esp32s3/esp_efuse_utility.c
@@ -12,6 +12,7 @@
 #include "sdkconfig.h"
 #include <sys/param.h>
 #include "esp32s3/rom/efuse.h"
+#include "hal/efuse_hal.h"
 
 static const char *TAG = "efuse";
 
@@ -56,7 +57,7 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = {
 // Update Efuse timing configuration
 static esp_err_t esp_efuse_set_timing(void)
 {
-    REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, 0x190);
+    efuse_hal_set_timing(0);
     return ESP_OK;
 }
 
diff --git a/components/hal/esp32c3/efuse_hal.c b/components/hal/esp32c3/efuse_hal.c
index fd7cad2987..a281f16b77 100644
--- a/components/hal/esp32c3/efuse_hal.c
+++ b/components/hal/esp32c3/efuse_hal.c
@@ -21,3 +21,14 @@ IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
 {
     return efuse_ll_get_chip_wafer_version_minor();
 }
+
+/******************* eFuse control functions *************************/
+
+void efuse_hal_set_timing(uint32_t apb_freq_hz)
+{
+    (void) apb_freq_hz;
+    efuse_ll_set_dac_num(0xFF);
+    efuse_ll_set_dac_clk_div(0x28);
+    efuse_ll_set_pwr_on_num(0x3000);
+    efuse_ll_set_pwr_off_num(0x190);
+}
diff --git a/components/hal/esp32c3/include/hal/efuse_hal.h b/components/hal/esp32c3/include/hal/efuse_hal.h
new file mode 100644
index 0000000000..a3b151e197
--- /dev/null
+++ b/components/hal/esp32c3/include/hal/efuse_hal.h
@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/soc_caps.h"
+#include "hal/efuse_ll.h"
+#include_next "hal/efuse_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief set eFuse timings
+ *
+ * @param apb_freq_hz APB frequency in Hz
+ */
+void efuse_hal_set_timing(uint32_t apb_freq_hz);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c3/include/hal/efuse_ll.h b/components/hal/esp32c3/include/hal/efuse_ll.h
index 6274fe7e67..99e4c59c49 100644
--- a/components/hal/esp32c3/include/hal/efuse_ll.h
+++ b/components/hal/esp32c3/include/hal/efuse_ll.h
@@ -120,6 +120,21 @@ __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_cod
     EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
 }
 
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
+{
+    EFUSE.dac_conf.dac_num = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
+{
+    EFUSE.dac_conf.dac_clk_div = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
+{
+    EFUSE.wr_tim_conf1.pwr_on_num = val;
+}
+
 __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
 {
     EFUSE.wr_tim_conf2.pwr_off_num = value;
diff --git a/components/hal/esp32s2/efuse_hal.c b/components/hal/esp32s2/efuse_hal.c
index fd7cad2987..f5e9236bf9 100644
--- a/components/hal/esp32s2/efuse_hal.c
+++ b/components/hal/esp32s2/efuse_hal.c
@@ -21,3 +21,63 @@ IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
 {
     return efuse_ll_get_chip_wafer_version_minor();
 }
+
+/******************* eFuse control functions *************************/
+
+void efuse_hal_set_timing(uint32_t apb_freq_hz)
+{
+    uint32_t tsup_a;
+    uint32_t tpgm;
+    uint32_t thp_a;
+    uint32_t tpgm_inact;
+    uint32_t clk_div;
+    uint32_t power_on;
+    uint32_t power_off;
+    uint32_t tsur_a;
+    uint32_t trd;
+    uint32_t thr_a;
+    if (apb_freq_hz == 80000000) {
+        tsup_a = 0x2;
+        tpgm = 0x320;
+        thp_a = 0x2;
+        tpgm_inact = 0x4;
+        clk_div = 0xA0;
+        power_on = 0xA200;
+	    power_off = 0x100;
+        tsur_a = 0x2;
+        trd = 0x4;
+        thr_a = 0x2;
+    } else if (apb_freq_hz == 40000000) {
+        tsup_a = 0x1;
+        tpgm = 0x190;
+        thp_a = 0x1;
+        tpgm_inact = 0x2;
+        clk_div = 0x50;
+        power_on = 0x5100;
+        power_off = 0x80;
+        tsur_a = 0x1;
+        trd = 0x2;
+        thr_a = 0x1;
+    } else { // 20000000 or 5000000 or 10000000
+        tsup_a = 0x1;
+        tpgm = 0xC8;
+        thp_a = 0x1;
+        tpgm_inact = 0x1;
+        clk_div = 0x28;
+        power_on = 0x2880;
+        power_off = 0x40;
+        tsur_a = 0x1;
+        trd = 0x1;
+        thr_a = 0x1;
+    }
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_TSUP_A, tsup_a);
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM, tpgm);
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_THP_A, thp_a);
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM_INACTIVE, tpgm_inact);
+    REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, clk_div);
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_PWR_ON_NUM, power_on);
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, power_off);
+    REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TSUR_A, tsur_a);
+    REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TRD, trd);
+    REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_THR_A, thr_a);
+}
diff --git a/components/hal/esp32s2/include/hal/efuse_hal.h b/components/hal/esp32s2/include/hal/efuse_hal.h
new file mode 100644
index 0000000000..a3b151e197
--- /dev/null
+++ b/components/hal/esp32s2/include/hal/efuse_hal.h
@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/soc_caps.h"
+#include "hal/efuse_ll.h"
+#include_next "hal/efuse_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief set eFuse timings
+ *
+ * @param apb_freq_hz APB frequency in Hz
+ */
+void efuse_hal_set_timing(uint32_t apb_freq_hz);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32s3/efuse_hal.c b/components/hal/esp32s3/efuse_hal.c
index ace30d55f6..4b950525b3 100644
--- a/components/hal/esp32s3/efuse_hal.c
+++ b/components/hal/esp32s3/efuse_hal.c
@@ -43,3 +43,14 @@ IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
     }
     return minor_raw;
 }
+
+/******************* eFuse control functions *************************/
+
+void efuse_hal_set_timing(uint32_t apb_freq_hz)
+{
+    (void) apb_freq_hz;
+    efuse_ll_set_dac_num(0xFF);
+    efuse_ll_set_dac_clk_div(0x28);
+    efuse_ll_set_pwr_on_num(0x3000);
+    efuse_ll_set_pwr_off_num(0x190);
+}
diff --git a/components/hal/esp32s3/include/hal/efuse_hal.h b/components/hal/esp32s3/include/hal/efuse_hal.h
new file mode 100644
index 0000000000..a3b151e197
--- /dev/null
+++ b/components/hal/esp32s3/include/hal/efuse_hal.h
@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/soc_caps.h"
+#include "hal/efuse_ll.h"
+#include_next "hal/efuse_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief set eFuse timings
+ *
+ * @param apb_freq_hz APB frequency in Hz
+ */
+void efuse_hal_set_timing(uint32_t apb_freq_hz);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32s3/include/hal/efuse_ll.h b/components/hal/esp32s3/include/hal/efuse_ll.h
index 07e17f9c3f..1e408e453c 100644
--- a/components/hal/esp32s3/include/hal/efuse_ll.h
+++ b/components/hal/esp32s3/include/hal/efuse_ll.h
@@ -120,6 +120,21 @@ __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_cod
     EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
 }
 
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
+{
+    EFUSE.dac_conf.dac_num = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
+{
+    EFUSE.dac_conf.dac_clk_div = val;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
+{
+    EFUSE.wr_tim_conf1.pwr_on_num = val;
+}
+
 __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
 {
     EFUSE.wr_tim_conf2.pwr_off_num = value;