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refactor(intr): unify riscv freertos set/clear intr mask from isr apis

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refactor(intr): find a potential bug that clic intr mask need extra nop ops
This commit is contained in:
Xiaoyu Liu 2024-09-03 15:22:58 +08:00
parent 8a608da2b0
commit 3d403a4ba8
1 changed files with 6 additions and 24 deletions
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30
components/freertos/FreeRTOS-Kernel/portable/riscv/port.c
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@ -476,38 +476,20 @@ BaseType_t IRAM_ATTR xPortInterruptedFromISRContext(void)
UBaseType_t xPortSetInterruptMaskFromISR(void)
{
UBaseType_t prev_int_level = 0;
UBaseType_t prev_int_level = 0, int_level = 0;
#if !SOC_INT_CLIC_SUPPORTED
unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
prev_int_level = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, RVHAL_EXCM_LEVEL);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
int_level = RVHAL_EXCM_LEVEL;
#else
/* When CLIC is supported, all interrupt priority levels less than or equal to the threshold level are masked. */
prev_int_level = rv_utils_set_intlevel_regval(RVHAL_EXCM_LEVEL_CLIC);
#endif /* !SOC_INIT_CLIC_SUPPORTED */
/**
* In theory, this function should not return immediately as there is a
* delay between the moment we mask the interrupt threshold register and
* the moment a potential lower-priority interrupt is triggered (as said
* above), it should have a delay of 2 machine cycles/instructions.
*
* However, in practice, this function has an epilogue of one instruction,
* thus the instruction masking the interrupt threshold register is
* followed by two instructions: `ret` and `csrrs` (RV_SET_CSR).
* That's why we don't need any additional nop instructions here.
*/
int_level = RVHAL_EXCM_LEVEL_CLIC;
#endif
prev_int_level = rv_utils_set_intlevel_regval(int_level);
return prev_int_level;
}
void vPortClearInterruptMaskFromISR(UBaseType_t prev_int_level)
{
#if !SOC_INT_CLIC_SUPPORTED
REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, prev_int_level);
#else
rv_utils_restore_intlevel_regval(prev_int_level);
#endif /* SOC_INIT_CLIC_SUPPORTED */
/**
* The delay between the moment we unmask the interrupt threshold register
* and the moment the potential requested interrupt is triggered is not