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https://github.com/espressif/esp-idf.git
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adc: support adc2 working with WiFi
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@ -593,6 +593,12 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
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//avoid collision with other tasks
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adc2_init(); // in critical section with whole rtc module. because the PWDET use the same registers, place it here.
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SARADC2_ENTER();
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#if SOC_ADC_ARBITER_SUPPORTED
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adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
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adc_hal_arbiter_config(&config);
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#endif
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#ifdef CONFIG_ADC_DISABLE_DAC
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adc2_dac_disable(channel); //disable other peripherals
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#endif
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@ -538,6 +538,9 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
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SAR_ADC2_LOCK_ACQUIRE();
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adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
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adc_hal_arbiter_config(&config);
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adc_atten_t atten = s_atten2_single[channel];
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uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, channel, atten);
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adc_hal_set_calibration_param(ADC_NUM_2, cal_val);
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@ -44,6 +44,14 @@ void adc_hal_init(void)
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adc_ll_digi_set_clk_div(SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT);
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}
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#if SOC_ADC_ARBITER_SUPPORTED
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void adc_hal_arbiter_config(adc_arbiter_t *config)
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{
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adc_ll_set_arbiter_work_mode(config->mode);
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adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
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}
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#endif
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/*---------------------------------------------------------------
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ADC calibration setting
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---------------------------------------------------------------*/
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@ -339,6 +347,7 @@ static void adc_hal_onetime_start(void)
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adc_ll_onetime_start(false);
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esp_rom_delay_us(delay);
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adc_ll_onetime_start(true);
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//No need to delay here. Becuase if the start signal is not seen, there won't be a done intr.
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}
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@ -142,24 +142,3 @@ void adc_hal_digi_monitor_enable(adc_digi_monitor_idx_t mon_idx, bool enable)
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s_monitor_enabled[mon_idx] = enable;
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update_monitor(mon_idx);
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}
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/*---------------------------------------------------------------
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Common setting
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---------------------------------------------------------------*/
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/**
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* Config ADC2 module arbiter.
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* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
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* the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
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*
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* @note Only ADC2 support arbiter.
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* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
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* @note Default priority: Wi-Fi > RTC > Digital;
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*
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* @param config Refer to `adc_arbiter_t`.
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*/
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void adc_hal_arbiter_config(adc_arbiter_t *config)
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{
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adc_ll_set_arbiter_work_mode(config->mode);
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adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
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}
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@ -97,23 +97,6 @@ void adc_hal_digi_monitor_config(adc_digi_monitor_idx_t mon_idx, adc_digi_monito
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*/
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void adc_hal_digi_monitor_enable(adc_digi_monitor_idx_t mon_idx, bool enable);
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/*---------------------------------------------------------------
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Common setting
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---------------------------------------------------------------*/
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/**
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* Config ADC2 module arbiter.
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* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
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* the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
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*
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* @note Only ADC2 support arbiter.
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* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
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* @note Default priority: Wi-Fi > RTC > Digital;
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*
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* @param config Refer to `adc_arbiter_t`.
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*/
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void adc_hal_arbiter_config(adc_arbiter_t *config);
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#ifdef __cplusplus
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}
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#endif
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@ -122,24 +122,3 @@ void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
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adc_ll_digi_monitor_set_mode(adc_n, config->mode);
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adc_ll_digi_monitor_set_thres(adc_n, config->threshold);
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}
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/*---------------------------------------------------------------
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Common setting
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---------------------------------------------------------------*/
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/**
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* Config ADC2 module arbiter.
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* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
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* the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
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*
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* @note Only ADC2 support arbiter.
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* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
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* @note Default priority: Wi-Fi > RTC > Digital;
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*
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* @param config Refer to ``adc_arbiter_t``.
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*/
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void adc_hal_arbiter_config(adc_arbiter_t *config)
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{
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adc_ll_set_arbiter_work_mode(config->mode);
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adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
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}
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@ -197,23 +197,6 @@ void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
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*/
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#define adc_hal_rtc_reset() adc_ll_rtc_reset()
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/*---------------------------------------------------------------
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Common setting
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---------------------------------------------------------------*/
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/**
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* Config ADC2 module arbiter.
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* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
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* the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
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*
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* @note Only ADC2 support arbiter.
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* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
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* @note Default priority: Wi-Fi > RTC > Digital;
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*
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* @param config Refer to ``adc_arbiter_t``.
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*/
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void adc_hal_arbiter_config(adc_arbiter_t *config);
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#ifdef __cplusplus
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}
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#endif
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@ -114,6 +114,22 @@ void adc_hal_init(void);
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#define adc_hal_amp_disable() adc_ll_amp_disable()
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#endif
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#if SOC_ADC_ARBITER_SUPPORTED
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//No ADC2 controller arbiter on ESP32
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/**
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* Config ADC2 module arbiter.
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* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
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* the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
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*
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* @note Only ADC2 support arbiter.
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* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
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* @note Default priority: Wi-Fi > RTC > Digital;
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*
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* @param config Refer to ``adc_arbiter_t``.
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*/
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void adc_hal_arbiter_config(adc_arbiter_t *config);
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#endif //#if SOC_ADC_ARBITER_SUPPORTED
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/*---------------------------------------------------------------
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PWDET(Power detect) controller setting
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---------------------------------------------------------------*/
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@ -44,6 +44,7 @@
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//F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095
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#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
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#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
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#define SOC_ADC_ARBITER_SUPPORTED 1
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/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
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#define SOC_APB_BACKUP_DMA (1)
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@ -77,6 +77,7 @@
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*/
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#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
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#define SOC_ADC_SUPPORT_RTC_CTRL 1
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#define SOC_ADC_ARBITER_SUPPORTED 1
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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#define SOC_BROWNOUT_RESET_SUPPORTED 1
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@ -34,6 +34,7 @@
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#define SOC_ADC_MAX_CHANNEL_NUM (10)
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#define SOC_ADC_MAX_BITWIDTH (12)
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#define SOC_ADC_SUPPORT_RTC_CTRL (1)
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#define SOC_ADC_ARBITER_SUPPORTED (1)
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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