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esp_system: Ensure TIMG0 clock is always enabled during normal operation
If the TimerGroup 0 clock is disabled and then reenabled, the watchdog registers (Flashboot protection included) will be re-enabled, and some seconds later, will trigger an unintended reset. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
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@ -388,10 +388,7 @@ static void gptimer_release_group_handle(gptimer_group_t *group)
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assert(s_platform.groups[group_id]);
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assert(s_platform.groups[group_id]);
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do_deinitialize = true;
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do_deinitialize = true;
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s_platform.groups[group_id] = NULL;
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s_platform.groups[group_id] = NULL;
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// Theoretically we need to disable the peripheral clock for the timer group
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periph_module_disable(timer_group_periph_signals.groups[group_id].module);
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// However, next time when we enable the peripheral again, the registers will be reset to default value, including the watchdog registers inside the group
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// Then the watchdog will go into reset state, e.g. the flash boot watchdog is enabled again and reset the system very soon
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// periph_module_disable(timer_group_periph_signals.groups[group_id].module);
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}
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}
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_lock_release(&s_platform.mutex);
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_lock_release(&s_platform.mutex);
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@ -300,6 +300,15 @@ __attribute__((weak)) void esp_perip_clk_init(void)
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/* Enable RNG clock. */
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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periph_module_enable(PERIPH_RNG_MODULE);
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/* Enable TimerGroup 0 clock to ensure its reference counter will never
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* be decremented to 0 during normal operation and preventing it from
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* being disabled.
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* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
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* registers (Flashboot protection included) will be reenabled, and some
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* seconds later, will trigger an unintended reset.
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*/
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periph_module_enable(PERIPH_TIMG0_MODULE);
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}
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}
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void rtc_clk_select_rtc_slow_clk(void)
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void rtc_clk_select_rtc_slow_clk(void)
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@ -251,4 +251,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
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/* Enable RNG clock. */
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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periph_module_enable(PERIPH_RNG_MODULE);
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/* Enable TimerGroup 0 clock to ensure its reference counter will never
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* be decremented to 0 during normal operation and preventing it from
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* being disabled.
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* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
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* registers (Flashboot protection included) will be reenabled, and some
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* seconds later, will trigger an unintended reset.
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*/
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periph_module_enable(PERIPH_TIMG0_MODULE);
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}
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}
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@ -295,4 +295,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
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/* Enable RNG clock. */
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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periph_module_enable(PERIPH_RNG_MODULE);
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/* Enable TimerGroup 0 clock to ensure its reference counter will never
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* be decremented to 0 during normal operation and preventing it from
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* being disabled.
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* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
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* registers (Flashboot protection included) will be reenabled, and some
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* seconds later, will trigger an unintended reset.
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*/
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periph_module_enable(PERIPH_TIMG0_MODULE);
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}
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}
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@ -290,4 +290,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
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/* Enable RNG clock. */
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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periph_module_enable(PERIPH_RNG_MODULE);
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#endif
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#endif
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/* Enable TimerGroup 0 clock to ensure its reference counter will never
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* be decremented to 0 during normal operation and preventing it from
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* being disabled.
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* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
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* registers (Flashboot protection included) will be reenabled, and some
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* seconds later, will trigger an unintended reset.
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*/
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periph_module_enable(PERIPH_TIMG0_MODULE);
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}
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}
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@ -277,6 +277,14 @@ __attribute__((weak)) void esp_perip_clk_init(void)
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/* Enable RNG clock. */
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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periph_module_enable(PERIPH_RNG_MODULE);
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#endif
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#endif
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/* Enable TimerGroup 0 clock to ensure its reference counter will never
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* be decremented to 0 during normal operation and preventing it from
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* being disabled.
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* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
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* registers (Flashboot protection included) will be reenabled, and some
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* seconds later, will trigger an unintended reset.
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*/
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periph_module_enable(PERIPH_TIMG0_MODULE);
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}
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}
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@ -274,4 +274,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
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/* Enable RNG clock. */
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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periph_module_enable(PERIPH_RNG_MODULE);
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/* Enable TimerGroup 0 clock to ensure its reference counter will never
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* be decremented to 0 during normal operation and preventing it from
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* being disabled.
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* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
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* registers (Flashboot protection included) will be reenabled, and some
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* seconds later, will trigger an unintended reset.
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*/
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periph_module_enable(PERIPH_TIMG0_MODULE);
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}
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}
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@ -312,4 +312,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
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/* Enable RNG clock. */
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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periph_module_enable(PERIPH_RNG_MODULE);
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/* Enable TimerGroup 0 clock to ensure its reference counter will never
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* be decremented to 0 during normal operation and preventing it from
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* being disabled.
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* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
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* registers (Flashboot protection included) will be reenabled, and some
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* seconds later, will trigger an unintended reset.
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*/
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periph_module_enable(PERIPH_TIMG0_MODULE);
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}
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}
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@ -314,4 +314,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
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/* Enable RNG clock. */
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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periph_module_enable(PERIPH_RNG_MODULE);
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/* Enable TimerGroup 0 clock to ensure its reference counter will never
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* be decremented to 0 during normal operation and preventing it from
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* being disabled.
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* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
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* registers (Flashboot protection included) will be reenabled, and some
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* seconds later, will trigger an unintended reset.
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*/
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periph_module_enable(PERIPH_TIMG0_MODULE);
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}
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}
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