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soc/rtc: don’t switch frequency in rtc_sleep_init
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3c78faa0a9
@ -427,7 +427,6 @@ void rtc_clk_wait_for_slow_cycle();
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* @brief sleep configuration for rtc_sleep_init function
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* @brief sleep configuration for rtc_sleep_init function
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*/
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*/
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typedef struct {
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typedef struct {
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uint32_t soc_clk_sel : 2; //!< SoC clock select, see RTC_CNTL_SOC_CLK_SEL
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uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
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uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
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uint32_t rtc_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (RTC memory)
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uint32_t rtc_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (RTC memory)
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uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
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uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
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@ -455,7 +454,6 @@ typedef struct {
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* @param RTC_SLEEP_PD_x flags combined using bitwise OR
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* @param RTC_SLEEP_PD_x flags combined using bitwise OR
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*/
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*/
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#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
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#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
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.soc_clk_sel = RTC_CNTL_SOC_CLK_SEL_XTL, \
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.lslp_mem_inf_fpu = 0, \
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.lslp_mem_inf_fpu = 0, \
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.rtc_mem_inf_fpu = 0, \
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.rtc_mem_inf_fpu = 0, \
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.rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
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.rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
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@ -48,7 +48,6 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par
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}
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}
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rtc_sleep_config_t cfg = { 0 };
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rtc_sleep_config_t cfg = { 0 };
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cfg.soc_clk_sel = RTC_CNTL_SOC_CLK_SEL_XTL;
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switch (sleep_mode) {
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switch (sleep_mode) {
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case PM_LIGHT_SLEEP:
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case PM_LIGHT_SLEEP:
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@ -89,9 +89,6 @@ static void rtc_sleep_pd(rtc_sleep_pd_config_t cfg)
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void rtc_sleep_init(rtc_sleep_config_t cfg)
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void rtc_sleep_init(rtc_sleep_config_t cfg)
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{
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{
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rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, cfg.soc_clk_sel);
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//set 5 PWC state machine times to fit in main state machine time
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//set 5 PWC state machine times to fit in main state machine time
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, 1);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, 1);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, RTC_CNTL_XTL_BUF_WAIT_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, RTC_CNTL_XTL_BUF_WAIT_DEFAULT);
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@ -112,16 +109,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, RTC_MEM_POWERUP_DELAY);
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, RTC_MEM_POWERUP_DELAY);
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, RTC_MEM_WAIT_DELAY);
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, RTC_MEM_WAIT_DELAY);
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if (cfg.soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) {
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_DEFAULT);
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} else if (cfg.soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_XTL) {
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ets_update_cpu_frequency(xtal_freq);
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rtc_clk_apb_freq_update(xtal_freq * MHZ);
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} else if (cfg.soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_8M) {
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ets_update_cpu_frequency(8);
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rtc_clk_apb_freq_update(8 * MHZ);
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}
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if (cfg.lslp_mem_inf_fpu) {
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if (cfg.lslp_mem_inf_fpu) {
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
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} else {
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} else {
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