diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index 2af91fd135..6ff5a77d73 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -275,10 +275,15 @@ static inline void bootloader_hardware_init(void) static inline void bootloader_glitch_reset_disable(void) { + /* + For origin chip & ECO1: only support swt reset; + For ECO2: fix brownout reset bug, support swt & brownout reset; + For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset. + */ uint8_t chip_version = bootloader_common_get_chip_revision(); if (chip_version < 2) { REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST); - } else { + } else if (chip_version == 2) { REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST); } } diff --git a/components/efuse/esp32c3/esp_efuse_table.c b/components/efuse/esp32c3/esp_efuse_table.c index 40dfd08f23..2983e3031e 100644 --- a/components/efuse/esp32c3/esp_efuse_table.c +++ b/components/efuse/esp32c3/esp_efuse_table.c @@ -17,7 +17,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table f9a84eb22f94a7bc083b4c6817a33a59 +// md5_digest_table 61baa79d296df996c838bc2adc1837e5 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -484,6 +484,30 @@ static const esp_efuse_desc_t SYS_DATA_PART2[] = { {EFUSE_BLK10, 0, 256}, // System configuration, }; +static const esp_efuse_desc_t K_RTC_LDO[] = { + {EFUSE_BLK1, 135, 7}, // BLOCK1 K_RTC_LDO, +}; + +static const esp_efuse_desc_t K_DIG_LDO[] = { + {EFUSE_BLK1, 142, 7}, // BLOCK1 K_DIG_LDO, +}; + +static const esp_efuse_desc_t V_RTC_DBIAS20[] = { + {EFUSE_BLK1, 149, 8}, // BLOCK1 voltage of rtc dbias20, +}; + +static const esp_efuse_desc_t V_DIG_DBIAS20[] = { + {EFUSE_BLK1, 157, 8}, // BLOCK1 voltage of digital dbias20, +}; + +static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { + {EFUSE_BLK1, 165, 5}, // BLOCK1 digital dbias when hvt, +}; + +static const esp_efuse_desc_t THRES_HVT[] = { + {EFUSE_BLK1, 170, 10}, // BLOCK1 pvt threshold when hvt, +}; + @@ -1062,3 +1086,33 @@ const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { &SYS_DATA_PART2[0], // System configuration NULL }; + +const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = { + &K_RTC_LDO[0], // BLOCK1 K_RTC_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = { + &K_DIG_LDO[0], // BLOCK1 K_DIG_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = { + &V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = { + &V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = { + &DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[] = { + &THRES_HVT[0], // BLOCK1 pvt threshold when hvt + NULL +}; diff --git a/components/efuse/esp32c3/esp_efuse_table.csv b/components/efuse/esp32c3/esp_efuse_table.csv index 3d13f5c43c..2e322fb0d1 100644 --- a/components/efuse/esp32c3/esp_efuse_table.csv +++ b/components/efuse/esp32c3/esp_efuse_table.csv @@ -153,3 +153,12 @@ KEY3, EFUSE_BLK7, 0, 256, Key3 or us KEY4, EFUSE_BLK8, 0, 256, Key4 or user data KEY5, EFUSE_BLK9, 0, 256, Key5 or user data SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration + +# AUTO CONFIG DIG&RTC DBIAS# +################ +K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO +K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO +V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, BLOCK1 voltage of rtc dbias20 +V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20 +DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, BLOCK1 digital dbias when hvt +THRES_HVT, EFUSE_BLK1, 170, 10, BLOCK1 pvt threshold when hvt diff --git a/components/efuse/esp32c3/include/esp_efuse_table.h b/components/efuse/esp32c3/include/esp_efuse_table.h index 13f3f1839f..a6d4ca27f0 100644 --- a/components/efuse/esp32c3/include/esp_efuse_table.h +++ b/components/efuse/esp32c3/include/esp_efuse_table.h @@ -17,7 +17,7 @@ extern "C" { #endif -// md5_digest_table f9a84eb22f94a7bc083b4c6817a33a59 +// md5_digest_table 61baa79d296df996c838bc2adc1837e5 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -138,6 +138,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[]; #ifdef __cplusplus } diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk.c b/components/esp_hw_support/port/esp32c3/rtc_clk.c index 56ae2047fd..f47848a523 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk.c @@ -121,18 +121,6 @@ bool rtc_clk_8md256_enabled(void) return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; } -static void wait_dig_dbias_valid(uint64_t rtc_cycles) -{ - rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); - rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == RTC_SLOW_FREQ_32K_XTAL) { - cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_freq == RTC_SLOW_FREQ_8MD256) { - cal_clk = RTC_CAL_8MD256; - } - rtc_clk_cal(cal_clk, rtc_cycles); -} - void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) { REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq); @@ -292,24 +280,15 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq) */ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) { - int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); - int origin_cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL); - int dbias = DIG_DBIAS_80M; int per_conf = DPORT_CPUPERIOD_SEL_80; if (cpu_freq_mhz == 80) { /* nothing to do */ } else if (cpu_freq_mhz == 160) { - dbias = DIG_DBIAS_160M; per_conf = DPORT_CPUPERIOD_SEL_160; } else { SOC_LOGE(TAG, "invalid frequency"); abort(); } - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias); - if ((origin_soc_clk == DPORT_SOC_CLK_SEL_XTAL) || (origin_soc_clk == DPORT_SOC_CLK_SEL_8M) - || (((origin_soc_clk == DPORT_SOC_CLK_SEL_PLL) && (0 == origin_cpuperiod_sel)))) { - wait_dig_dbias_valid(2); - } REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf); REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL); @@ -457,18 +436,7 @@ void rtc_clk_cpu_freq_set_xtal(void) */ void rtc_clk_cpu_freq_to_xtal(int freq, int div) { - int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); - int origin_div_cnt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT); ets_update_cpu_frequency(freq); - /* lower the voltage */ - if (freq <= 2) { - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_2M); - } else { - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL); - } - if ((DPORT_SOC_CLK_SEL_XTAL == origin_soc_clk) && (origin_div_cnt > 0)) { - wait_dig_dbias_valid(2); - } /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */ REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1); @@ -480,13 +448,7 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div) static void rtc_clk_cpu_freq_to_8m(void) { - int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); - int origin_div_cnt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT); ets_update_cpu_frequency(8); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL); - if ((DPORT_SOC_CLK_SEL_XTAL == origin_soc_clk) && (origin_div_cnt > 4)) { - wait_dig_dbias_valid(2); - } REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M); rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M); diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c index 19adae8dca..7a33720bea 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_init.c @@ -31,6 +31,7 @@ static const char *TAG = "rtc_init"; static void set_ocode_by_efuse(int calib_version); static void calibrate_ocode(void); +static void set_rtc_dig_dbias(void); void rtc_init(rtc_config_t cfg) { @@ -55,9 +56,21 @@ void rtc_init(rtc_config_t cfg) REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles); REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles); - /* Reset RTC bias to default value (needed if waking up from deep sleep) */ - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, RTC_CNTL_DBIAS_1V10); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, RTC_CNTL_DBIAS_1V10); + if (cfg.cali_ocode) { + uint32_t rtc_calib_version = 0; + esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3); + if (err != ESP_OK) { + rtc_calib_version = 0; + SOC_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version); + } + if (rtc_calib_version == 1) { + set_ocode_by_efuse(rtc_calib_version); + } else { + calibrate_ocode(); + } + } + + set_rtc_dig_dbias(); if (cfg.clkctl_init) { //clear CMMU clock force on @@ -138,16 +151,6 @@ void rtc_init(rtc_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); } - if (cfg.cali_ocode) { - uint32_t rtc_calib_version = 0; - esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3); - if (rtc_calib_version == 1) { - set_ocode_by_efuse(rtc_calib_version); - } else { - calibrate_ocode(); - } - } - REG_WRITE(RTC_CNTL_INT_ENA_REG, 0); REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); } @@ -195,7 +198,9 @@ static void set_ocode_by_efuse(int calib_version) assert(calib_version == 1); // use efuse ocode. uint32_t ocode; - ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8)); + esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8); + assert(err == ESP_OK); + (void) err; REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); } @@ -250,3 +255,85 @@ static void calibrate_ocode(void) } rtc_clk_cpu_freq_set_config(&old_config); } + +static uint32_t get_dig_dbias_by_efuse(uint8_t chip_version) +{ + assert(chip_version >= 3); + uint32_t dig_dbias = 28; + esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, 5); + if (err != ESP_OK) { + dig_dbias = 28; + SOC_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias); + } + return dig_dbias; +} + +uint32_t get_rtc_dbias_by_efuse(uint8_t chip_version, uint32_t dig_dbias) +{ + assert(chip_version >= 3); + uint32_t rtc_dbias = 0; + signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0; + esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, 7); + esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, 7); + esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, 8); + esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, 8); + if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) { + k_rtc_ldo = 0; + k_dig_ldo = 0; + v_rtc_bias20 = 0; + v_dig_bias20 = 0; + SOC_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20); + } + + k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): k_rtc_ldo; + k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo; + v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20; + v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20; + + uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500; + uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500; + signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo; + signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo; + uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20); + uint32_t v_rtc_nearest_1v15_mul10000 = 0; + for (rtc_dbias = 15; rtc_dbias < 32; rtc_dbias++) { + v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20); + if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250) + break; + } + return rtc_dbias; +} + +static void set_rtc_dig_dbias() +{ + /* + 1. a reasonable dig_dbias which by scaning pvt to make 160 CPU run successful stored in efuse; + 2. also we store some value in efuse, include: + k_rtc_ldo (slope of rtc voltage & rtc_dbias); + k_dig_ldo (slope of digital voltage & digital_dbias); + v_rtc_bias20 (rtc voltage when rtc dbais is 20); + v_dig_bias20 (digital voltage when digital dbais is 20). + 3. a reasonable rtc_dbias can be calculated by a certion formula. + */ + uint32_t rtc_dbias = 28, dig_dbias = 28; + uint8_t chip_version = esp_efuse_get_chip_ver(); + if (chip_version >= 3) { + dig_dbias = get_dig_dbias_by_efuse(chip_version); + if (dig_dbias != 0) { + if (dig_dbias + 4 > 28) { + dig_dbias = 28; + } else { + dig_dbias += 4; + } + rtc_dbias = get_rtc_dbias_by_efuse(chip_version, dig_dbias); // already burn dig_dbias in efuse + } else { + dig_dbias = 28; + SOC_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in chip version: 0%d\n", chip_version); + } + } + else { + SOC_LOGD(TAG, "chip_version is less than 3, not burn core voltage in efuse\n"); + } + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, rtc_dbias); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dig_dbias); +} diff --git a/components/esp_hw_support/port/esp32c3/rtc_sleep.c b/components/esp_hw_support/port/esp32c3/rtc_sleep.c index 241b1271a5..1cdc56f2d3 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c3/rtc_sleep.c @@ -121,9 +121,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, cfg.rtc_dbias_wak); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, cfg.dig_dbias_wak); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h index f6377477af..3fda6cb8a7 100644 --- a/components/soc/esp32c3/include/soc/rtc.h +++ b/components/soc/esp32c3/include/soc/rtc.h @@ -122,6 +122,15 @@ set sleep_init default param #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 +/* +The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value +storing in efuse (based on ATE 5k ECO3 chips) +*/ +#define K_RTC_MID_MUL10000 215 +#define K_DIG_MID_MUL10000 213 +#define V_RTC_MID_MUL10000 10800 +#define V_DIG_MID_MUL10000 10860 + /** * @brief Possible main XTAL frequency values. *