From 3b7da7eae52fbb85569f5261926ce73476e2ce4b Mon Sep 17 00:00:00 2001
From: morris <maoshengrong@espressif.com>
Date: Tue, 11 Jul 2023 16:32:54 +0800
Subject: [PATCH] feat(gdma): gdma descriptor alignment

---
 .../hal/esp32p4/include/hal/axi_dma_ll.h      |  2 --
 components/hal/include/hal/dma_types.h        | 34 ++++++++++++++-----
 2 files changed, 26 insertions(+), 10 deletions(-)

diff --git a/components/hal/esp32p4/include/hal/axi_dma_ll.h b/components/hal/esp32p4/include/hal/axi_dma_ll.h
index 2219725c0d..f044cc6707 100644
--- a/components/hal/esp32p4/include/hal/axi_dma_ll.h
+++ b/components/hal/esp32p4/include/hal/axi_dma_ll.h
@@ -108,7 +108,6 @@ static inline void axi_dma_ll_rx_enable_owner_check(axi_dma_dev_t *dev, uint32_t
  */
 static inline void axi_dma_ll_rx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
 {
-    // TODO: IDF-6504
 }
 
 /**
@@ -305,7 +304,6 @@ static inline void axi_dma_ll_tx_enable_owner_check(axi_dma_dev_t *dev, uint32_t
  */
 static inline void axi_dma_ll_tx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
 {
-    // TODO: IDF-6504
 }
 
 /**
diff --git a/components/hal/include/hal/dma_types.h b/components/hal/include/hal/dma_types.h
index dead785c2c..a0cae11ea3 100644
--- a/components/hal/include/hal/dma_types.h
+++ b/components/hal/include/hal/dma_types.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,10 +14,10 @@ extern "C" {
 #endif
 
 /**
- * @brief Type of DMA descriptor
- *
+ * @brief Type of DMA descriptor the aligned to 4 bytes
  */
-typedef struct dma_descriptor_s {
+typedef struct dma_descriptor_s dma_descriptor_t;
+struct dma_descriptor_s {
     struct {
         uint32_t size : 12;         /*!< Buffer size */
         uint32_t length : 12;       /*!< Number of valid bytes in the buffer */
@@ -28,17 +28,35 @@ typedef struct dma_descriptor_s {
         uint32_t owner : 1;         /*!< Who is allowed to access the buffer that this descriptor points to */
     } dw0;                          /*!< Descriptor Word 0 */
     void *buffer;                   /*!< Pointer to the buffer */
-    struct dma_descriptor_s *next;  /*!< Pointer to the next descriptor (set to NULL if the descriptor is the last one, e.g. suc_eof=1) */
-} dma_descriptor_t;
+    dma_descriptor_t *next;         /*!< Pointer to the next descriptor (set to NULL if the descriptor is the last one, e.g. suc_eof=1) */
+} __attribute__((aligned(4)));
+typedef dma_descriptor_t dma_descriptor_align4_t;
+ESP_STATIC_ASSERT(sizeof(dma_descriptor_align4_t) == 12, "dma_descriptor_align4_t should occupy 12 bytes in memory");
 
-ESP_STATIC_ASSERT(sizeof(dma_descriptor_t) == 12, "dma_descriptor_t should occupy 12 bytes in memory");
+/**
+ * @brief Type of DMA descriptor the aligned to 8 bytes
+ */
+typedef struct dma_descriptor_align8_s dma_descriptor_align8_t;
+struct dma_descriptor_align8_s {
+    struct {
+        uint32_t size : 12;         /*!< Buffer size */
+        uint32_t length : 12;       /*!< Number of valid bytes in the buffer */
+        uint32_t reversed24_27 : 4; /*!< Reserved */
+        uint32_t err_eof : 1;       /*!< Whether the received buffer contains error */
+        uint32_t reserved29 : 1;    /*!< Reserved */
+        uint32_t suc_eof : 1;       /*!< Whether the descriptor is the last one in the link */
+        uint32_t owner : 1;         /*!< Who is allowed to access the buffer that this descriptor points to */
+    } dw0;                          /*!< Descriptor Word 0 */
+    void *buffer;                   /*!< Pointer to the buffer */
+    dma_descriptor_align8_t *next;  /*!< Pointer to the next descriptor (set to NULL if the descriptor is the last one, e.g. suc_eof=1) */
+} __attribute__((aligned(8)));
+ESP_STATIC_ASSERT(sizeof(dma_descriptor_align8_t) == 16, "dma_descriptor_align8_t should occupy 16 bytes in memory");
 
 #define DMA_DESCRIPTOR_BUFFER_OWNER_CPU (0)   /*!< DMA buffer is allowed to be accessed by CPU */
 #define DMA_DESCRIPTOR_BUFFER_OWNER_DMA (1)   /*!< DMA buffer is allowed to be accessed by DMA engine */
 #define DMA_DESCRIPTOR_BUFFER_MAX_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */
 #define DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED  (4095-3)  /*!< Maximum size of the buffer that can be attached to descriptor, and aligned to 4B */
 
-
 #ifdef __cplusplus
 }
 #endif