refactor(regi2c): add LL function to control analog i2c master clock

components/bootloader_support/src/esp32c5/bootloader_esp32c5.c

@@ -41,8 +41,7 @@
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
-#include "modem/modem_syscon_reg.h"
 
 static const char *TAG = "boot.esp32c5";
 
@@ -85,10 +84,9 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    /* Enable analog i2c master clock */
+    regi2c_ctrl_ll_master_enable_clock(true);
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO); // TODO: IDF-8667 Remove this?
+    regi2c_ctrl_ll_master_configure_clock();
-    SET_PERI_REG_MASK(MODEM_SYSCON_CLK_CONF_REG, MODEM_SYSCON_CLK_I2C_MST_SEL_160M);
 }
 
 static inline void bootloader_ana_reset_config(void)

components/bootloader_support/src/esp32c6/bootloader_esp32c6.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -43,7 +43,7 @@
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 static const char *TAG = "boot.esp32c6";
 
@@ -95,9 +95,8 @@ static inline void bootloader_hardware_init(void)
     esp_rom_spiflash_fix_dummylen(1, 1);
 #endif
 
-    /* Enable analog i2c master clock */
+    regi2c_ctrl_ll_master_enable_clock(true);
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+    regi2c_ctrl_ll_master_configure_clock();
-    SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
 }
 
 static inline void bootloader_ana_reset_config(void)
@@ -167,7 +166,7 @@ esp_err_t bootloader_init(void)
     }
 #endif // !CONFIG_APP_BUILD_TYPE_RAM
 
-    // check whether a WDT reset happend
+    // check whether a WDT reset happened
     bootloader_check_wdt_reset();
     // config WDT
     bootloader_config_wdt();

components/bootloader_support/src/esp32c61/bootloader_esp32c61.c

@@ -43,8 +43,7 @@
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
-#include "modem/modem_syscon_reg.h"
 
 static const char *TAG = "boot.esp32c61";
 
@@ -96,10 +95,9 @@ static inline void bootloader_hardware_init(void)
     esp_rom_spiflash_fix_dummylen(1, 1);
 #endif
 
-    /* Enable analog i2c master clock */
+    regi2c_ctrl_ll_master_enable_clock(true);
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO); // TODO: IDF-9274 Remove this?
+    regi2c_ctrl_ll_master_configure_clock();
-    SET_PERI_REG_MASK(MODEM_SYSCON_CLK_CONF_REG, MODEM_SYSCON_CLK_I2C_MST_SEL_160M);
 }
 
 static inline void bootloader_ana_reset_config(void)

components/bootloader_support/src/esp32h2/bootloader_esp32h2.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -31,7 +31,6 @@
 #include "esp_private/regi2c_ctrl.h"
 #include "soc/regi2c_lp_bias.h"
 #include "soc/regi2c_bias.h"
-#include "modem/modem_lpcon_reg.h"
 #include "bootloader_console.h"
 #include "bootloader_flash_priv.h"
 #include "bootloader_soc.h"
@@ -43,7 +42,7 @@
 #include "soc/lp_wdt_reg.h"
 #include "soc/pmu_reg.h"
 #include "hal/efuse_hal.h"
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 static const char *TAG = "boot.esp32h2";
 
@@ -89,8 +88,9 @@ static inline void bootloader_hardware_init(void)
     /* Disable RF pll by default */
     CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
-    /* Enable analog i2c master clock */
+
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_configure_clock();
 }
 
 static inline void bootloader_ana_reset_config(void)
@@ -160,7 +160,7 @@ esp_err_t bootloader_init(void)
     }
 #endif // !CONFIG_APP_BUILD_TYPE_RAM
 
-    // check whether a WDT reset happend
+    // check whether a WDT reset happened
     bootloader_check_wdt_reset();
     // config WDT
     bootloader_config_wdt();

components/bootloader_support/src/esp32p4/bootloader_esp32p4.c

@@ -48,6 +48,7 @@
 #include "soc/regi2c_cpll.h"
 #include "soc/regi2c_bias.h"
 #include "esp_private/periph_ctrl.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 static const char *TAG = "boot.esp32p4";
 
@@ -92,8 +93,10 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
+    int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_RC_ATOMIC_ENV
-    // regi2c is enabled by default on ESP32P4, do nothing
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_configure_clock();
+
     unsigned chip_version = efuse_hal_chip_revision();
     if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
         // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader
@@ -106,6 +109,7 @@ static inline void bootloader_hardware_init(void)
     REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10);
 
     // IDF-10019 TODO: This is temporarily for ESP32P4-ECO0, please remove it when eco0 is not widly used.
+    int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
     if (likely(ESP_CHIP_REV_ABOVE(chip_version, 1))) {
         spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
         spimem_ctrlr_ll_set_core_clock(0, 6);

components/esp_hw_support/modem_clock.c

@@ -17,6 +17,7 @@
 #include "esp_sleep.h"
 #include "hal/efuse_hal.h"
 #include "hal/clk_tree_ll.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 // Please define the frequently called modules in the low bit,
 // which will improve the execution efficiency
@@ -117,7 +118,7 @@ static void IRAM_ATTR modem_clock_modem_private_fe_configure(modem_clock_context
 
 static void IRAM_ATTR modem_clock_i2c_master_configure(modem_clock_context_t *ctx, bool enable)
 {
-    modem_lpcon_ll_enable_i2c_master_clock(ctx->hal->lpcon_dev, enable);
+    regi2c_ctrl_ll_master_enable_clock(enable);
 }
 
 static void IRAM_ATTR modem_clock_etm_configure(modem_clock_context_t *ctx, bool enable)

components/esp_hw_support/port/esp32c5/rtc_clk.c

@@ -22,12 +22,8 @@
 #include "esp_private/sleep_event.h"
 
 #if SOC_MODEM_CLOCK_SUPPORTED
-#ifdef BOOTLOADER_BUILD
-#include "hal/modem_lpcon_ll.h"
-#else
 #include "esp_private/esp_modem_clock.h"
 #endif
-#endif
 
 static const char *TAG = "rtc_clk";
 
@@ -150,7 +146,7 @@ static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
 {
 #if SOC_MODEM_CLOCK_SUPPORTED
 #ifdef BOOTLOADER_BUILD
-    modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, enable);
+    regi2c_ctrl_ll_master_enable_clock(enable);
 #else
     if (enable) {
         modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);

components/esp_hw_support/port/esp32c6/rtc_clk.c

@@ -20,12 +20,7 @@
 #include "soc/io_mux_reg.h"
 #include "soc/lp_aon_reg.h"
 #include "esp_private/sleep_event.h"
-
-#ifdef BOOTLOADER_BUILD
-#include "hal/modem_lpcon_ll.h"
-#else
 #include "esp_private/esp_modem_clock.h"
-#endif
 
 static const char *TAG = "rtc_clk";
 
@@ -147,7 +142,7 @@ static void rtc_clk_bbpll_enable(void)
 static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
 {
 #ifdef BOOTLOADER_BUILD
-    modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, enable);
+    regi2c_ctrl_ll_master_enable_clock(enable);
 #else
     if (enable) {
         modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);

components/esp_hw_support/port/esp32c61/rtc_clk.c

@@ -22,12 +22,8 @@
 #include "esp_private/sleep_event.h"
 
 #if SOC_MODEM_CLOCK_SUPPORTED   //TODO: [ESP32C61] IDF-9513
-#ifdef BOOTLOADER_BUILD
-#include "hal/modem_lpcon_ll.h"
-#else
 #include "esp_private/esp_modem_clock.h"
 #endif
-#endif
 
 static const char *TAG = "rtc_clk";
 
@@ -151,7 +147,7 @@ static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
 // TODO: [ESP32C61] IDF-9513, modem support
 #if SOC_MODEM_CLOCK_SUPPORTED
 #ifdef BOOTLOADER_BUILD
-    modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, enable);
+    regi2c_ctrl_ll_master_enable_clock(enable);
 #else
     if (enable) {
         modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);

components/esp_hw_support/port/esp32h2/rtc_clk.c

@@ -20,12 +20,7 @@
 #include "soc/io_mux_reg.h"
 #include "soc/lp_aon_reg.h"
 #include "esp_private/sleep_event.h"
-
-#ifdef BOOTLOADER_BUILD
-#include "hal/modem_lpcon_ll.h"
-#else
 #include "esp_private/esp_modem_clock.h"
-#endif
 
 static const char *TAG = "rtc_clk";
 
@@ -163,7 +158,7 @@ static void rtc_clk_bbpll_enable(void)
 static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
 {
 #ifdef BOOTLOADER_BUILD
-    modem_lpcon_ll_enable_i2c_master_clock(&MODEM_LPCON, enable);
+    regi2c_ctrl_ll_master_enable_clock(enable);
 #else
     if (enable) {
         modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);

components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c

@@ -6,7 +6,7 @@
 #include "esp_rom_sys.h"
 #include "esp_attr.h"
 #include "soc/i2c_ana_mst_reg.h"
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 #define REGI2C_BIAS_MST_SEL    (BIT(8))
 #define REGI2C_BBPLL_MST_SEL   (BIT(9))
@@ -75,7 +75,7 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
 
-    REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+    regi2c_ctrl_ll_master_enable_clock(true);
 
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {

components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c

@@ -1,12 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include "esp_rom_sys.h"
 #include "esp_attr.h"
 #include "soc/i2c_ana_mst_reg.h"
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
 /**
  * BB    - 0x67 - BIT0
  * TXRF  - 0x6B - BIT1
@@ -86,8 +86,7 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
 
-    REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+    regi2c_ctrl_ll_master_enable_clock(true);
-    REG_SET_BIT(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
 
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {

components/esp_rom/patches/esp_rom_regi2c_esp32c61.c

@@ -7,7 +7,7 @@
 #include "esp_attr.h"
 #include "soc/i2c_ana_mst_reg.h"
 #include "soc/pmu_reg.h" // TODO: IDF-9249 Can be removed
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 #define REGI2C_BIAS_MST_SEL    (BIT(8))
 #define REGI2C_BBPLL_MST_SEL   (BIT(9))
@@ -76,7 +76,7 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
 
-    REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+    regi2c_ctrl_ll_master_enable_clock(true);
     REG_SET_BIT(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); // TODO: IDF-9249 Move to pmu_init()
     REG_SET_BIT(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); // TODO: IDF-9249 Move to pmu_init()
 

components/esp_rom/patches/esp_rom_regi2c_esp32h2.c

@@ -6,7 +6,7 @@
 #include "esp_rom_sys.h"
 #include "esp_attr.h"
 #include "soc/i2c_ana_mst_reg.h"
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 /**
  * BB    - 0x67 - BIT0
@@ -86,7 +86,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
-    REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+    regi2c_ctrl_ll_master_enable_clock(true);
 
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {

components/esp_rom/patches/esp_rom_regi2c_esp32p4.c

@@ -1,12 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include "esp_rom_sys.h"
 #include "esp_attr.h"
 #include "soc/i2c_ana_mst_reg.h"
-#include "soc/lpperi_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
 /**
  * DIG_REG      - 0x6D - BIT10
  * PLL_CPU      - 0x67 - BIT11
@@ -87,8 +87,8 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
-    REG_SET_BIT(LPPERI_CLK_EN_REG, LPPERI_CK_EN_LP_I2CMST);
+    int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // Right now this patch in rom can not depend on esp_hw_support, after IDF-10110 is done, this should be removed, should have spinlock protection
-    SET_PERI_REG_MASK(I2C_ANA_MST_CLK160M_REG, I2C_ANA_MST_CLK_I2C_MST_SEL_160M);
+    regi2c_ctrl_ll_master_enable_clock(true);
     REG_SET_FIELD(I2C_ANA_MST_ANA_CONF2_REG, I2C_ANA_MST_ANA_CONF2, 0);
     REG_SET_FIELD(I2C_ANA_MST_ANA_CONF1_REG, I2C_ANA_MST_ANA_CONF1, 0);
 

components/hal/esp32c5/include/hal/modem_lpcon_ll.h

@@ -133,12 +133,6 @@ static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_d
     return hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num;
 }
 
-__attribute__((always_inline))
-static inline void modem_lpcon_ll_enable_i2c_master_160m_clock(modem_lpcon_dev_t *hw, bool en)
-{
-    // ESP32C5 Not Support
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_set_modem_pwr_clk_src_fo(modem_lpcon_dev_t *hw, bool value)
 {
@@ -169,12 +163,6 @@ static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool
     hw->clk_conf.clk_coex_en = en;
 }
 
-__attribute__((always_inline))
-static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en)
-{
-    hw->clk_conf.clk_i2c_mst_en = en;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_enable_ble_rtc_timer_clock(modem_lpcon_dev_t *hw, bool en)
 {
@@ -193,12 +181,6 @@ static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw,
     hw->clk_conf_force_on.clk_coex_fo = en;
 }
 
-__attribute__((always_inline))
-static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en)
-{
-    hw->clk_conf_force_on.clk_i2c_mst_fo = en;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_enable_ble_rtc_timer_force_clock(modem_lpcon_dev_t *hw, bool en)
 {
@@ -267,13 +249,6 @@ static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw)
     hw->rst_conf.rst_coex = 0;
 }
 
-__attribute__((always_inline))
-static inline void modem_lpcon_ll_reset_i2c_master(modem_lpcon_dev_t *hw)
-{
-    hw->rst_conf.rst_i2c_mst = 1;
-    hw->rst_conf.rst_i2c_mst = 0;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_reset_ble_rtc_timer(modem_lpcon_dev_t *hw)
 {

components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,18 +10,54 @@
 #include <stdint.h>
 #include "soc/soc.h"
 #include "soc/regi2c_defs.h"
+#include "modem/modem_lpcon_struct.h"
+#include "modem/modem_syscon_struct.h"
+#include "soc/i2c_ana_mst_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/**
+ * @brief Enable analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+{
+    MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
+}
+
+/**
+ * @brief Reset analog I2C master
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+{
+    MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
+    MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
+}
+
+/**
+ * @brief Force enable analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en)
+{
+    MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en;
+}
+
+/**
+ * @brief Configure analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void)
+{
+    MODEM_SYSCON.clk_conf.clk_i2c_mst_sel_160m = 1;
+}
+
 /**
  * @brief Start BBPLL self-calibration
  */
 static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void)
 {
-    REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
+    REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
-    REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+    REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
 }
 
 /**
@@ -29,8 +65,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
  */
 static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void)
 {
-    REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+    REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
-    REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
+    REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
 }
 
 /**
@@ -40,7 +76,7 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
  */
 static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void)
 {
-    return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
+    return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
 }
 
 /**
@@ -48,8 +84,7 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
  */
 static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
 {
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD);
+    // TODO: IDF-8727
-    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU);
 }
 
 /**
@@ -57,8 +92,7 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
  */
 static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
 {
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
+    // TODO: IDF-8727
-    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
 }
 
 #ifdef __cplusplus

components/hal/esp32c6/include/hal/modem_lpcon_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -133,12 +133,6 @@ static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_d
     return hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num;
 }
 
-__attribute__((always_inline))
-static inline void modem_lpcon_ll_enable_i2c_master_160m_clock(modem_lpcon_dev_t *hw, bool en)
-{
-    hw->i2c_mst_clk_conf.clk_i2c_mst_sel_160m = en;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src)
 {
@@ -157,12 +151,6 @@ static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool
     hw->clk_conf.clk_coex_en = en;
 }
 
-__attribute__((always_inline))
-static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en)
-{
-    hw->clk_conf.clk_i2c_mst_en = en;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_enable_ble_rtc_timer_clock(modem_lpcon_dev_t *hw, bool en)
 {
@@ -181,12 +169,6 @@ static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw,
     hw->clk_conf_force_on.clk_coex_fo = en;
 }
 
-__attribute__((always_inline))
-static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en)
-{
-    hw->clk_conf_force_on.clk_i2c_mst_fo = en;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_enable_ble_rtc_timer_force_clock(modem_lpcon_dev_t *hw, bool en)
 {
@@ -255,13 +237,6 @@ static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw)
     hw->rst_conf.rst_coex = 0;
 }
 
-__attribute__((always_inline))
-static inline void modem_lpcon_ll_reset_i2c_master(modem_lpcon_dev_t *hw)
-{
-    hw->rst_conf.rst_i2c_mst = 1;
-    hw->rst_conf.rst_i2c_mst = 0;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_reset_ble_rtc_timer(modem_lpcon_dev_t *hw)
 {

components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,11 +10,45 @@
 #include <stdint.h>
 #include "soc/soc.h"
 #include "soc/regi2c_defs.h"
+#include "modem/modem_lpcon_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/**
+ * @brief Enable analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+{
+    MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
+}
+
+/**
+ * @brief Reset analog I2C master
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+{
+    MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
+    MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
+}
+
+/**
+ * @brief Force enable analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en)
+{
+    MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en;
+}
+
+/**
+ * @brief Configure analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void)
+{
+    MODEM_LPCON.i2c_mst_clk_conf.clk_i2c_mst_sel_160m = 1;
+}
+
 /**
  * @brief Start BBPLL self-calibration
  */

components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h

@@ -10,18 +10,54 @@
 #include <stdint.h>
 #include "soc/soc.h"
 #include "soc/regi2c_defs.h"
+#include "modem/modem_lpcon_struct.h"
+#include "modem/modem_syscon_struct.h"
+#include "soc/i2c_ana_mst_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/**
+ * @brief Enable analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+{
+    MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
+}
+
+/**
+ * @brief Reset analog I2C master
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+{
+    MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
+    MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
+}
+
+/**
+ * @brief Force enable analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en)
+{
+    MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en;
+}
+
+/**
+ * @brief Configure analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void)
+{
+    MODEM_SYSCON.clk_conf.clk_i2c_mst_sel_160m = 1;
+}
+
 /**
  * @brief Start BBPLL self-calibration
  */
 static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void)
 {
-    REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
+    REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
-    REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+    REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
 }
 
 /**
@@ -29,8 +65,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
  */
 static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void)
 {
-    REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+    REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
-    REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
+    REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
 }
 
 /**
@@ -40,7 +76,7 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
  */
 static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void)
 {
-    return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
+    return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
 }
 
 /**
@@ -48,8 +84,7 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
  */
 static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
 {
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD);
+    // TODO: IDF-9322
-    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU);
 }
 
 /**
@@ -57,8 +92,7 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
  */
 static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
 {
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
+    // TODO: IDF-9322
-    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
 }
 
 #ifdef __cplusplus

components/hal/esp32h2/include/hal/modem_lpcon_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -67,12 +67,6 @@ static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool
     hw->clk_conf.clk_coex_en = en;
 }
 
-__attribute__((always_inline))
-static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en)
-{
-    hw->clk_conf.clk_i2c_mst_en = en;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_enable_fe_mem_clock(modem_lpcon_dev_t *hw, bool en)
 {
@@ -85,12 +79,6 @@ static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw,
     hw->clk_conf_force_on.clk_coex_fo = en;
 }
 
-__attribute__((always_inline))
-static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en)
-{
-    hw->clk_conf_force_on.clk_i2c_mst_fo = en;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_enable_fe_mem_force_clock(modem_lpcon_dev_t *hw, bool en)
 {
@@ -104,13 +92,6 @@ static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw)
     hw->rst_conf.rst_coex = 0;
 }
 
-__attribute__((always_inline))
-static inline void modem_lpcon_ll_reset_i2c_master(modem_lpcon_dev_t *hw)
-{
-    hw->rst_conf.rst_i2c_mst = 1;
-    hw->rst_conf.rst_i2c_mst = 0;
-}
-
 __attribute__((always_inline))
 static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw)
 {

components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,12 +11,45 @@
 #include "soc/soc.h"
 #include "soc/regi2c_defs.h"
 #include "soc/i2c_ana_mst_reg.h"
-
+#include "modem/modem_lpcon_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/**
+ * @brief Enable analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+{
+    MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
+}
+
+/**
+ * @brief Reset analog I2C master
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+{
+    MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
+    MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
+}
+
+/**
+ * @brief Force enable analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en)
+{
+    MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en;
+}
+
+/**
+ * @brief Configure analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void)
+{
+    // Nothing to configure
+}
+
 /**
  * @brief Start BBPLL self-calibration
  */

components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,11 +11,44 @@
 #include "soc/soc.h"
 #include "soc/regi2c_defs.h"
 #include "soc/hp_sys_clkrst_reg.h"
+#include "soc/lpperi_struct.h"
+#include "soc/i2c_ana_mst_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/**
+ * @brief Enable analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+{
+    LPPERI.clk_en.ck_en_lp_i2cmst = en;
+}
+
+// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset analog I2C master
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+{
+    LPPERI.reset_en.rst_en_lp_i2cmst = 1;
+    LPPERI.reset_en.rst_en_lp_i2cmst = 0;
+}
+
+// LPPERI.reset_en is a shared register, so this function must be used in an atomic way
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+
+/**
+ * @brief Configure analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void)
+{
+    I2C_ANA_MST.clk160m.clk_i2c_mst_sel_160m = 1;
+}
+
 /**
  * @brief Start CPLL self-calibration
  */

components/soc/esp32c5/include/soc/regi2c_defs.h

@@ -9,21 +9,7 @@
 #include "esp_bit_defs.h"
 
 /* Analog function control register */
-#define I2C_MST_ANA_CONF0_REG          0x600AF818
+// I2C_ANA_MST_ANA_CONF0_REG
 #define I2C_MST_BBPLL_STOP_FORCE_HIGH  (BIT(2))
 #define I2C_MST_BBPLL_STOP_FORCE_LOW   (BIT(3))
 #define I2C_MST_BBPLL_CAL_DONE         (BIT(24))
-
-
-#define ANA_CONFIG_REG  0x600AF81C
-#define ANA_CONFIG_S    (8)
-#define ANA_CONFIG_M    (0x3FF)
-
-#define ANA_I2C_SAR_FORCE_PD BIT(18)
-#define ANA_I2C_BBPLL_M      BIT(17) /* Clear to enable BBPLL */
-
-
-#define ANA_CONFIG2_REG  0x600AF820
-#define ANA_CONFIG2_M    BIT(18)
-
-#define ANA_I2C_SAR_FORCE_PU BIT(16)

components/soc/esp32c61/include/soc/regi2c_defs.h

@@ -9,21 +9,7 @@
 #include "esp_bit_defs.h"
 
 /* Analog function control register */
-#define I2C_MST_ANA_CONF0_REG          0x600AF818
+// I2C_ANA_MST_ANA_CONF0_REG
 #define I2C_MST_BBPLL_STOP_FORCE_HIGH  (BIT(2))
 #define I2C_MST_BBPLL_STOP_FORCE_LOW   (BIT(3))
 #define I2C_MST_BBPLL_CAL_DONE         (BIT(24))
-
-
-#define ANA_CONFIG_REG  0x600AF81C
-#define ANA_CONFIG_S    (8)
-#define ANA_CONFIG_M    (0x3FF)
-
-#define ANA_I2C_SAR_FORCE_PD BIT(18)
-#define ANA_I2C_BBPLL_M      BIT(17) /* Clear to enable BBPLL */
-
-
-#define ANA_CONFIG2_REG  0x600AF820
-#define ANA_CONFIG2_M    BIT(18)
-
-#define ANA_I2C_SAR_FORCE_PU BIT(16)

components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h

@@ -275,7 +275,7 @@ typedef union {
 } i2c_ana_mst_date_reg_t;
 
 
-typedef struct {
+typedef struct i2c_ana_mst_dev_t {
     volatile i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
     volatile i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl;
     volatile i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
@@ -293,6 +293,7 @@ typedef struct {
     volatile i2c_ana_mst_date_reg_t date;
 } i2c_ana_mst_dev_t;
 
+extern i2c_ana_mst_dev_t I2C_ANA_MST;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(i2c_ana_mst_dev_t) == 0x3c, "Invalid size of i2c_ana_mst_dev_t structure");

components/soc/esp32p4/ld/esp32p4.peripherals.ld

@@ -85,7 +85,7 @@ PROVIDE ( LP_TOUCH      = 0x50128000 );
 PROVIDE ( LP_GPIO         = 0x5012A000 );
 PROVIDE ( LP_PERI_PMS   = 0x5012E000 );
 PROVIDE ( HP2LP_PERI_PMS = 0x5012E800 );
-PROVIDE ( LP_I2C_ANA_MST = 0x50124000 );
+PROVIDE ( I2C_ANA_MST   = 0x50124000 );
 PROVIDE ( LP_ANA_PERI   = 0x50113000 );
 PROVIDE ( AHB_DMA      =  0x50085000 );
 PROVIDE ( AXI_DMA      =  0x5008a000 );