diff --git a/components/hal/esp32c6/include/hal/i2c_ll.h b/components/hal/esp32c6/include/hal/i2c_ll.h
index 7d2f2ff4b7..797c197359 100644
--- a/components/hal/esp32c6/include/hal/i2c_ll.h
+++ b/components/hal/esp32c6/include/hal/i2c_ll.h
@@ -655,6 +655,20 @@ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw)
     hw->ctr.conf_upgate = 1;
 }
 
+/**
+ * @brief Set the ACK level that the I2C master must send when the Rx FIFO count has reached the threshold value.
+ *        ack_level: 1 (NACK)
+ *        ack_level: 0 (ACK)
+ *
+ * @param  hw Beginning address of the peripheral registers
+ *
+ * @return None
+ */
+static inline void i2c_ll_master_rx_full_ack_level(i2c_dev_t *hw, int ack_level)
+{
+    hw->ctr.rx_full_ack_level = ack_level;
+}
+
 /**
  * @brief Set I2C source clock
  *
diff --git a/components/ulp/lp_core/lp_core/lp_core_i2c.c b/components/ulp/lp_core/lp_core/lp_core_i2c.c
index feccabc5b1..7b73fc1cc2 100644
--- a/components/ulp/lp_core/lp_core/lp_core_i2c.c
+++ b/components/ulp/lp_core/lp_core/lp_core_i2c.c
@@ -382,11 +382,9 @@ esp_err_t lp_core_i2c_master_write_read_device(i2c_port_t lp_i2c_num, uint16_t d
         i2c_ll_write_txfifo(dev, &data_wr[data_idx], fifo_size);
         lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_WRITE, 0, LP_I2C_ACK, s_ack_check_en, fifo_size);
 
-        if (remaining_bytes) {
-            /* This means we have to send more than what can fit in the Tx FIFO. Insert an End command. */
-            lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_END, 0, 0, 0, 0);
-            cmd_idx = 0;
-        }
+        /* Insert an End command to signal the end of the write transaction to the HW */
+        lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_END, 0, 0, 0, 0);
+        cmd_idx = 0;
 
         /* Initiate I2C transfer */
         i2c_ll_update(dev);
diff --git a/components/ulp/lp_core/lp_core_i2c.c b/components/ulp/lp_core/lp_core_i2c.c
index 39741a5a20..21a26fe328 100644
--- a/components/ulp/lp_core/lp_core_i2c.c
+++ b/components/ulp/lp_core/lp_core_i2c.c
@@ -112,7 +112,7 @@ static esp_err_t lp_i2c_config_clk(const lp_core_i2c_cfg_t *cfg)
     lp_periph_set_clk_src(LP_PERIPH_I2C0_MODULE, (soc_module_clk_t)source_clk);
 
     /* Configure LP I2C timing paramters. source_clk is ignored for LP_I2C in this call */
-    i2c_hal_set_bus_timing(&i2c_hal, (i2c_clock_source_t)source_clk, cfg->i2c_timing_cfg.clk_speed_hz, source_freq);
+    i2c_hal_set_bus_timing(&i2c_hal, cfg->i2c_timing_cfg.clk_speed_hz, (i2c_clock_source_t)source_clk, source_freq);
 
     return ret;
 }
@@ -143,6 +143,9 @@ esp_err_t lp_core_i2c_master_init(i2c_port_t lp_i2c_num, const lp_core_i2c_cfg_t
     /* Enable SDA and SCL filtering. This configuration matches the HP I2C filter config */
     i2c_ll_set_filter(i2c_hal.dev, LP_I2C_FILTER_CYC_NUM_DEF);
 
+    /* Configure the I2C master to send a NACK when the Rx FIFO count is full */
+    i2c_ll_master_rx_full_ack_level(i2c_hal.dev, 1);
+
     /* Synchronize the config register values to the LP I2C peripheral clock */
     i2c_ll_update(i2c_hal.dev);