Merge branch 'ci/re-enable_spi_lcd_test_on_p4' into 'master'

Ci(spi_lcd): re-enable spi lcd test on p4

Closes IDF-8975

See merge request espressif/esp-idf!31824

components/esp_lcd/test_apps/.build-test-rules.yml

@@ -52,7 +52,3 @@ components/esp_lcd/test_apps/spi_lcd:
     - esp_driver_spi
   disable:
     - if: SOC_GPSPI_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: test not pass, should be re-enable # TODO: IDF-8975

components/esp_lcd/test_apps/spi_lcd/main/test_spi_board.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -28,6 +28,20 @@ extern "C" {
 #define TEST_LCD_DC_GPIO        1
 #define TEST_LCD_PCLK_GPIO      2
 #define TEST_LCD_DATA0_GPIO     4
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define TEST_LCD_BK_LIGHT_GPIO  23
+#define TEST_LCD_RST_GPIO       6
+#define TEST_LCD_CS_GPIO        4
+#define TEST_LCD_DC_GPIO        3
+#define TEST_LCD_PCLK_GPIO      2
+#define TEST_LCD_DATA0_GPIO     32
+#define TEST_LCD_DATA1_GPIO     33
+#define TEST_LCD_DATA2_GPIO     22
+#define TEST_LCD_DATA3_GPIO     8
+#define TEST_LCD_DATA4_GPIO     21
+#define TEST_LCD_DATA5_GPIO     53
+#define TEST_LCD_DATA6_GPIO     20
+#define TEST_LCD_DATA7_GPIO     5
 #else
 #define TEST_LCD_BK_LIGHT_GPIO  18
 #define TEST_LCD_RST_GPIO       5

components/esp_lcd/test_apps/spi_lcd/pytest_spi_lcd.py

@@ -1,11 +1,9 @@
 # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
-
 import pytest
 from pytest_embedded import Dut
 
 
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='esp32p4 support TBD')  # TODO: IDF-8975
 @pytest.mark.supported_targets
 @pytest.mark.generic
 @pytest.mark.parametrize(

components/hal/esp32p4/include/hal/spi_ll.h

@@ -42,6 +42,7 @@ extern "C" {
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV      1  //clock source have divider before peripheral
 #define SPI_LL_CLK_SRC_PRE_DIV_MAX          512//div1(8bit) * div2(8bit but set const 2)
+#define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
 
 /**
  * The data structure holding calculated clock configuration. Since the
@@ -880,6 +881,16 @@ static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int dela
 {
 }
 
+/**
+ * Determine and unify the default level of mosi line when bus free
+ *
+ * @param hw Beginning address of the peripheral registers.
+ */
+static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
+{
+    hw->ctrl.d_pol = level;     //set default level for MOSI only on IDLE state
+}
+
 /**
  * Set the miso delay applied to the input signal before the internal peripheral. (Preview)
  *