From 36532aaea86094f1e1f301a1ba4c2f32e93bc715 Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 9 Jan 2023 19:44:49 +0800 Subject: [PATCH] mspi: make mspi_timing_tuning.h available for all supported targets --- .../esp_hw_support/mspi_timing_config.h | 184 +++++++++++++ .../esp_hw_support/mspi_timing_tuning.c | 198 +++++++------- .../port/esp32s3/mspi_timing_config.c | 128 ++++----- .../port/esp32s3/mspi_timing_config.h | 256 ------------------ .../port/esp32s3/mspi_timing_tuning_configs.h | 179 ++++++++++++ .../include/hal/mspi_timing_tuning_ll.h | 109 ++++++++ 6 files changed, 628 insertions(+), 426 deletions(-) create mode 100644 components/esp_hw_support/mspi_timing_config.h delete mode 100644 components/esp_hw_support/port/esp32s3/mspi_timing_config.h diff --git a/components/esp_hw_support/mspi_timing_config.h b/components/esp_hw_support/mspi_timing_config.h new file mode 100644 index 0000000000..16ea72789a --- /dev/null +++ b/components/esp_hw_support/mspi_timing_config.h @@ -0,0 +1,184 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "mspi_timing_tuning_configs.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * SPI timing tuning registers. + * Upper layer rely on these 3 registers to tune the timing. + */ +typedef struct { + uint8_t spi_din_mode; /*!< input signal delay mode*/ + uint8_t spi_din_num; /*!< input signal delay number */ + uint8_t extra_dummy_len; /*!< extra dummy length*/ +} mspi_timing_tuning_param_t; + +typedef struct { + mspi_timing_tuning_param_t tuning_config_table[MSPI_TIMING_CONFIG_NUM_DEFAULT]; //available timing tuning configs + uint32_t available_config_num; + uint32_t default_config_id; //If tuning fails, we use this one as default +} mspi_timing_config_t; + +/** + * The SPI FLASH module clock and SPI PSRAM module clock is divided from the SPI core clock, core clock is from system clock: + * + * PLL ----| |---- FLASH Module Clock + * XTAL ----|----> Core Clock ---->| + * RTC8M ----| |---- PSRAM Module Clock + * + */ +typedef enum { + MSPI_TIMING_CONFIG_CORE_CLOCK_80M, + MSPI_TIMING_CONFIG_CORE_CLOCK_120M, + MSPI_TIMING_CONFIG_CORE_CLOCK_160M, + MSPI_TIMING_CONFIG_CORE_CLOCK_240M +} mspi_timing_config_core_clock_t; + + +//-------------------------------------- Generic Config APIs --------------------------------------// +/** + * @brief Get required core clock, under current sdkconfig (Flash / PSRAM mode, speed, etc.) + */ +mspi_timing_config_core_clock_t mspi_timing_config_get_core_clock(void); + +/** + * @brief Set MSPI core clock + * + * @param spi_num SPI0 / 1 + * @param core_clock core clock + */ +void mspi_timing_config_set_core_clock(uint8_t spi_num, mspi_timing_config_core_clock_t core_clock); + +/** + * @brief Set MSPI Flash module clock + * + * @param spi_num SPI0 / 1 + * @param freqdiv Freq divider + */ +void mspi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqdiv); + +/** + * @brief Set MSPI Flash Din Mode and Din Num + * + * @param spi_num SPI0 / 1 + * @param din_mode Din mode + * @param din_num Din num + */ +void mspi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num); + +/** + * @brief Set MSPI Flash extra dummy + * + * @param spi_num SPI0 / 1 + * @param extra_dummy extra dummy + */ +void mspi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy); + +/** + * @brief Configure Flash to read data via SPI1 + * + * @param buf buffer + * @param addr address + * @param len length + */ +void mspi_timing_config_flash_read_data(uint8_t *buf, uint32_t addr, uint32_t len); + +/** + * @brief Set MSPI PSRAM module clock + * + * @param spi_num SPI0 / 1 + * @param freqdiv Freq divider + */ +void mspi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv); + +/** + * @brief Set MSPI PSRAM Din Mode and Din Num + * + * @param spi_num SPI0 / 1 + * @param din_mode Din mode + * @param din_num Din num + */ +void mspi_timing_config_psram_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num); + +/** + * @brief Set MSPI PSRAM extra dummy + * + * @param spi_num SPI0 / 1 + * @param extra_dummy extra dummy + */ +void mspi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy); + +/** + * @brief Configure PSRAM to write data via SPI1 + * + * @param buf buffer + * @param addr address + * @param len length + */ +void mspi_timing_config_psram_write_data(uint8_t *buf, uint32_t addr, uint32_t len); + +/** + * @brief Configure PSRAM to read data via SPI1 + * + * @param buf buffer + * @param addr address + * @param len length + */ +void mspi_timing_config_psram_read_data(uint8_t *buf, uint32_t addr, uint32_t len); + +/*------------------------------------------------------------------------------------------------- + * SPI1 Timing Tuning APIs + * These APIs are only used in `spi_flash_timing_tuning.c/sweep_for_success_sample_points()` for + * configuring SPI1 timing tuning related registers to find best tuning parameter + *-------------------------------------------------------------------------------------------------*/ +/** + * @brief Tune Flash Din Mode and Num of SPI1 + * @param din_mode Din mode + * @param din_num Din num + */ +void mspi_timing_config_flash_tune_din_num_mode(uint8_t din_mode, uint8_t din_num); + +/** + * @brief Tune Flash extra dummy of SPI1 + * @param extra_dummy extra dummy bits + */ +void mspi_timing_config_flash_tune_dummy(uint8_t extra_dummy); + +/** + * @brief Tune PSRAM Din Mode and Num of SPI1 + * @param din_mode Din mode + * @param din_num Din num + */ +void mspi_timing_config_psram_tune_din_num_mode(uint8_t din_mode, uint8_t din_num); + +/** + * @brief Tune PSRAM extra dummy of SPI1 + * @param extra_dummy extra dummy bits + */ +void mspi_timing_config_psram_tune_dummy(uint8_t extra_dummy); + +/** + * SPI1 register info get APIs. These APIs inform `spi_flash_timing_tuning.c` (driver layer) of the SPI1 flash settings. + * In this way, other components (e.g.: esp_flash driver) can get the info from it (`spi_flash_timing_tuning.c`). + */ +void mspi_timing_config_get_cs_timing(uint8_t *setup_time, uint32_t *hold_time); + +/** + * @brief Get Flash clock reg val + */ +uint32_t mspi_timing_config_get_flash_clock_reg(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/mspi_timing_tuning.c b/components/esp_hw_support/mspi_timing_tuning.c index f7ec76d348..ee565b353f 100644 --- a/components/esp_hw_support/mspi_timing_tuning.c +++ b/components/esp_hw_support/mspi_timing_tuning.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,15 +17,15 @@ #include "soc/soc.h" #include "hal/spi_flash_hal.h" #include "hal/mspi_timing_tuning_ll.h" +#include "mspi_timing_config.h" #if CONFIG_IDF_TARGET_ESP32S3 -#include "port/esp32s3/mspi_timing_config.h" #include "esp32s3/rom/cache.h" #endif -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING const static char *TAG = "MSPI Timing"; -static spi_timing_tuning_param_t s_flash_best_timing_tuning_config; -static spi_timing_tuning_param_t s_psram_best_timing_tuning_config; +static mspi_timing_tuning_param_t s_flash_best_timing_tuning_config; +static mspi_timing_tuning_param_t s_psram_best_timing_tuning_config; #endif /*------------------------------------------------------------------------------ @@ -41,21 +41,21 @@ void mspi_timing_set_pin_drive_strength(void) /*------------------------------------------------------------------------------ * Static functions to get clock configs *----------------------------------------------------------------------------*/ -static spi_timing_config_core_clock_t get_mspi_core_clock(void) +static mspi_timing_config_core_clock_t get_mspi_core_clock(void) { - return spi_timing_config_get_core_clock(); + return mspi_timing_config_get_core_clock(); } static uint32_t get_flash_clock_divider(void) { #if CONFIG_ESPTOOLPY_FLASHFREQ_20M - return SPI_TIMING_CORE_CLOCK_MHZ / 20; + return MSPI_TIMING_CORE_CLOCK_MHZ / 20; #elif CONFIG_ESPTOOLPY_FLASHFREQ_40M - return SPI_TIMING_CORE_CLOCK_MHZ / 40; + return MSPI_TIMING_CORE_CLOCK_MHZ / 40; #elif CONFIG_ESPTOOLPY_FLASHFREQ_80M - return SPI_TIMING_CORE_CLOCK_MHZ / 80; + return MSPI_TIMING_CORE_CLOCK_MHZ / 80; #elif CONFIG_ESPTOOLPY_FLASHFREQ_120M - return SPI_TIMING_CORE_CLOCK_MHZ / 120; + return MSPI_TIMING_CORE_CLOCK_MHZ / 120; #else abort(); #endif @@ -64,18 +64,18 @@ static uint32_t get_flash_clock_divider(void) static uint32_t get_psram_clock_divider(void) { #if CONFIG_SPIRAM_SPEED_40M - return SPI_TIMING_CORE_CLOCK_MHZ / 40; + return MSPI_TIMING_CORE_CLOCK_MHZ / 40; #elif CONFIG_SPIRAM_SPEED_80M - return SPI_TIMING_CORE_CLOCK_MHZ / 80; + return MSPI_TIMING_CORE_CLOCK_MHZ / 80; #elif CONFIG_SPIRAM_SPEED_120M - return SPI_TIMING_CORE_CLOCK_MHZ / 120; + return MSPI_TIMING_CORE_CLOCK_MHZ / 120; #else //Will enter this branch only if PSRAM is not enable return 0; #endif } -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING /*------------------------------------------------------------------------------ * Static functions to do timing tuning *----------------------------------------------------------------------------*/ @@ -85,19 +85,19 @@ static uint32_t get_psram_clock_divider(void) static void init_spi1_for_tuning(bool is_flash) { //Get required core clock and module clock settings - spi_timing_config_core_clock_t core_clock = get_mspi_core_clock(); + mspi_timing_config_core_clock_t core_clock = get_mspi_core_clock(); //Set SPI1 core clock. SPI0 and SPI1 share the register for core clock. So we only set SPI0 here. - spi_timing_config_set_core_clock(0, core_clock); + mspi_timing_config_set_core_clock(0, core_clock); //Set SPI1 module clock as required if (is_flash) { uint32_t flash_div = get_flash_clock_divider(); - spi_timing_config_set_flash_clock(1, flash_div); + mspi_timing_config_set_flash_clock(1, flash_div); //Power on HCLK mspi_timinng_ll_enable_flash_hclk(0); } else { //We use SPI1 Flash to tune PSRAM, PSRAM timing related regs do nothing on SPI1 uint32_t psram_div = get_psram_clock_divider(); - spi_timing_config_set_flash_clock(1, psram_div); + mspi_timing_config_set_flash_clock(1, psram_div); //Power on HCLK mspi_timinng_ll_enable_psram_hclk(0); } @@ -107,25 +107,25 @@ static void init_spi1_for_tuning(bool is_flash) * We use different SPI1 timing tuning config to read data to see if current MSPI sampling is successful. * The sampling result will be stored in an array. In this array, successful item will be 1, failed item will be 0. */ -static void sweep_for_success_sample_points(uint8_t *reference_data, const spi_timing_config_t *config, bool is_flash, uint8_t *out_array) +static void sweep_for_success_sample_points(uint8_t *reference_data, const mspi_timing_config_t *config, bool is_flash, uint8_t *out_array) { uint32_t config_idx = 0; - uint8_t read_data[SPI_TIMING_TEST_DATA_LEN] = {0}; + uint8_t read_data[MSPI_TIMING_TEST_DATA_LEN] = {0}; for (config_idx = 0; config_idx < config->available_config_num; config_idx++) { - memset(read_data, 0, SPI_TIMING_TEST_DATA_LEN); -#if SPI_TIMING_FLASH_NEEDS_TUNING + memset(read_data, 0, MSPI_TIMING_TEST_DATA_LEN); +#if MSPI_TIMING_FLASH_NEEDS_TUNING if (is_flash) { - spi_timing_config_flash_tune_din_num_mode(config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num); - spi_timing_config_flash_tune_dummy(config->tuning_config_table[config_idx].extra_dummy_len); - spi_timing_config_flash_read_data(1, read_data, SPI_TIMING_FLASH_TEST_DATA_ADDR, sizeof(read_data)); + mspi_timing_config_flash_tune_din_num_mode(config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num); + mspi_timing_config_flash_tune_dummy(config->tuning_config_table[config_idx].extra_dummy_len); + mspi_timing_config_flash_read_data(read_data, MSPI_TIMING_FLASH_TEST_DATA_ADDR, sizeof(read_data)); } #endif -#if SPI_TIMING_PSRAM_NEEDS_TUNING +#if MSPI_TIMING_PSRAM_NEEDS_TUNING if (!is_flash) { - spi_timing_config_psram_tune_din_num_mode(config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num); - spi_timing_config_psram_tune_dummy(config->tuning_config_table[config_idx].extra_dummy_len); - spi_timing_config_psram_read_data(1, read_data, SPI_TIMING_PSRAM_TEST_DATA_ADDR, SPI_TIMING_TEST_DATA_LEN); + mspi_timing_config_psram_tune_din_num_mode(config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num); + mspi_timing_config_psram_tune_dummy(config->tuning_config_table[config_idx].extra_dummy_len); + mspi_timing_config_psram_read_data(read_data, MSPI_TIMING_PSRAM_TEST_DATA_ADDR, MSPI_TIMING_TEST_DATA_LEN); } #endif if (memcmp(reference_data, read_data, sizeof(read_data)) == 0) { @@ -164,10 +164,10 @@ static void find_max_consecutive_success_points(uint8_t *array, uint32_t size, u *out_end_index = match_num == size ? size : end; } -#if SPI_TIMING_FLASH_DTR_MODE || SPI_TIMING_PSRAM_DTR_MODE -static uint32_t select_best_tuning_config_dtr(spi_timing_config_t *config, uint32_t consecutive_length, uint32_t end) +#if MSPI_TIMING_FLASH_DTR_MODE || MSPI_TIMING_PSRAM_DTR_MODE +static uint32_t select_best_tuning_config_dtr(mspi_timing_config_t *config, uint32_t consecutive_length, uint32_t end) { -#if (SPI_TIMING_CORE_CLOCK_MHZ == 160) +#if (MSPI_TIMING_CORE_CLOCK_MHZ == 160) //Core clock 160M DTR best point scheme uint32_t best_point; @@ -194,10 +194,10 @@ static uint32_t select_best_tuning_config_dtr(spi_timing_config_t *config, uint3 } #endif -#if SPI_TIMING_FLASH_STR_MODE || SPI_TIMING_PSRAM_STR_MODE -static uint32_t select_best_tuning_config_str(spi_timing_config_t *config, uint32_t consecutive_length, uint32_t end) +#if MSPI_TIMING_FLASH_STR_MODE || MSPI_TIMING_PSRAM_STR_MODE +static uint32_t select_best_tuning_config_str(mspi_timing_config_t *config, uint32_t consecutive_length, uint32_t end) { -#if (SPI_TIMING_CORE_CLOCK_MHZ == 120 || SPI_TIMING_CORE_CLOCK_MHZ == 240) +#if (MSPI_TIMING_CORE_CLOCK_MHZ == 120 || MSPI_TIMING_CORE_CLOCK_MHZ == 240) ESP_EARLY_LOGW("FLASH/PSRAM", "DO NOT USE FOR MASS PRODUCTION! Timing parameters may be updated in future IDF version."); //STR best point scheme @@ -221,27 +221,27 @@ static uint32_t select_best_tuning_config_str(spi_timing_config_t *config, uint3 } #endif -static void select_best_tuning_config(spi_timing_config_t *config, uint32_t consecutive_length, uint32_t end, bool is_flash) +static void select_best_tuning_config(mspi_timing_config_t *config, uint32_t consecutive_length, uint32_t end, bool is_flash) { uint32_t best_point = 0; if (is_flash) { -#if SPI_TIMING_FLASH_DTR_MODE +#if MSPI_TIMING_FLASH_DTR_MODE best_point = select_best_tuning_config_dtr(config, consecutive_length, end); -#elif SPI_TIMING_FLASH_STR_MODE +#elif MSPI_TIMING_FLASH_STR_MODE best_point = select_best_tuning_config_str(config, consecutive_length, end); #endif s_flash_best_timing_tuning_config = config->tuning_config_table[best_point]; } else { -#if SPI_TIMING_PSRAM_DTR_MODE +#if MSPI_TIMING_PSRAM_DTR_MODE best_point = select_best_tuning_config_dtr(config, consecutive_length, end); -#elif SPI_TIMING_PSRAM_STR_MODE +#elif MSPI_TIMING_PSRAM_STR_MODE best_point = select_best_tuning_config_str(config, consecutive_length, end); #endif s_psram_best_timing_tuning_config = config->tuning_config_table[best_point]; } } -static void do_tuning(uint8_t *reference_data, spi_timing_config_t *timing_config, bool is_flash) +static void do_tuning(uint8_t *reference_data, mspi_timing_config_t *timing_config, bool is_flash) { /** * We use SPI1 to tune the timing: @@ -251,36 +251,36 @@ static void do_tuning(uint8_t *reference_data, spi_timing_config_t *timing_confi */ uint32_t consecutive_length = 0; uint32_t last_success_point = 0; - uint8_t sample_result[SPI_TIMING_CONFIG_NUM_DEFAULT] = {0}; + uint8_t sample_result[MSPI_TIMING_CONFIG_NUM_DEFAULT] = {0}; init_spi1_for_tuning(is_flash); sweep_for_success_sample_points(reference_data, timing_config, is_flash, sample_result); - find_max_consecutive_success_points(sample_result, SPI_TIMING_CONFIG_NUM_DEFAULT, &consecutive_length, &last_success_point); + find_max_consecutive_success_points(sample_result, MSPI_TIMING_CONFIG_NUM_DEFAULT, &consecutive_length, &last_success_point); select_best_tuning_config(timing_config, consecutive_length, last_success_point, is_flash); } -#endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#endif //#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING /*------------------------------------------------------------------------------ * FLASH Timing Tuning *----------------------------------------------------------------------------*/ -#if SPI_TIMING_FLASH_NEEDS_TUNING -static void get_flash_tuning_configs(spi_timing_config_t *config) +#if MSPI_TIMING_FLASH_NEEDS_TUNING +static void get_flash_tuning_configs(mspi_timing_config_t *config) { -#if SPI_TIMING_FLASH_DTR_MODE +#if MSPI_TIMING_FLASH_DTR_MODE #define FLASH_MODE DTR_MODE -#else //SPI_TIMING_FLASH_STR_MODE +#else //MSPI_TIMING_FLASH_STR_MODE #define FLASH_MODE STR_MODE #endif #if CONFIG_ESPTOOLPY_FLASHFREQ_20M - *config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 20, FLASH_MODE); + *config = MSPI_TIMING_FLASH_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 20, FLASH_MODE); #elif CONFIG_ESPTOOLPY_FLASHFREQ_40M - *config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 40, FLASH_MODE); + *config = MSPI_TIMING_FLASH_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 40, FLASH_MODE); #elif CONFIG_ESPTOOLPY_FLASHFREQ_80M - *config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 80, FLASH_MODE); + *config = MSPI_TIMING_FLASH_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 80, FLASH_MODE); #elif CONFIG_ESPTOOLPY_FLASHFREQ_120M - *config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 120, FLASH_MODE); + *config = MSPI_TIMING_FLASH_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 120, FLASH_MODE); #endif #undef FLASH_MODE @@ -297,9 +297,9 @@ void mspi_timing_flash_tuning(void) //Disable the variable dummy mode when doing timing tuning mspi_timing_ll_enable_flash_variable_dummy(1, false); //GD flash will read error in variable mode with 20MHz - uint8_t reference_data[SPI_TIMING_TEST_DATA_LEN] = {0}; - spi_timing_config_flash_read_data(1, reference_data, SPI_TIMING_FLASH_TEST_DATA_ADDR, sizeof(reference_data)); - spi_timing_config_t timing_configs = {0}; + uint8_t reference_data[MSPI_TIMING_TEST_DATA_LEN] = {0}; + mspi_timing_config_flash_read_data(reference_data, MSPI_TIMING_FLASH_TEST_DATA_ADDR, sizeof(reference_data)); + mspi_timing_config_t timing_configs = {0}; get_flash_tuning_configs(&timing_configs); do_tuning(reference_data, &timing_configs, true); @@ -310,27 +310,27 @@ void mspi_timing_flash_tuning(void) { //Empty function for compatibility, therefore upper layer won't need to know that FLASH in which operation mode and frequency config needs to be tuned } -#endif //SPI_TIMING_FLASH_NEEDS_TUNING +#endif //MSPI_TIMING_FLASH_NEEDS_TUNING /*------------------------------------------------------------------------------ * PSRAM Timing Tuning *----------------------------------------------------------------------------*/ -#if SPI_TIMING_PSRAM_NEEDS_TUNING -static void get_psram_tuning_configs(spi_timing_config_t *config) +#if MSPI_TIMING_PSRAM_NEEDS_TUNING +static void get_psram_tuning_configs(mspi_timing_config_t *config) { -#if SPI_TIMING_PSRAM_DTR_MODE +#if MSPI_TIMING_PSRAM_DTR_MODE #define PSRAM_MODE DTR_MODE -#else //SPI_TIMING_PSRAM_STR_MODE +#else //MSPI_TIMING_PSRAM_STR_MODE #define PSRAM_MODE STR_MODE #endif #if CONFIG_SPIRAM_SPEED_40M - *config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 40, PSRAM_MODE); + *config = MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 40, PSRAM_MODE); #elif CONFIG_SPIRAM_SPEED_80M - *config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 80, PSRAM_MODE); + *config = MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 80, PSRAM_MODE); #elif CONFIG_SPIRAM_SPEED_120M - *config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 120, PSRAM_MODE); + *config = MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 120, PSRAM_MODE); #endif #undef PSRAM_MODE @@ -345,12 +345,12 @@ void mspi_timing_psram_tuning(void) mspi_timing_enter_low_speed_mode(true); // write data into psram, used to do timing tuning test. - uint8_t reference_data[SPI_TIMING_TEST_DATA_LEN]; - for (int i=0; i < SPI_TIMING_TEST_DATA_LEN/4; i++) { + uint8_t reference_data[MSPI_TIMING_TEST_DATA_LEN]; + for (int i=0; i < MSPI_TIMING_TEST_DATA_LEN/4; i++) { ((uint32_t *)reference_data)[i] = 0xa5ff005a; } - spi_timing_config_psram_write_data(1, reference_data, SPI_TIMING_PSRAM_TEST_DATA_ADDR, SPI_TIMING_TEST_DATA_LEN); - spi_timing_config_t timing_configs = {0}; + mspi_timing_config_psram_write_data(reference_data, MSPI_TIMING_PSRAM_TEST_DATA_ADDR, MSPI_TIMING_TEST_DATA_LEN); + mspi_timing_config_t timing_configs = {0}; get_psram_tuning_configs(&timing_configs); //Disable the variable dummy mode when doing timing tuning @@ -365,27 +365,27 @@ void mspi_timing_psram_tuning(void) { //Empty function for compatibility, therefore upper layer won't need to know that FLASH in which operation mode and frequency config needs to be tuned } -#endif //SPI_TIMING_PSRAM_NEEDS_TUNING +#endif //MSPI_TIMING_PSRAM_NEEDS_TUNING /*------------------------------------------------------------------------------ * APIs to make SPI0 (and SPI1) FLASH work for high/low freq *----------------------------------------------------------------------------*/ -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING static void clear_timing_tuning_regs(bool control_spi1) { - spi_timing_config_flash_set_din_mode_num(0, 0, 0); //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg - spi_timing_config_flash_set_extra_dummy(0, 0); + mspi_timing_config_flash_set_din_mode_num(0, 0, 0); //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg + mspi_timing_config_flash_set_extra_dummy(0, 0); if (control_spi1) { - spi_timing_config_flash_set_extra_dummy(1, 0); + mspi_timing_config_flash_set_extra_dummy(1, 0); } else { //Won't touch SPI1 registers } - spi_timing_config_psram_set_din_mode_num(0, 0, 0); - spi_timing_config_psram_set_extra_dummy(0, 0); + mspi_timing_config_psram_set_din_mode_num(0, 0, 0); + mspi_timing_config_psram_set_extra_dummy(0, 0); } -#endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#endif //#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING void mspi_timing_enter_low_speed_mode(bool control_spi1) { @@ -399,35 +399,35 @@ void mspi_timing_enter_low_speed_mode(bool control_spi1) */ //Switch SPI1 and SPI0 clock as 20MHz, set its SPIMEM core clock as 80M and set clock division as 4 - spi_timing_config_set_core_clock(0, SPI_TIMING_CONFIG_CORE_CLOCK_80M); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here. - spi_timing_config_set_flash_clock(0, 4); + mspi_timing_config_set_core_clock(0, MSPI_TIMING_CONFIG_CORE_CLOCK_80M); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here. + mspi_timing_config_set_flash_clock(0, 4); if (control_spi1) { //After tuning, won't touch SPI1 again - spi_timing_config_set_flash_clock(1, 4); + mspi_timing_config_set_flash_clock(1, 4); } //Set PSRAM module clock - spi_timing_config_set_psram_clock(0, 4); + mspi_timing_config_set_psram_clock(0, 4); -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING clear_timing_tuning_regs(control_spi1); #endif } -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING static void set_timing_tuning_regs_as_required(bool control_spi1) { //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg - spi_timing_config_flash_set_din_mode_num(0, s_flash_best_timing_tuning_config.spi_din_mode, s_flash_best_timing_tuning_config.spi_din_num); - spi_timing_config_flash_set_extra_dummy(0, s_flash_best_timing_tuning_config.extra_dummy_len); + mspi_timing_config_flash_set_din_mode_num(0, s_flash_best_timing_tuning_config.spi_din_mode, s_flash_best_timing_tuning_config.spi_din_num); + mspi_timing_config_flash_set_extra_dummy(0, s_flash_best_timing_tuning_config.extra_dummy_len); if (control_spi1) { - spi_timing_config_flash_set_extra_dummy(1, s_flash_best_timing_tuning_config.extra_dummy_len); + mspi_timing_config_flash_set_extra_dummy(1, s_flash_best_timing_tuning_config.extra_dummy_len); } - spi_timing_config_psram_set_din_mode_num(0, s_psram_best_timing_tuning_config.spi_din_mode, s_psram_best_timing_tuning_config.spi_din_num); - spi_timing_config_psram_set_extra_dummy(0, s_psram_best_timing_tuning_config.extra_dummy_len); + mspi_timing_config_psram_set_din_mode_num(0, s_psram_best_timing_tuning_config.spi_din_mode, s_psram_best_timing_tuning_config.spi_din_num); + mspi_timing_config_psram_set_extra_dummy(0, s_psram_best_timing_tuning_config.extra_dummy_len); } -#endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#endif //#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING /** * Set SPI0 FLASH and PSRAM module clock, din_num, din_mode and extra dummy, @@ -438,21 +438,21 @@ static void set_timing_tuning_regs_as_required(bool control_spi1) */ void mspi_timing_enter_high_speed_mode(bool control_spi1) { - spi_timing_config_core_clock_t core_clock = get_mspi_core_clock(); + mspi_timing_config_core_clock_t core_clock = get_mspi_core_clock(); uint32_t flash_div = get_flash_clock_divider(); uint32_t psram_div = get_psram_clock_divider(); //Set SPI01 core clock - spi_timing_config_set_core_clock(0, core_clock); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here. + mspi_timing_config_set_core_clock(0, core_clock); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here. //Set FLASH module clock - spi_timing_config_set_flash_clock(0, flash_div); + mspi_timing_config_set_flash_clock(0, flash_div); if (control_spi1) { - spi_timing_config_set_flash_clock(1, flash_div); + mspi_timing_config_set_flash_clock(1, flash_div); } //Set PSRAM module clock - spi_timing_config_set_psram_clock(0, psram_div); + mspi_timing_config_set_psram_clock(0, psram_div); -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING set_timing_tuning_regs_as_required(true); #endif } @@ -477,18 +477,18 @@ void mspi_timing_change_speed_mode_cache_safe(bool switch_down) *----------------------------------------------------------------------------*/ bool spi_timing_is_tuned(void) { -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING return true; #else return false; #endif } -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config) { // Get clock configuration directly from system. - out_timing_config->clock_config.spimem = spi_timing_config_get_flash_clock_reg(); + out_timing_config->clock_config.spimem = mspi_timing_config_get_flash_clock_reg(); // Get extra dummy length here. Therefore, no matter what freq, or mode. // If it needs tuning, it will return correct extra dummy len. If no tuning, it will return 0. @@ -496,7 +496,7 @@ void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing out_timing_config->extra_dummy = s_flash_best_timing_tuning_config.extra_dummy_len; // Get CS setup/hold value here. - spi_timing_config_get_cs_timing(&out_timing_config->cs_setup, &out_timing_config->cs_hold); + mspi_timing_config_get_cs_timing(&out_timing_config->cs_setup, &out_timing_config->cs_hold); } #else void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config) @@ -504,4 +504,4 @@ void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing // This function shouldn't be called if timing tuning is not used. abort(); } -#endif // SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#endif // MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING diff --git a/components/esp_hw_support/port/esp32s3/mspi_timing_config.c b/components/esp_hw_support/port/esp32s3/mspi_timing_config.c index 96d865afea..4f09c31604 100644 --- a/components/esp_hw_support/port/esp32s3/mspi_timing_config.c +++ b/components/esp_hw_support/port/esp32s3/mspi_timing_config.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,8 +13,10 @@ #include "esp_log.h" #include "soc/spi_mem_reg.h" #include "hal/mspi_timing_tuning_ll.h" -#include "mspi_timing_config.h" +#include "../../mspi_timing_config.h" #include "bootloader_flash.h" +#include "esp32s3/rom/spi_flash.h" +#include "esp32s3/rom/opi_flash.h" #define OPI_PSRAM_SYNC_READ 0x0000 #define OPI_PSRAM_SYNC_WRITE 0x8080 @@ -28,37 +30,37 @@ #define NOT_INIT_INT 127 //-------------------------------------MSPI Clock Setting-------------------------------------// -spi_timing_config_core_clock_t spi_timing_config_get_core_clock(void) +mspi_timing_config_core_clock_t mspi_timing_config_get_core_clock(void) { - switch (SPI_TIMING_CORE_CLOCK_MHZ) { + switch (MSPI_TIMING_CORE_CLOCK_MHZ) { case 80: - return SPI_TIMING_CONFIG_CORE_CLOCK_80M; + return MSPI_TIMING_CONFIG_CORE_CLOCK_80M; case 120: - return SPI_TIMING_CONFIG_CORE_CLOCK_120M; + return MSPI_TIMING_CONFIG_CORE_CLOCK_120M; case 160: - return SPI_TIMING_CONFIG_CORE_CLOCK_160M; + return MSPI_TIMING_CONFIG_CORE_CLOCK_160M; case 240: - return SPI_TIMING_CONFIG_CORE_CLOCK_240M; + return MSPI_TIMING_CONFIG_CORE_CLOCK_240M; default: abort(); } } -void spi_timing_config_set_core_clock(uint8_t spi_num, spi_timing_config_core_clock_t core_clock) +void mspi_timing_config_set_core_clock(uint8_t spi_num, mspi_timing_config_core_clock_t core_clock) { uint32_t reg_val = 0; switch (core_clock) { - case SPI_TIMING_CONFIG_CORE_CLOCK_80M: + case MSPI_TIMING_CONFIG_CORE_CLOCK_80M: reg_val = 0; break; - case SPI_TIMING_CONFIG_CORE_CLOCK_120M: + case MSPI_TIMING_CONFIG_CORE_CLOCK_120M: reg_val = 1; break; - case SPI_TIMING_CONFIG_CORE_CLOCK_160M: + case MSPI_TIMING_CONFIG_CORE_CLOCK_160M: reg_val = 2; break; - case SPI_TIMING_CONFIG_CORE_CLOCK_240M: + case MSPI_TIMING_CONFIG_CORE_CLOCK_240M: reg_val = 3; break; default: @@ -68,20 +70,20 @@ void spi_timing_config_set_core_clock(uint8_t spi_num, spi_timing_config_core_cl mspi_timing_ll_set_core_clock_divider(spi_num, reg_val); } -void spi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqdiv) +void mspi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqdiv) { assert(freqdiv > 0); mspi_timing_ll_set_flash_clock(spi_num, freqdiv); } -void spi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv) +void mspi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv) { mspi_timing_ll_set_psram_clock(spi_num, freqdiv); } /////////////////////////////////////////TIMING TUNING IS NEEDED////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING //If one of the FLASH / PSRAM or both of them need timing tuning, we should build following code typedef enum { PSRAM_CMD_QPI, @@ -103,7 +105,7 @@ extern void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode, #endif //-------------------------------------FLASH timing tuning register config-------------------------------------// -void spi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num) +void mspi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num) { mspi_timing_ll_set_flash_din_mode(spi_num, din_mode); mspi_timing_ll_set_flash_din_num(spi_num, din_num); @@ -157,7 +159,7 @@ static uint32_t spi_timing_config_get_dummy(void) } } -void spi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy) +void mspi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy) { if (bootloader_flash_is_octal_mode_enabled()) { mspi_timing_ll_set_octal_flash_extra_dummy(spi_num, extra_dummy); @@ -176,47 +178,44 @@ void spi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t extra_dumm // Only Quad Flash will run into this branch. uint32_t dummy = spi_timing_config_get_dummy(); - SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, dummy + g_rom_spiflash_dummy_len_plus[spi_num], SPI_MEM_USR_DUMMY_CYCLELEN_S); + mspi_timing_ll_set_quad_flash_dummy(spi_num, dummy + g_rom_spiflash_dummy_len_plus[spi_num]); } //-------------------------------------PSRAM timing tuning register config-------------------------------------// -void spi_timing_config_psram_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num) +void mspi_timing_config_psram_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num) { mspi_timing_ll_set_psram_din_mode(spi_num, din_mode); mspi_timing_ll_set_psram_din_num(spi_num, din_num); } -void spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy) +void mspi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy) { #if CONFIG_SPIRAM_MODE_OCT mspi_timing_ll_set_octal_psram_extra_dummy(spi_num, extra_dummy); #elif CONFIG_SPIRAM_MODE_QUAD //HW workaround: Use normal dummy register to set extra dummy, the calibration dedicated extra dummy register doesn't work for quad mode - SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_USR_RD_SRAM_DUMMY_M); - SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (QPI_PSRAM_FAST_READ_DUMMY + extra_dummy - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); + mspi_timing_ll_set_quad_psram_dummy(spi_num, (QPI_PSRAM_FAST_READ_DUMMY + extra_dummy - 1)); #endif } //-------------------------------------------FLASH/PSRAM Read/Write------------------------------------------// -void spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) +void mspi_timing_config_flash_read_data(uint8_t *buf, uint32_t addr, uint32_t len) { if (bootloader_flash_is_octal_mode_enabled()) { // note that in spi_flash_read API, there is a wait-idle stage, since flash can only be read in idle state. // but after we change the timing settings, we might not read correct idle status via RDSR. // so, here we should use a read API that won't check idle status. - for (int i = 0; i < 16; i++) { - REG_WRITE(SPI_MEM_W0_REG(1) + i*4, 0); - } + mspi_timing_ll_clear_fifo(1); esp_rom_opiflash_read_raw(addr, buf, len); } else { esp_rom_spiflash_read(addr, (uint32_t *)buf, len); } } -static void s_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) +static void s_psram_write_data(uint8_t *buf, uint32_t addr, uint32_t len) { #if CONFIG_SPIRAM_MODE_OCT - esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_OPI_DTR_MODE, + esp_rom_opiflash_exec_cmd(1, ESP_ROM_SPIFLASH_OPI_DTR_MODE, OPI_PSRAM_SYNC_WRITE, 16, addr, 32, OCT_PSRAM_WR_DUMMY_NUM, @@ -225,7 +224,7 @@ static void s_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uin BIT(1), false); #elif CONFIG_SPIRAM_MODE_QUAD - psram_exec_cmd(spi_num, 0, + psram_exec_cmd(1, 0, QPI_PSRAM_WRITE, 8, addr, 24, 0, @@ -236,13 +235,11 @@ static void s_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uin #endif } -static void s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) +static void s_psram_read_data(uint8_t *buf, uint32_t addr, uint32_t len) { #if CONFIG_SPIRAM_MODE_OCT - for (int i = 0; i < 16; i++) { - REG_WRITE(SPI_MEM_W0_REG(1) + i*4, 0); - } - esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_OPI_DTR_MODE, + mspi_timing_ll_clear_fifo(1); + esp_rom_opiflash_exec_cmd(1, ESP_ROM_SPIFLASH_OPI_DTR_MODE, OPI_PSRAM_SYNC_READ, 16, addr, 32, OCT_PSRAM_RD_DUMMY_NUM, @@ -251,7 +248,7 @@ static void s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint BIT(1), false); #elif CONFIG_SPIRAM_MODE_QUAD - psram_exec_cmd(spi_num, 0, + psram_exec_cmd(1, 0, QPI_PSRAM_FAST_READ, 8, addr, 24, QPI_PSRAM_FAST_READ_DUMMY + s_psram_extra_dummy, @@ -262,14 +259,14 @@ static void s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint #endif } -static void s_psram_execution(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len, bool is_read) +static void s_psram_execution(uint8_t *buf, uint32_t addr, uint32_t len, bool is_read) { while (len) { uint32_t length = MIN(len, 32); if (is_read) { - s_psram_read_data(1, buf, addr, length); + s_psram_read_data(buf, addr, length); } else { - s_psram_write_data(1, buf, addr, length); + s_psram_write_data(buf, addr, length); } addr += length; buf += length; @@ -277,14 +274,14 @@ static void s_psram_execution(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint } } -void spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) +void mspi_timing_config_psram_write_data(uint8_t *buf, uint32_t addr, uint32_t len) { - s_psram_execution(spi_num, buf, addr, len, false); + s_psram_execution(buf, addr, len, false); } -void spi_timing_config_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len) +void mspi_timing_config_psram_read_data(uint8_t *buf, uint32_t addr, uint32_t len) { - s_psram_execution(spi_num, buf, addr, len, true); + s_psram_execution(buf, addr, len, true); } @@ -293,80 +290,69 @@ void spi_timing_config_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t a * These APIs are only used in `spi_flash_timing_tuning.c/sweep_for_success_sample_points()` for * configuring SPI1 timing tuning related registers to find best tuning parameter *-------------------------------------------------------------------------------------------------*/ -void spi_timing_config_flash_tune_din_num_mode(uint8_t din_mode, uint8_t din_num) +void mspi_timing_config_flash_tune_din_num_mode(uint8_t din_mode, uint8_t din_num) { /** * 1. SPI_MEM_DINx_MODE(1), SPI_MEM_DINx_NUM(1) are meaningless * SPI0 and SPI1 share the SPI_MEM_DINx_MODE(0), SPI_MEM_DINx_NUM(0) for FLASH timing tuning * 2. We use SPI1 to get the best Flash timing tuning (mode and num) config */ - spi_timing_config_flash_set_din_mode_num(0, din_mode, din_num); + mspi_timing_config_flash_set_din_mode_num(0, din_mode, din_num); } -void spi_timing_config_flash_tune_dummy(uint8_t extra_dummy) +void mspi_timing_config_flash_tune_dummy(uint8_t extra_dummy) { - spi_timing_config_flash_set_extra_dummy(1, extra_dummy); + mspi_timing_config_flash_set_extra_dummy(1, extra_dummy); } -void spi_timing_config_psram_tune_din_num_mode(uint8_t din_mode, uint8_t din_num) +void mspi_timing_config_psram_tune_din_num_mode(uint8_t din_mode, uint8_t din_num) { /** * 1. SPI_MEM_SPI_SMEM_DINx_MODE(1), SPI_MEM_SPI_SMEM_DINx_NUM(1) are meaningless * SPI0 and SPI1 share the SPI_MEM_SPI_SMEM_DINx_MODE(0), SPI_MEM_SPI_SMEM_DINx_NUM(0) for PSRAM timing tuning * 2. We use SPI1 to get the best PSRAM timing tuning (mode and num) config */ - spi_timing_config_psram_set_din_mode_num(0, din_mode, din_num); + mspi_timing_config_psram_set_din_mode_num(0, din_mode, din_num); } -void spi_timing_config_psram_tune_dummy(uint8_t extra_dummy) +void mspi_timing_config_psram_tune_dummy(uint8_t extra_dummy) { #if CONFIG_SPIRAM_MODE_OCT //On 728, for SPI1, flash and psram share the extra dummy register - spi_timing_config_flash_set_extra_dummy(1, extra_dummy); + mspi_timing_config_flash_set_extra_dummy(1, extra_dummy); #elif CONFIG_SPIRAM_MODE_QUAD //Update this `s_psram_extra_dummy`, the `s_psram_read_data` will set dummy according to this `s_psram_extra_dummy` s_psram_extra_dummy = extra_dummy; - SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_USR_DUMMY); // dummy en - SET_PERI_REG_BITS(SPI_MEM_USER1_REG(1), SPI_MEM_USR_DUMMY_CYCLELEN_V, extra_dummy - 1, SPI_MEM_USR_DUMMY_CYCLELEN_S); + mspi_timing_ll_set_quad_flash_dummy(1, extra_dummy - 1); #endif } -#endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING +#endif //#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING /*------------------------------------------------------------------------------------------------- * To let upper lay (spi_flash_timing_tuning.c) to know the necessary timing registers *-------------------------------------------------------------------------------------------------*/ -static bool s_get_cs_setup_enable(void) -{ - return REG_GET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_CS_SETUP); -} - -static bool s_get_cs_hold_enable(void) -{ - return REG_GET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD); -} - /** * Get the SPI1 Flash CS timing setting. The setup time and hold time are both realistic cycles. * @note On ESP32-S3, SPI0/1 share the Flash CS timing registers. Therefore, we should not change these values. * @note This function inform `spi_flash_timing_tuning.c` (driver layer) of the cycle, * and other component (esp_flash driver) should get these cycle and configure the registers accordingly. */ -void spi_timing_config_get_cs_timing(uint8_t *setup_time, uint32_t *hold_time) +void mspi_timing_config_get_cs_timing(uint8_t *setup_time, uint32_t *hold_time) { - *setup_time = REG_GET_FIELD(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME); - *hold_time = REG_GET_FIELD(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME); + *setup_time = mspi_timing_ll_get_cs_setup_val(0); + *hold_time = mspi_timing_ll_get_cs_hold_val(0); /** * The logic here is, if setup_en / hold_en is false, then we return the realistic cycle number, * which is 0. If true, then the realistic cycle number is (reg_value + 1) */ - if (s_get_cs_setup_enable()) { + if (mspi_timing_ll_is_cs_setup_enabled(0)) { *setup_time += 1; } else { *setup_time = 0; } - if (s_get_cs_hold_enable()) { + if (mspi_timing_ll_is_cs_hold_enabled(0)) { *hold_time += 1; } else { *hold_time = 0; @@ -378,7 +364,7 @@ void spi_timing_config_get_cs_timing(uint8_t *setup_time, uint32_t *hold_time) * @note Similarly, this function inform `spi_flash_timing_tuning.c` (driver layer) of the clock setting, * and other component (esp_flash driver) should get these and configure the registers accordingly. */ -uint32_t spi_timing_config_get_flash_clock_reg(void) +uint32_t mspi_timing_config_get_flash_clock_reg(void) { - return READ_PERI_REG(SPI_MEM_CLOCK_REG(1)); + return mspi_timing_ll_get_clock_reg(1); } diff --git a/components/esp_hw_support/port/esp32s3/mspi_timing_config.h b/components/esp_hw_support/port/esp32s3/mspi_timing_config.h deleted file mode 100644 index de8f13dcba..0000000000 --- a/components/esp_hw_support/port/esp32s3/mspi_timing_config.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "esp_flash_partitions.h" -#include "esp32s3/rom/spi_flash.h" -#include "esp32s3/rom/opi_flash.h" -#include "mspi_timing_tuning_configs.h" -#include "esp_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -#define SPI_TIMING_CONFIG_NUM_DEFAULT 20 //This should be larger than the max available timing config num -#define SPI_TIMING_TEST_DATA_LEN 64 -#define SPI_TIMING_PSRAM_TEST_DATA_ADDR 0 -#define SPI_TIMING_FLASH_TEST_DATA_ADDR ESP_BOOTLOADER_OFFSET -/** - * @note BACKGOURND: - * - * The SPI FLASH module clock and SPI PSRAM module clock is divided from the SPI core clock, core clock is from system clock: - * - * PLL ----| |---- FLASH Module Clock - * XTAL ----|----> Core Clock ---->| - * RTC8M ----| |---- PSRAM Module Clock - * - * - * DDR stands for double data rate, MSPI samples at both posedge and negedge. So the real spped will be doubled. - * Speed from high to low: 120M DDR > 80M DDR > 120 SDR > 80M SDR > ... - * - * Module with speed lower than 120M SDR doesn't need to be tuned - * - * @note LIMITATION: - * How to determine the core clock on 728. There are 2 limitations. - * - * 1. MSPI FLASH and PSRAM share the core clock register. Therefore: - * SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ - * - * 2. DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2. - */ -//--------------------------------------FLASH Sampling Mode --------------------------------------// -#define SPI_TIMING_FLASH_DTR_MODE CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR -#define SPI_TIMING_FLASH_STR_MODE CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR -//--------------------------------------FLASH Module Clock --------------------------------------// -#if CONFIG_ESPTOOLPY_FLASHFREQ_20M -#define SPI_TIMING_FLASH_MODULE_CLOCK 20 -#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M -#define SPI_TIMING_FLASH_MODULE_CLOCK 40 -#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M -#define SPI_TIMING_FLASH_MODULE_CLOCK 80 -#else //CONFIG_ESPTOOLPY_FLASHFREQ_120M -#define SPI_TIMING_FLASH_MODULE_CLOCK 120 -#endif -//------------------------------------FLASH Needs Tuning or not-------------------------------------// -#if SPI_TIMING_FLASH_DTR_MODE -#define SPI_TIMING_FLASH_NEEDS_TUNING (SPI_TIMING_FLASH_MODULE_CLOCK > 40) -#elif SPI_TIMING_FLASH_STR_MODE -#define SPI_TIMING_FLASH_NEEDS_TUNING (SPI_TIMING_FLASH_MODULE_CLOCK > 80) -#endif - -//--------------------------------------PSRAM Sampling Mode --------------------------------------// -#define SPI_TIMING_PSRAM_DTR_MODE CONFIG_SPIRAM_MODE_OCT -#define SPI_TIMING_PSRAM_STR_MODE !CONFIG_SPIRAM_MODE_OCT -//--------------------------------------PSRAM Module Clock --------------------------------------// -#if CONFIG_SPIRAM -#if CONFIG_SPIRAM_SPEED_40M -#define SPI_TIMING_PSRAM_MODULE_CLOCK 40 -#elif CONFIG_SPIRAM_SPEED_80M -#define SPI_TIMING_PSRAM_MODULE_CLOCK 80 -#else //CONFIG_SPIRAM_SPEED_120M -#define SPI_TIMING_PSRAM_MODULE_CLOCK 120 -#endif -#else //Disable PSRAM -#define SPI_TIMING_PSRAM_MODULE_CLOCK 10 //Define this to 10MHz, because we rely on `SPI_TIMING_PSRAM_MODULE_CLOCK` macro for calculation and check below, see `Determine the Core Clock` chapter -#endif -//------------------------------------PSRAM Needs Tuning or not-------------------------------------// -#if SPI_TIMING_PSRAM_DTR_MODE -#define SPI_TIMING_PSRAM_NEEDS_TUNING (SPI_TIMING_PSRAM_MODULE_CLOCK > 40) -#elif SPI_TIMING_PSRAM_STR_MODE -#define SPI_TIMING_PSRAM_NEEDS_TUNING (SPI_TIMING_PSRAM_MODULE_CLOCK > 80) -#endif - - -/** - * @note Define A feasible core clock below: SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ and SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ - */ -/** - * Due to MSPI core clock is used by both MSPI Flash and PSRAM clock, - * define the STR/DTR mode here for selecting the core clock: - * @note If either Flash or PSRAM, or both of them are set to DTR mode, then we use DIV 2 - */ -#if (SPI_TIMING_FLASH_DTR_MODE || SPI_TIMING_PSRAM_DTR_MODE) -#define SPI_TIMING_CORE_CLOCK_DIV 2 -#else //#if (SPI_TIMING_FLASH_STR_MODE && (SPI_TIMING_PSRAM_STR_MODE)) -#define SPI_TIMING_CORE_CLOCK_DIV 1 -#endif - -///////////////////////////////////// FLASH CORE CLOCK ///////////////////////////////////// -//FLASH 80M DTR -#if SPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_80M -#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 160 -#endif - -//FLASH 120M DTR -#if SPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M -#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240 -#endif - -//FLASH 120M STR -#if SPI_TIMING_FLASH_STR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M -#if (SPI_TIMING_CORE_CLOCK_DIV == 2) -#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240 -#elif (SPI_TIMING_CORE_CLOCK_DIV == 1) -#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 120 -#endif -#endif //FLASH 120M STR - -///////////////////////////////////// PSRAM CORE CLOCK ///////////////////////////////////// -//PSRAM 80M DTR -#if SPI_TIMING_PSRAM_DTR_MODE && CONFIG_SPIRAM_SPEED_80M -#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 160 -#endif - -//PSRAM 120M STR -#if SPI_TIMING_PSRAM_STR_MODE && CONFIG_SPIRAM_SPEED_120M -#if (SPI_TIMING_CORE_CLOCK_DIV == 2) -#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 240 -#elif (SPI_TIMING_CORE_CLOCK_DIV == 1) -#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 120 -#endif -#endif //PSRAM 120M STR - - -//------------------------------------------Determine the Core Clock-----------------------------------------------// -/** - * @note - * Limitation 1: - * On 728, MSPI FLASH and PSRAM share the core clock register. Therefore, - * the expected CORE CLOCK frequencies should be the same. - */ -#if SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING -ESP_STATIC_ASSERT(SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ, "FLASH and PSRAM Mode configuration are not supported"); -#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ - -//If only FLASH needs tuning, the core clock COULD be as FLASH expected -#elif SPI_TIMING_FLASH_NEEDS_TUNING && !SPI_TIMING_PSRAM_NEEDS_TUNING -ESP_STATIC_ASSERT(SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ % SPI_TIMING_PSRAM_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported"); -#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ - -//If only PSRAM needs tuning, the core clock COULD be as PSRAM expected -#elif !SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING -ESP_STATIC_ASSERT(SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % SPI_TIMING_FLASH_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported"); -#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ - -#else -#define SPI_TIMING_CORE_CLOCK_MHZ 80 -#endif - -/** - * @note - * Limitation 2: DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2. - */ -#define CHECK_POWER_OF_2(n) ((((n) & ((~(n)) + 1))) == (n)) - -#if SPI_TIMING_FLASH_DTR_MODE -ESP_STATIC_ASSERT(CHECK_POWER_OF_2(SPI_TIMING_CORE_CLOCK_MHZ / SPI_TIMING_FLASH_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported"); -#endif -#if SPI_TIMING_PSRAM_DTR_MODE -ESP_STATIC_ASSERT(CHECK_POWER_OF_2(SPI_TIMING_CORE_CLOCK_MHZ / SPI_TIMING_PSRAM_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported"); -#endif - - -//------------------------------------------Helper Macros to get FLASH/PSRAM tuning configs-----------------------------------------------// -#define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \ - (spi_timing_config_t) { .tuning_config_table = MSPI_TIMING_##type##_CONFIG_TABLE_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \ - .available_config_num = MSPI_TIMING_##type##_CONFIG_NUM_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \ - .default_config_id = MSPI_TIMING_##type##_DEFAULT_CONFIG_ID_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode } - -#define _GET_TUNING_CONFIG(type, core_clock, module_clock, mode) __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) - -#define SPI_TIMING_FLASH_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(FLASH, core_clock_mhz, module_clock_mhz, mode) -#define SPI_TIMING_PSRAM_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(PSRAM, core_clock_mhz, module_clock_mhz, mode) - - -/** - * SPI timing tuning registers. The macro `SPI_TIMING_FLASH_CONFIG_TABLE` below is the corresponding register value table. - * Upper layer rely on these 3 registers to tune the timing. - */ -typedef struct { - uint8_t spi_din_mode; /*!< input signal delay mode*/ - uint8_t spi_din_num; /*!< input signal delay number */ - uint8_t extra_dummy_len; /*!< extra dummy length*/ -} spi_timing_tuning_param_t; - -typedef struct { - spi_timing_tuning_param_t tuning_config_table[SPI_TIMING_CONFIG_NUM_DEFAULT]; //available timing tuning configs - uint32_t available_config_num; - uint32_t default_config_id; //If tuning fails, we use this one as default -} spi_timing_config_t; - -/** - * The SPI FLASH module clock and SPI PSRAM module clock is divided from the SPI core clock, core clock is from system clock: - * - * PLL ----| |---- FLASH Module Clock - * XTAL ----|----> Core Clock ---->| - * RTC8M ----| |---- PSRAM Module Clock - * - */ -typedef enum { - SPI_TIMING_CONFIG_CORE_CLOCK_80M, - SPI_TIMING_CONFIG_CORE_CLOCK_120M, - SPI_TIMING_CONFIG_CORE_CLOCK_160M, - SPI_TIMING_CONFIG_CORE_CLOCK_240M -} spi_timing_config_core_clock_t; - - -spi_timing_config_core_clock_t spi_timing_config_get_core_clock(void); -void spi_timing_config_set_core_clock(uint8_t spi_num, spi_timing_config_core_clock_t core_clock); - -void spi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqdiv); -void spi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num); -void spi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy); -void spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len); - -void spi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv); -void spi_timing_config_psram_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num); -void spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy); -void spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len); -void spi_timing_config_psram_read_data(uint8_t spi_num,uint8_t *buf, uint32_t addr, uint32_t len); - -/*------------------------------------------------------------------------------------------------- - * SPI1 Timing Tuning APIs - * These APIs are only used in `spi_flash_timing_tuning.c/sweep_for_success_sample_points()` for - * configuring SPI1 timing tuning related registers to find best tuning parameter - *-------------------------------------------------------------------------------------------------*/ -void spi_timing_config_flash_tune_din_num_mode(uint8_t din_mode, uint8_t din_num); -void spi_timing_config_flash_tune_dummy(uint8_t extra_dummy); -void spi_timing_config_psram_tune_din_num_mode(uint8_t din_mode, uint8_t din_num); -void spi_timing_config_psram_tune_dummy(uint8_t extra_dummy); - -/** - * SPI1 register info get APIs. These APIs inform `spi_flash_timing_tuning.c` (driver layer) of the SPI1 flash settings. - * In this way, other components (e.g.: esp_flash driver) can get the info from it (`spi_flash_timing_tuning.c`). - */ -void spi_timing_config_get_cs_timing(uint8_t *setup_time, uint32_t *hold_time); -uint32_t spi_timing_config_get_flash_clock_reg(void); - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_hw_support/port/esp32s3/mspi_timing_tuning_configs.h b/components/esp_hw_support/port/esp32s3/mspi_timing_tuning_configs.h index 5e98c777c3..3a538ae387 100644 --- a/components/esp_hw_support/port/esp32s3/mspi_timing_tuning_configs.h +++ b/components/esp_hw_support/port/esp32s3/mspi_timing_tuning_configs.h @@ -5,6 +5,185 @@ */ #pragma once +#include "sdkconfig.h" +#include "esp_assert.h" +#include "esp_flash_partitions.h" + +#define MSPI_TIMING_CONFIG_NUM_DEFAULT 20 //This should be larger than the max available timing config num +#define MSPI_TIMING_TEST_DATA_LEN 64 +#define MSPI_TIMING_PSRAM_TEST_DATA_ADDR 0 +#define MSPI_TIMING_FLASH_TEST_DATA_ADDR ESP_BOOTLOADER_OFFSET +/** + * @note BACKGOURND: + * + * The SPI FLASH module clock and SPI PSRAM module clock is divided from the SPI core clock, core clock is from system clock: + * + * PLL ----| |---- FLASH Module Clock + * XTAL ----|----> Core Clock ---->| + * RTC8M ----| |---- PSRAM Module Clock + * + * + * DDR stands for double data rate, MSPI samples at both posedge and negedge. So the real spped will be doubled. + * Speed from high to low: 120M DDR > 80M DDR > 120 SDR > 80M SDR > ... + * + * Module with speed lower than 120M SDR doesn't need to be tuned + * + * @note LIMITATION: + * How to determine the core clock on 728. There are 2 limitations. + * + * 1. MSPI FLASH and PSRAM share the core clock register. Therefore: + * MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ + * + * 2. DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2. + */ +//--------------------------------------FLASH Sampling Mode --------------------------------------// +#define MSPI_TIMING_FLASH_DTR_MODE CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR +#define MSPI_TIMING_FLASH_STR_MODE CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR +//--------------------------------------FLASH Module Clock --------------------------------------// +#if CONFIG_ESPTOOLPY_FLASHFREQ_20M +#define MSPI_TIMING_FLASH_MODULE_CLOCK 20 +#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M +#define MSPI_TIMING_FLASH_MODULE_CLOCK 40 +#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M +#define MSPI_TIMING_FLASH_MODULE_CLOCK 80 +#else //CONFIG_ESPTOOLPY_FLASHFREQ_120M +#define MSPI_TIMING_FLASH_MODULE_CLOCK 120 +#endif +//------------------------------------FLASH Needs Tuning or not-------------------------------------// +#if MSPI_TIMING_FLASH_DTR_MODE +#define MSPI_TIMING_FLASH_NEEDS_TUNING (MSPI_TIMING_FLASH_MODULE_CLOCK > 40) +#elif MSPI_TIMING_FLASH_STR_MODE +#define MSPI_TIMING_FLASH_NEEDS_TUNING (MSPI_TIMING_FLASH_MODULE_CLOCK > 80) +#endif + +//--------------------------------------PSRAM Sampling Mode --------------------------------------// +#define MSPI_TIMING_PSRAM_DTR_MODE CONFIG_SPIRAM_MODE_OCT +#define MSPI_TIMING_PSRAM_STR_MODE !CONFIG_SPIRAM_MODE_OCT +//--------------------------------------PSRAM Module Clock --------------------------------------// +#if CONFIG_SPIRAM +#if CONFIG_SPIRAM_SPEED_40M +#define MSPI_TIMING_PSRAM_MODULE_CLOCK 40 +#elif CONFIG_SPIRAM_SPEED_80M +#define MSPI_TIMING_PSRAM_MODULE_CLOCK 80 +#else //CONFIG_SPIRAM_SPEED_120M +#define MSPI_TIMING_PSRAM_MODULE_CLOCK 120 +#endif +#else //Disable PSRAM +#define MSPI_TIMING_PSRAM_MODULE_CLOCK 10 //Define this to 10MHz, because we rely on `MSPI_TIMING_PSRAM_MODULE_CLOCK` macro for calculation and check below, see `Determine the Core Clock` chapter +#endif +//------------------------------------PSRAM Needs Tuning or not-------------------------------------// +#if MSPI_TIMING_PSRAM_DTR_MODE +#define MSPI_TIMING_PSRAM_NEEDS_TUNING (MSPI_TIMING_PSRAM_MODULE_CLOCK > 40) +#elif MSPI_TIMING_PSRAM_STR_MODE +#define MSPI_TIMING_PSRAM_NEEDS_TUNING (MSPI_TIMING_PSRAM_MODULE_CLOCK > 80) +#endif + + +/** + * @note Define A feasible core clock below: MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ and MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ + */ +/** + * Due to MSPI core clock is used by both MSPI Flash and PSRAM clock, + * define the STR/DTR mode here for selecting the core clock: + * @note If either Flash or PSRAM, or both of them are set to DTR mode, then we use DIV 2 + */ +#if (MSPI_TIMING_FLASH_DTR_MODE || MSPI_TIMING_PSRAM_DTR_MODE) +#define MSPI_TIMING_CORE_CLOCK_DIV 2 +#else //#if (MSPI_TIMING_FLASH_STR_MODE && (MSPI_TIMING_PSRAM_STR_MODE)) +#define MSPI_TIMING_CORE_CLOCK_DIV 1 +#endif + +///////////////////////////////////// FLASH CORE CLOCK ///////////////////////////////////// +//FLASH 80M DTR +#if MSPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_80M +#define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 160 +#endif + +//FLASH 120M DTR +#if MSPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M +#define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240 +#endif + +//FLASH 120M STR +#if MSPI_TIMING_FLASH_STR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M +#if (MSPI_TIMING_CORE_CLOCK_DIV == 2) +#define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240 +#elif (MSPI_TIMING_CORE_CLOCK_DIV == 1) +#define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 120 +#endif +#endif //FLASH 120M STR + +///////////////////////////////////// PSRAM CORE CLOCK ///////////////////////////////////// +//PSRAM 80M DTR +#if MSPI_TIMING_PSRAM_DTR_MODE && CONFIG_SPIRAM_SPEED_80M +#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 160 +#endif + +//PSRAM 120M STR +#if MSPI_TIMING_PSRAM_STR_MODE && CONFIG_SPIRAM_SPEED_120M +#if (MSPI_TIMING_CORE_CLOCK_DIV == 2) +#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 240 +#elif (MSPI_TIMING_CORE_CLOCK_DIV == 1) +#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 120 +#endif +#endif //PSRAM 120M STR + + +//------------------------------------------Determine the Core Clock-----------------------------------------------// +/** + * @note + * Limitation 1: + * On 728, MSPI FLASH and PSRAM share the core clock register. Therefore, + * the expected CORE CLOCK frequencies should be the same. + */ +#if MSPI_TIMING_FLASH_NEEDS_TUNING && MSPI_TIMING_PSRAM_NEEDS_TUNING +ESP_STATIC_ASSERT(MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ, "FLASH and PSRAM Mode configuration are not supported"); +#define MSPI_TIMING_CORE_CLOCK_MHZ MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ + +//If only FLASH needs tuning, the core clock COULD be as FLASH expected +#elif MSPI_TIMING_FLASH_NEEDS_TUNING && !MSPI_TIMING_PSRAM_NEEDS_TUNING +ESP_STATIC_ASSERT(MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_PSRAM_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported"); +#define MSPI_TIMING_CORE_CLOCK_MHZ MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ + +//If only PSRAM needs tuning, the core clock COULD be as PSRAM expected +#elif !MSPI_TIMING_FLASH_NEEDS_TUNING && MSPI_TIMING_PSRAM_NEEDS_TUNING +ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported"); +#define MSPI_TIMING_CORE_CLOCK_MHZ MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ + +#else +#define MSPI_TIMING_CORE_CLOCK_MHZ 80 +#endif + +/** + * @note + * Limitation 2: DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2. + */ +#define CHECK_POWER_OF_2(n) ((((n) & ((~(n)) + 1))) == (n)) + +#if MSPI_TIMING_FLASH_DTR_MODE +ESP_STATIC_ASSERT(CHECK_POWER_OF_2(MSPI_TIMING_CORE_CLOCK_MHZ / MSPI_TIMING_FLASH_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported"); +#endif +#if MSPI_TIMING_PSRAM_DTR_MODE +ESP_STATIC_ASSERT(CHECK_POWER_OF_2(MSPI_TIMING_CORE_CLOCK_MHZ / MSPI_TIMING_PSRAM_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported"); +#endif + + +//------------------------------------------Helper Macros to get FLASH/PSRAM tuning configs-----------------------------------------------// +#define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \ + (mspi_timing_config_t) { .tuning_config_table = MSPI_TIMING_##type##_CONFIG_TABLE_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \ + .available_config_num = MSPI_TIMING_##type##_CONFIG_NUM_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \ + .default_config_id = MSPI_TIMING_##type##_DEFAULT_CONFIG_ID_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode } + +#define _GET_TUNING_CONFIG(type, core_clock, module_clock, mode) __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) + +#define MSPI_TIMING_FLASH_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(FLASH, core_clock_mhz, module_clock_mhz, mode) +#define MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(PSRAM, core_clock_mhz, module_clock_mhz, mode) + + + +/** + * Timing Tuning Parameters + */ //FLASH: core clock 160M, module clock 40M, DTR mode #define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_40M_DTR_MODE {{1, 0, 0}, {0, 0, 0}, {2, 1, 1}, {2, 0, 1}, {2, 2, 2}, {2, 1, 2}, {1, 0, 1}, {0, 0, 1}} #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_40M_DTR_MODE 8 diff --git a/components/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h index 8ca75de1d6..ce400c1c2c 100644 --- a/components/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h +++ b/components/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h @@ -262,6 +262,20 @@ static inline void mspi_timing_ll_set_octal_flash_extra_dummy(uint8_t spi_num, u } } +/** + * Set MSPI Quad Flash dummy + * + * @param spi_num SPI0 / SPI1 + * @param dummy dummy + */ +__attribute__((always_inline)) +static inline void mspi_timing_ll_set_quad_flash_dummy(uint8_t spi_num, uint8_t dummy) +{ + //HW workaround: Use normal dummy register to set extra dummy, the calibration dedicated extra dummy register doesn't work for quad mode + SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_DUMMY); + SET_PERI_REG_BITS(SPI_MEM_USER1_REG(spi_num), SPI_MEM_USR_DUMMY_CYCLELEN_V, dummy, SPI_MEM_USR_DUMMY_CYCLELEN_S); +} + /** * Set MSPI PSRAM din mode * @@ -312,6 +326,101 @@ static inline void mspi_timing_ll_set_octal_psram_extra_dummy(uint8_t spi_num, u } } +/** + * Set MSPI Octal PSRAM dummy + * + * @param spi_num SPI0 / SPI1 + * @param dummy dummy + */ +__attribute__((always_inline)) +static inline void mspi_timing_ll_set_quad_psram_dummy(uint8_t spi_num, uint8_t dummy) +{ + //HW workaround: Use normal dummy register to set extra dummy, the calibration dedicated extra dummy register doesn't work for quad mode + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_USR_RD_SRAM_DUMMY_M); + SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, dummy, SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); +} + +/** + * Clear MSPI hw fifo + * + * @param spi_num SPI0 / SPI1 + */ +__attribute__((always_inline)) +static inline void mspi_timing_ll_clear_fifo(uint8_t spi_num) +{ + for (int i = 0; i < 16; i++) { + REG_WRITE(SPI_MEM_W0_REG(spi_num) + i*4, 0); + } +} + +/** + * Get if cs setup is enabled or not + * + * @param spi_num SPI0 / SPI1 + * + * @return + * true: enabled; false: disabled + */ +__attribute__((always_inline)) +static inline bool mspi_timing_ll_is_cs_setup_enabled(uint8_t spi_num) +{ + return REG_GET_BIT(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP); +} + +/** + * Get cs setup val + * + * @param spi_num SPI0 / SPI1 + * + * @return + * cs setup reg val + */ +static inline uint32_t mspi_timing_ll_get_cs_setup_val(uint8_t spi_num) +{ + return REG_GET_FIELD(SPI_MEM_CTRL2_REG(spi_num), SPI_MEM_CS_SETUP_TIME); +} + +/** + * Get if cs hold is enabled or not + * + * @param spi_num SPI0 / SPI1 + * + * @return + * true: enabled; false: disabled + */ +__attribute__((always_inline)) +static inline bool mspi_timing_ll_is_cs_hold_enabled(uint8_t spi_num) +{ + return REG_GET_BIT(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_HOLD); +} + +/** + * Get cs hold val + * + * @param spi_num SPI0 / SPI1 + * + * @return + * cs hold reg val + */ +static inline uint32_t mspi_timing_ll_get_cs_hold_val(uint8_t spi_num) +{ + return REG_GET_FIELD(SPI_MEM_CTRL2_REG(spi_num), SPI_MEM_CS_HOLD_TIME); +} + +/** + * Get clock reg val + * + * @param spi_num SPI0 / SPI1 + * + * @return + * clock reg val + */ +__attribute__((always_inline)) +static inline uint32_t mspi_timing_ll_get_clock_reg(uint8_t spi_num) +{ + return READ_PERI_REG(SPI_MEM_CLOCK_REG(spi_num)); +} + #ifdef __cplusplus } #endif