From 473f39c31f00ed14dded0fc46dd165afe5552cc9 Mon Sep 17 00:00:00 2001 From: wanckl Date: Fri, 30 Aug 2024 15:41:11 +0800 Subject: [PATCH 1/2] fix(driver_spi): move macro GPIO_MATRIX_DELAY_NS out from soc.h --- components/hal/esp32/include/hal/gpio_ll.h | 3 +++ components/hal/esp32c2/include/hal/spi_ll.h | 8 ++++---- components/hal/esp32c3/include/hal/spi_ll.h | 2 +- components/hal/esp32c5/include/hal/spi_ll.h | 2 +- components/hal/esp32c6/include/hal/spi_ll.h | 2 +- components/hal/esp32h2/include/hal/spi_ll.h | 2 +- components/hal/esp32p4/include/hal/spi_ll.h | 4 ++-- components/hal/esp32s2/include/hal/spi_ll.h | 2 +- components/hal/esp32s3/include/hal/spi_ll.h | 2 +- components/hal/spi_flash_hal.c | 8 ++++++-- components/hal/spi_hal.c | 11 +++++++++-- components/soc/esp32/include/soc/soc.h | 1 - components/soc/esp32c2/include/soc/soc.h | 1 - components/soc/esp32c3/include/soc/soc.h | 1 - components/soc/esp32c5/include/soc/soc.h | 1 - components/soc/esp32c6/include/soc/soc.h | 1 - components/soc/esp32c61/include/soc/soc.h | 1 - components/soc/esp32h2/include/soc/soc.h | 1 - components/soc/esp32p4/include/soc/soc.h | 1 - components/soc/esp32s2/include/soc/soc.h | 1 - components/soc/esp32s3/include/soc/soc.h | 1 - 21 files changed, 30 insertions(+), 26 deletions(-) diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h index 6ab6dfd4da..4728683903 100644 --- a/components/hal/esp32/include/hal/gpio_ll.h +++ b/components/hal/esp32/include/hal/gpio_ll.h @@ -33,6 +33,9 @@ extern const uint8_t GPIO_PIN_MUX_REG_OFFSET[SOC_GPIO_PIN_COUNT]; // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) +// the gpio matrix signal routing const time +#define GPIO_LL_MATRIX_DELAY_NS 25 + #define GPIO_LL_APP_CPU_INTR_ENA (BIT(0)) #define GPIO_LL_APP_CPU_NMI_INTR_ENA (BIT(1)) #define GPIO_LL_PRO_CPU_INTR_ENA (BIT(2)) diff --git a/components/hal/esp32c2/include/hal/spi_ll.h b/components/hal/esp32c2/include/hal/spi_ll.h index f6ae3f4b17..4acd7b1721 100644 --- a/components/hal/esp32c2/include/hal/spi_ll.h +++ b/components/hal/esp32c2/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -313,7 +313,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw) /** * Reset SPI CPU TX FIFO * - * On ESP32C3, this function is not separated + * On ESP32C2, this function is not separated * * @param hw Beginning address of the peripheral registers. */ @@ -326,7 +326,7 @@ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) /** * Reset SPI CPU RX FIFO * - * On ESP32C3, this function is not separated + * On ESP32C2, this function is not separated * * @param hw Beginning address of the peripheral registers. */ @@ -859,7 +859,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32C2 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32c3/include/hal/spi_ll.h b/components/hal/esp32c3/include/hal/spi_ll.h index 9bb2f3ab7d..2b5ea2346a 100644 --- a/components/hal/esp32c3/include/hal/spi_ll.h +++ b/components/hal/esp32c3/include/hal/spi_ll.h @@ -861,7 +861,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32C3 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32c5/include/hal/spi_ll.h b/components/hal/esp32c5/include/hal/spi_ll.h index 5dd81c20c2..6af7784d9c 100644 --- a/components/hal/esp32c5/include/hal/spi_ll.h +++ b/components/hal/esp32c5/include/hal/spi_ll.h @@ -859,7 +859,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32C5 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32c6/include/hal/spi_ll.h b/components/hal/esp32c6/include/hal/spi_ll.h index 32e76c6ee3..9ef3d32280 100644 --- a/components/hal/esp32c6/include/hal/spi_ll.h +++ b/components/hal/esp32c6/include/hal/spi_ll.h @@ -853,7 +853,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32C6 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32h2/include/hal/spi_ll.h b/components/hal/esp32h2/include/hal/spi_ll.h index 944bad7ef4..7fbb59aa2c 100644 --- a/components/hal/esp32h2/include/hal/spi_ll.h +++ b/components/hal/esp32h2/include/hal/spi_ll.h @@ -852,7 +852,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32H2 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32p4/include/hal/spi_ll.h b/components/hal/esp32p4/include/hal/spi_ll.h index e45f484549..68299190eb 100644 --- a/components/hal/esp32p4/include/hal/spi_ll.h +++ b/components/hal/esp32p4/include/hal/spi_ll.h @@ -324,7 +324,7 @@ static inline void spi_ll_apply_config(spi_dev_t *hw) /** * Trigger start of user-defined transaction. - * The synchronization between two clock domains is required in ESP32-S3 + * The synchronization between two clock domains is required in ESP32P4 * * @param hw Beginning address of the peripheral registers. */ @@ -919,7 +919,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32P4 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h index efb690877c..19d62c57e2 100644 --- a/components/hal/esp32s2/include/hal/spi_ll.h +++ b/components/hal/esp32s2/include/hal/spi_ll.h @@ -871,7 +871,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32S2 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/esp32s3/include/hal/spi_ll.h b/components/hal/esp32s3/include/hal/spi_ll.h index 6ccaec8533..bdbeb9267d 100644 --- a/components/hal/esp32s3/include/hal/spi_ll.h +++ b/components/hal/esp32s3/include/hal/spi_ll.h @@ -880,7 +880,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) /** * Set the delay of SPI clocks before the first SPI clock after the CS active edge. * - * Note ESP32 doesn't support to use this feature when command/address phases + * Note ESP32S3 doesn't support to use this feature when command/address phases * are used in full duplex mode. * * @param hw Beginning address of the peripheral registers. diff --git a/components/hal/spi_flash_hal.c b/components/hal/spi_flash_hal.c index 75414367ef..d758608c8b 100644 --- a/components/hal/spi_flash_hal.c +++ b/components/hal/spi_flash_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,6 +11,7 @@ #include #include #include "soc/soc_caps.h" +#include "hal/gpio_ll.h" //for GPIO_LL_MATRIX_DELAY_NS #include "hal/spi_flash_hal.h" #include "hal/assert.h" #include "hal/log.h" @@ -64,7 +65,10 @@ static inline int get_dummy_n(bool gpio_is_used, int input_delay_ns, int eff_clk const int apbclk_kHz = APB_CLK_FREQ / 1000; //calculate how many apb clocks a period has const int apbclk_n = APB_CLK_FREQ / eff_clk; - const int gpio_delay_ns = gpio_is_used ? GPIO_MATRIX_DELAY_NS : 0; + int gpio_delay_ns = 0; +#if GPIO_LL_MATRIX_DELAY_NS + gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#endif //calculate how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. int apb_period_n = (1 + input_delay_ns + gpio_delay_ns) * apbclk_kHz / 1000 / 1000; diff --git a/components/hal/spi_hal.c b/components/hal/spi_hal.c index 18a17865d7..90ff24de39 100644 --- a/components/hal/spi_hal.c +++ b/components/hal/spi_hal.c @@ -9,6 +9,7 @@ #include "hal/spi_hal.h" #include "hal/log.h" #include "hal/assert.h" +#include "hal/gpio_ll.h" //for GPIO_LL_MATRIX_DELAY_NS #include "soc/soc_caps.h" #include "soc/clk_tree_defs.h" @@ -115,7 +116,10 @@ void spi_hal_cal_timing(int source_freq_hz, int eff_clk, bool gpio_is_used, int const int apbclk_kHz = source_freq_hz / 1000; //how many apb clocks a period has const int spiclk_apb_n = source_freq_hz / eff_clk; - const int gpio_delay_ns = gpio_is_used ? GPIO_MATRIX_DELAY_NS : 0; + int gpio_delay_ns = 0; +#if GPIO_LL_MATRIX_DELAY_NS + gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#endif //how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. int delay_apb_n = (1 + input_delay_ns + gpio_delay_ns) * apbclk_kHz / 1000 / 1000; @@ -146,7 +150,10 @@ void spi_hal_cal_timing(int source_freq_hz, int eff_clk, bool gpio_is_used, int int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns) { const int apbclk_kHz = APB_CLK_FREQ / 1000; - const int gpio_delay_ns = gpio_is_used ? GPIO_MATRIX_DELAY_NS : 0; + int gpio_delay_ns = 0; +#if GPIO_LL_MATRIX_DELAY_NS + gpio_delay_ns = gpio_is_used ? GPIO_LL_MATRIX_DELAY_NS : 0; +#endif //how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off. int delay_apb_n = (1 + input_delay_ns + gpio_delay_ns) * apbclk_kHz / 1000 / 1000; diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index 15a1812180..2eb996fd2b 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -166,7 +166,6 @@ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 26 // CPU is 80MHz -#define GPIO_MATRIX_DELAY_NS 25 //}} /* Overall memory map */ diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index b271cc2ca2..a57b15794a 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -152,7 +152,6 @@ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 4 #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 40 // CPU is 40MHz -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index b4969ec811..d661c4eb12 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -146,7 +146,6 @@ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 40 // CPU is 80MHz -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h index 7f4536f0d8..7134121e4b 100644 --- a/components/soc/esp32c5/include/soc/soc.h +++ b/components/soc/esp32c5/include/soc/soc.h @@ -138,7 +138,6 @@ #define APB_CLK_FREQ ( 40*1000000 ) #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) #define REF_CLK_FREQ ( 1000000 ) -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index 7986a5c2f1..6778a1764b 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -143,7 +143,6 @@ #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) #define REF_CLK_FREQ ( 1000000 ) #define XTAL_CLK_FREQ (40*1000000) -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h index ab6fe10aac..01ed3d40db 100644 --- a/components/soc/esp32c61/include/soc/soc.h +++ b/components/soc/esp32c61/include/soc/soc.h @@ -138,7 +138,6 @@ #define APB_CLK_FREQ ( 40*1000000 ) #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) #define REF_CLK_FREQ ( 1000000 ) -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 1191c37e61..f3d2b2a904 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -141,7 +141,6 @@ #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 32*1000000 ) #define REF_CLK_FREQ ( 1000000 ) #define XTAL_CLK_FREQ (32*1000000) -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h index 5c564db301..5b1b8490a6 100644 --- a/components/soc/esp32p4/include/soc/soc.h +++ b/components/soc/esp32p4/include/soc/soc.h @@ -141,7 +141,6 @@ #define APB_CLK_FREQ ( 90*1000000 ) #define REF_CLK_FREQ ( 1000000 ) #define XTAL_CLK_FREQ (40*1000000) -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index 6bca2b7bea..12d97311ff 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -152,7 +152,6 @@ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 40 // CPU is 80MHz -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 2600af7e59..056c6d9f4e 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -162,7 +162,6 @@ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 40 // CPU is 80MHz -#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ From 19c6e77a3161a5b4c3a88ee2a46e7d0f834192e2 Mon Sep 17 00:00:00 2001 From: wanckl Date: Fri, 30 Aug 2024 15:51:17 +0800 Subject: [PATCH 2/2] fix(mspi): collect mspi iomux pin macro from iomux_reg.h to spi_pins.h --- .../src/bootloader_flash_config_esp32.c | 34 ++++++------ .../src/bootloader_flash_config_esp32c2.c | 12 ++--- .../src/bootloader_flash_config_esp32c3.c | 12 ++--- .../src/bootloader_flash_config_esp32c5.c | 12 ++--- .../src/bootloader_flash_config_esp32c6.c | 12 ++--- .../src/bootloader_flash_config_esp32c61.c | 12 ++--- .../src/bootloader_flash_config_esp32h2.c | 12 ++--- .../src/bootloader_flash_config_esp32p4.c | 12 ++--- .../src/bootloader_flash_config_esp32s2.c | 14 ++--- .../src/bootloader_flash_config_esp32s3.c | 12 ++--- .../include/test_spi_utils.h | 2 +- components/esp_hw_support/sleep_modes.c | 10 ++-- .../esp_psram/device/esp_psram_impl_ap_quad.c | 2 +- .../esp_psram/device/esp_quad_psram_defs.h | 22 ++++---- .../esp_psram/esp32/esp_psram_impl_quad.c | 15 +++--- .../esp_psram/esp32s2/esp_psram_impl_quad.c | 18 +++---- .../esp_psram/esp32s3/esp_psram_impl_octal.c | 2 +- components/soc/esp32/include/soc/spi_pins.h | 45 +++++++--------- components/soc/esp32/spi_periph.c | 38 +++++-------- components/soc/esp32c2/include/soc/spi_pins.h | 37 +++++++------ components/soc/esp32c3/include/soc/spi_pins.h | 53 ++++++++----------- components/soc/esp32c5/include/soc/spi_pins.h | 33 ++++++------ components/soc/esp32c6/include/soc/spi_pins.h | 37 +++++++------ .../soc/esp32c61/include/soc/io_mux_reg.h | 8 --- .../soc/esp32c61/include/soc/spi_pins.h | 18 ++++--- components/soc/esp32h2/include/soc/spi_pins.h | 37 +++++++------ components/soc/esp32p4/include/soc/spi_pins.h | 19 ++++++- components/soc/esp32s2/include/soc/spi_pins.h | 53 +++++++++---------- components/soc/esp32s2/spi_periph.c | 17 +++--- components/soc/esp32s3/include/soc/spi_pins.h | 53 +++++++++---------- components/spi_flash/flash_ops.c | 28 +++++----- .../esp_flash/main/test_esp_flash_drv.c | 2 - tools/ci/check_copyright_ignore.txt | 5 -- 33 files changed, 339 insertions(+), 359 deletions(-) diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c index 3c23ec5abc..e50dcff87e 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -28,12 +28,12 @@ #include "bootloader_flash_priv.h" #include "bootloader_init.h" -#define FLASH_CLK_IO SPI_CLK_GPIO_NUM -#define FLASH_CS_IO SPI_CS0_GPIO_NUM -#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM -#define FLASH_SPID_IO SPI_D_GPIO_NUM -#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM -#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM +#define FLASH_CLK_IO MSPI_IOMUX_PIN_NUM_CLK +#define FLASH_CS_IO MSPI_IOMUX_PIN_NUM_CS0 +#define FLASH_SPIQ_IO MSPI_IOMUX_PIN_NUM_MISO +#define FLASH_SPID_IO MSPI_IOMUX_PIN_NUM_MOSI +#define FLASH_SPIWP_IO MSPI_IOMUX_PIN_NUM_WP +#define FLASH_SPIHD_IO MSPI_IOMUX_PIN_NUM_HD void bootloader_flash_update_id(void) { @@ -98,15 +98,15 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr) } else { const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { - esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0); - esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0); - esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0); - esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0); - esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0); - esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0); - esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0); - esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0); - esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0); + esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0); + esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0); + esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0); + esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0); + esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0); + esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0); + esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0); + esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0); + esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0); //select pin function gpio gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO); gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO); @@ -190,7 +190,7 @@ int bootloader_flash_get_wp_pin(void) case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302: return ESP32_PICO_V3_GPIO; default: - return SPI_WP_GPIO_NUM; + return MSPI_IOMUX_PIN_NUM_WP; } #endif } diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c index 8aa9df3493..fa4f3c5a3c 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c @@ -88,12 +88,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv) { // IDF-4066 const uint32_t spiconfig = 0; - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK; + uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO; + uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI; + uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0; + uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD; + uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP; if (spiconfig == 0) { } diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c index efcae99098..f537240bd9 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c @@ -92,12 +92,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv) { const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK; + uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO; + uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI; + uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0; + uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD; + uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP; if (spiconfig == 0) { } else { diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c index 7c2cf1476f..92d259b3e9 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c @@ -74,12 +74,12 @@ static const char *TAG = "boot.esp32c5"; void IRAM_ATTR bootloader_configure_spi_pins(int drv) { - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK; + uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO; + uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI; + uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0; + uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD; + uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP; esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); esp_rom_gpio_pad_set_drv(q_gpio_num, drv); esp_rom_gpio_pad_set_drv(d_gpio_num, drv); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c index 4e6701de9a..62ec882741 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c @@ -69,12 +69,12 @@ static const char *TAG = "boot.esp32c6"; void IRAM_ATTR bootloader_configure_spi_pins(int drv) { - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK; + uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO; + uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI; + uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0; + uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD; + uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP; esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); esp_rom_gpio_pad_set_drv(q_gpio_num, drv); esp_rom_gpio_pad_set_drv(d_gpio_num, drv); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c index 06d3db2796..077d67afa2 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c @@ -70,12 +70,12 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) void IRAM_ATTR bootloader_configure_spi_pins(int drv) { - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK; + uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO; + uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI; + uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0; + uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD; + uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP; esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); esp_rom_gpio_pad_set_drv(q_gpio_num, drv); esp_rom_gpio_pad_set_drv(d_gpio_num, drv); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c index 11b366b1de..b0f1ff411f 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c @@ -70,12 +70,12 @@ static const char *TAG = "boot.esp32h2"; void IRAM_ATTR bootloader_configure_spi_pins(int drv) { - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK; + uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO; + uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI; + uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0; + uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD; + uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP; esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); esp_rom_gpio_pad_set_drv(q_gpio_num, drv); esp_rom_gpio_pad_set_drv(d_gpio_num, drv); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c index 7b1c01d080..866f6572d0 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c @@ -66,12 +66,12 @@ static const char *TAG = "boot.esp32p4"; void IRAM_ATTR bootloader_configure_spi_pins(int drv) { - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK; + uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO; + uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI; + uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0; + uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD; + uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP; esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); esp_rom_gpio_pad_set_drv(q_gpio_num, drv); esp_rom_gpio_pad_set_drv(d_gpio_num, drv); diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c index 40587e4960..05978269db 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -94,12 +94,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv) { const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK; + uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO; + uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI; + uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0; + uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD; + uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP; if (spiconfig == 0) { } else { diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c index 046553332c..83b02ba069 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c @@ -105,12 +105,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv) { const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK; + uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO; + uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI; + uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0; + uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD; + uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP; if (spiconfig == 0) { } else { diff --git a/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h b/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h index 9513e716ad..0fdcb27e49 100644 --- a/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h +++ b/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h @@ -99,7 +99,7 @@ #define TEST_DMA_CHAN_MASTER GET_DMA_CHAN(TEST_SPI_HOST) #define TEST_DMA_CHAN_SLAVE GET_DMA_CHAN(TEST_SLAVE_HOST) -#define FUNC_SPI 1 +#define FUNC_SPI SPI2_FUNC_NUM #define FUNC_GPIO PIN_FUNC_GPIO //Delay information diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index ec856782ff..d49c1920c8 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -26,6 +26,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "soc/soc_caps.h" +#include "soc/spi_pins.h" #include "soc/chip_revision.h" #include "driver/rtc_io.h" #include "hal/efuse_hal.h" @@ -51,7 +52,6 @@ #include "hal/rtc_hal.h" #include "soc/rtc.h" -#include "soc/soc_caps.h" #include "regi2c_ctrl.h" //For `REGI2C_ANA_CALI_PD_WORKAROUND`, temp #include "hal/cache_hal.h" @@ -998,12 +998,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m #if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND /* Cache suspend also means SPI bus IDLE, then we can hold SPI CS pin safely */ #if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359 - gpio_ll_hold_en(&GPIO, SPI_CS0_GPIO_NUM); + gpio_ll_hold_en(&GPIO, MSPI_IOMUX_PIN_NUM_CS0); #endif #endif #if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM /* Cache suspend also means SPI bus IDLE, then we can hold SPI CS pin safely */ - gpio_ll_hold_en(&GPIO, SPI_CS1_GPIO_NUM); + gpio_ll_hold_en(&GPIO, MSPI_IOMUX_PIN_NUM_CS1); #endif } #endif @@ -1059,11 +1059,11 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m if(!(pd_flags & RTC_SLEEP_PD_VDDSDIO) && (pd_flags & PMU_SLEEP_PD_TOP)) { #if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND #if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359 - gpio_ll_hold_dis(&GPIO, SPI_CS0_GPIO_NUM); + gpio_ll_hold_dis(&GPIO, MSPI_IOMUX_PIN_NUM_CS0); #endif #endif #if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM - gpio_ll_hold_dis(&GPIO, SPI_CS1_GPIO_NUM); + gpio_ll_hold_dis(&GPIO, MSPI_IOMUX_PIN_NUM_CS1); #endif } #endif diff --git a/components/esp_psram/device/esp_psram_impl_ap_quad.c b/components/esp_psram/device/esp_psram_impl_ap_quad.c index 9c1b2786d4..a269751388 100644 --- a/components/esp_psram/device/esp_psram_impl_ap_quad.c +++ b/components/esp_psram/device/esp_psram_impl_ap_quad.c @@ -176,7 +176,7 @@ static void psram_gpio_config(void) { //CS1 uint8_t cs1_io = PSRAM_CS_IO; - if (cs1_io == SPI_CS1_GPIO_NUM) { + if (cs1_io == MSPI_IOMUX_PIN_NUM_CS1) { gpio_ll_func_sel(&GPIO, cs1_io, FUNC_SPICS1_SPICS1); } else { esp_rom_gpio_connect_out_signal(cs1_io, FSPICS1_OUT_IDX, 0, 0); diff --git a/components/esp_psram/device/esp_quad_psram_defs.h b/components/esp_psram/device/esp_quad_psram_defs.h index 171f310ec0..67b5044f3f 100644 --- a/components/esp_psram/device/esp_quad_psram_defs.h +++ b/components/esp_psram/device/esp_quad_psram_defs.h @@ -8,7 +8,7 @@ #pragma once -#include "soc/io_mux_reg.h" +#include "soc/spi_pins.h" #ifdef __cplusplus extern "C" { @@ -57,18 +57,18 @@ extern "C" { // IO-pins for PSRAM. // PSRAM clock and cs IO should be configured based on hardware design. -#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM -#define PSRAM_CS_IO SPI_CS1_GPIO_NUM -#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM -#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM -#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM -#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM +#define PSRAM_CLK_IO MSPI_IOMUX_PIN_NUM_CLK +#define PSRAM_CS_IO MSPI_IOMUX_PIN_NUM_CS1 +#define PSRAM_SPIQ_SD0_IO MSPI_IOMUX_PIN_NUM_MISO +#define PSRAM_SPID_SD1_IO MSPI_IOMUX_PIN_NUM_MOSI +#define PSRAM_SPIWP_SD3_IO MSPI_IOMUX_PIN_NUM_WP +#define PSRAM_SPIHD_SD2_IO MSPI_IOMUX_PIN_NUM_HD -#define PSRAM_CMD_LENGTH 8 -#define PSRAM_ADDR_LENGTH 24 +#define PSRAM_CMD_LENGTH 8 +#define PSRAM_ADDR_LENGTH 24 -#define PSRAM_CS_HOLD_VAL 1 -#define PSRAM_CS_SETUP_VAL 1 +#define PSRAM_CS_HOLD_VAL 1 +#define PSRAM_CS_SETUP_VAL 1 #ifdef __cplusplus } diff --git a/components/esp_psram/esp32/esp_psram_impl_quad.c b/components/esp_psram/esp32/esp_psram_impl_quad.c index 5014358a87..b7e802cef0 100644 --- a/components/esp_psram/esp32/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32/esp_psram_impl_quad.c @@ -93,11 +93,12 @@ typedef enum { // WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines // hardcode the flash pins as well, making this code incompatible with either a setup // that has the flash on non-standard pins or ESP32s with built-in flash. -#define PSRAM_SPIQ_SD0_IO 7 -#define PSRAM_SPID_SD1_IO 8 -#define PSRAM_SPIWP_SD3_IO 10 -#define PSRAM_SPIHD_SD2_IO 9 +#define PSRAM_SPIQ_SD0_IO MSPI_IOMUX_PIN_NUM_MISO +#define PSRAM_SPID_SD1_IO MSPI_IOMUX_PIN_NUM_MOSI +#define PSRAM_SPIHD_SD2_IO MSPI_IOMUX_PIN_NUM_HD +#define PSRAM_SPIWP_SD3_IO MSPI_IOMUX_PIN_NUM_WP +// HSPI Pins #define FLASH_HSPI_CLK_IO 14 #define FLASH_HSPI_CS_IO 15 #define PSRAM_HSPI_SPIQ_SD0_IO 12 @@ -800,7 +801,7 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_speed_ esp_rom_gpio_connect_in_signal(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0); //select pin function gpio - if ((psram_io->flash_clk_io == SPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) { + if ((psram_io->flash_clk_io == MSPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) { //flash clock signal should come from IO MUX. gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUNC_SD_CLK_SPICLK); } else { @@ -909,8 +910,8 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { - psram_io.flash_clk_io = SPI_IOMUX_PIN_NUM_CLK; - psram_io.flash_cs_io = SPI_IOMUX_PIN_NUM_CS; + psram_io.flash_clk_io = MSPI_IOMUX_PIN_NUM_CLK; + psram_io.flash_cs_io = MSPI_IOMUX_PIN_NUM_CS0; psram_io.psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO; psram_io.psram_spid_sd1_io = PSRAM_SPID_SD1_IO; psram_io.psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO; diff --git a/components/esp_psram/esp32s2/esp_psram_impl_quad.c b/components/esp_psram/esp32s2/esp_psram_impl_quad.c index 014ae1b1ba..af0bdd39ae 100644 --- a/components/esp_psram/esp32s2/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32s2/esp_psram_impl_quad.c @@ -21,7 +21,7 @@ #include "rom/efuse.h" #include "esp_rom_efuse.h" #include "soc/spi_reg.h" -#include "soc/io_mux_reg.h" +#include "soc/spi_pins.h" #include "esp_private/esp_gpio_reserve.h" static const char* TAG = "quad_psram"; @@ -70,15 +70,15 @@ static const char* TAG = "quad_psram"; // WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines // hardcode the flash pins as well, making this code incompatible with either a setup // that has the flash on non-standard pins or ESP32s with built-in flash. -#define FLASH_CLK_IO SPI_CLK_GPIO_NUM -#define FLASH_CS_IO SPI_CS0_GPIO_NUM +#define FLASH_CLK_IO MSPI_IOMUX_PIN_NUM_CLK +#define FLASH_CS_IO MSPI_IOMUX_PIN_NUM_CS0 // PSRAM clock and cs IO should be configured based on hardware design. -#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM -#define PSRAM_CS_IO SPI_CS1_GPIO_NUM -#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM -#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM -#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM -#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM +#define PSRAM_CLK_IO MSPI_IOMUX_PIN_NUM_CLK +#define PSRAM_CS_IO MSPI_IOMUX_PIN_NUM_CS1 +#define PSRAM_SPIQ_SD0_IO MSPI_IOMUX_PIN_NUM_MISO +#define PSRAM_SPID_SD1_IO MSPI_IOMUX_PIN_NUM_MOSI +#define PSRAM_SPIWP_SD3_IO MSPI_IOMUX_PIN_NUM_WP +#define PSRAM_SPIHD_SD2_IO MSPI_IOMUX_PIN_NUM_HD #define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M #define CS_FLASH_SEL SPI_MEM_CS0_DIS_M diff --git a/components/esp_psram/esp32s3/esp_psram_impl_octal.c b/components/esp_psram/esp32s3/esp_psram_impl_octal.c index 42eeac475d..f2a775ed0e 100644 --- a/components/esp_psram/esp32s3/esp_psram_impl_octal.c +++ b/components/esp_psram/esp32s3/esp_psram_impl_octal.c @@ -32,7 +32,7 @@ #define OCT_PSRAM_ADDR_BITLEN 32 #define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1)) #define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1)) -#define OCT_PSRAM_CS1_IO SPI_CS1_GPIO_NUM +#define OCT_PSRAM_CS1_IO MSPI_IOMUX_PIN_NUM_CS1 #define OCT_PSRAM_VENDOR_ID 0xD #define OCT_PSRAM_CS_SETUP_TIME 3 diff --git a/components/soc/esp32/include/soc/spi_pins.h b/components/soc/esp32/include/soc/spi_pins.h index 9d9424d27c..82d97c64b3 100644 --- a/components/soc/esp32/include/soc/spi_pins.h +++ b/components/soc/esp32/include/soc/spi_pins.h @@ -1,34 +1,27 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once -#define SPI_FUNC_NUM 1 -#define SPI_IOMUX_PIN_NUM_MISO 7 -#define SPI_IOMUX_PIN_NUM_MOSI 8 -#define SPI_IOMUX_PIN_NUM_CLK 6 -#define SPI_IOMUX_PIN_NUM_CS 11 -#define SPI_IOMUX_PIN_NUM_WP 10 -#define SPI_IOMUX_PIN_NUM_HD 9 +// MSPI IOMUX PINs +#define MSPI_FUNC_NUM 1 +#define MSPI_IOMUX_PIN_NUM_CLK 6 +#define MSPI_IOMUX_PIN_NUM_MISO 7 +#define MSPI_IOMUX_PIN_NUM_MOSI 8 +#define MSPI_IOMUX_PIN_NUM_HD 9 +#define MSPI_IOMUX_PIN_NUM_WP 10 +#define MSPI_IOMUX_PIN_NUM_CS0 11 //For D2WD and PICO-D4 chip -#define SPI_D2WD_PIN_NUM_MISO 17 -#define SPI_D2WD_PIN_NUM_MOSI 8 -#define SPI_D2WD_PIN_NUM_CLK 6 -#define SPI_D2WD_PIN_NUM_CS 16 -#define SPI_D2WD_PIN_NUM_WP 7 -#define SPI_D2WD_PIN_NUM_HD 11 +#define SPI_D2WD_PIN_NUM_MISO 17 +#define SPI_D2WD_PIN_NUM_MOSI 8 +#define SPI_D2WD_PIN_NUM_CLK 6 +#define SPI_D2WD_PIN_NUM_CS 16 +#define SPI_D2WD_PIN_NUM_WP 7 +#define SPI_D2WD_PIN_NUM_HD 11 #define SPI2_FUNC_NUM HSPI_FUNC_NUM #define SPI2_IOMUX_PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO diff --git a/components/soc/esp32/spi_periph.c b/components/soc/esp32/spi_periph.c index c36de0266e..934fcde61c 100644 --- a/components/soc/esp32/spi_periph.c +++ b/components/soc/esp32/spi_periph.c @@ -1,21 +1,11 @@ -// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/spi_periph.h" -#define FUNC_SPI 1 //all pins of SPI1, HSPI and VSPI shares this function number - /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc */ @@ -33,16 +23,16 @@ const spi_signal_conn_t spi_periph_signal[3] = { .spihd_in = SPIHD_IN_IDX, .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX, SPICS2_OUT_IDX}, .spics_in = SPICS0_IN_IDX, - .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, - .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, - .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, - .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, - .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, - .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, + .spiclk_iomux_pin = MSPI_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = MSPI_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = MSPI_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = MSPI_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = MSPI_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = MSPI_IOMUX_PIN_NUM_CS0, .irq = ETS_SPI1_INTR_SOURCE, .irq_dma = ETS_SPI1_DMA_INTR_SOURCE, .module = PERIPH_SPI_MODULE, - .func = FUNC_SPI, + .func = MSPI_FUNC_NUM, .hw = &SPI1 }, { .spiclk_out = HSPICLK_OUT_IDX, @@ -66,7 +56,7 @@ const spi_signal_conn_t spi_periph_signal[3] = { .irq = ETS_SPI2_INTR_SOURCE, .irq_dma = ETS_SPI2_DMA_INTR_SOURCE, .module = PERIPH_HSPI_MODULE, - .func = FUNC_SPI, + .func = HSPI_FUNC_NUM, .hw = &SPI2 }, { .spiclk_out = VSPICLK_OUT_IDX, @@ -90,7 +80,7 @@ const spi_signal_conn_t spi_periph_signal[3] = { .irq = ETS_SPI3_INTR_SOURCE, .irq_dma = ETS_SPI3_DMA_INTR_SOURCE, .module = PERIPH_VSPI_MODULE, - .func = FUNC_SPI, + .func = VSPI_FUNC_NUM, .hw = &SPI3 } }; diff --git a/components/soc/esp32c2/include/soc/spi_pins.h b/components/soc/esp32c2/include/soc/spi_pins.h index 0921353333..c72957a1ee 100644 --- a/components/soc/esp32c2/include/soc/spi_pins.h +++ b/components/soc/esp32c2/include/soc/spi_pins.h @@ -1,26 +1,25 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_SPI_PINS_H_ -#define _SOC_SPI_PINS_H_ +#pragma once -#define SPI_FUNC_NUM 0 -#define SPI_IOMUX_PIN_NUM_HD 12 -#define SPI_IOMUX_PIN_NUM_CS 14 -#define SPI_IOMUX_PIN_NUM_MOSI 16 -#define SPI_IOMUX_PIN_NUM_CLK 15 -#define SPI_IOMUX_PIN_NUM_MISO 17 -#define SPI_IOMUX_PIN_NUM_WP 13 +// MSPI IOMUX PINs +#define MSPI_FUNC_NUM 0 +#define MSPI_IOMUX_PIN_NUM_HD 12 +#define MSPI_IOMUX_PIN_NUM_WP 13 +#define MSPI_IOMUX_PIN_NUM_CS0 14 +#define MSPI_IOMUX_PIN_NUM_CLK 15 +#define MSPI_IOMUX_PIN_NUM_MOSI 16 +#define MSPI_IOMUX_PIN_NUM_MISO 17 -#define SPI2_FUNC_NUM 2 -#define SPI2_IOMUX_PIN_NUM_MISO 2 -#define SPI2_IOMUX_PIN_NUM_HD 4 -#define SPI2_IOMUX_PIN_NUM_WP 5 -#define SPI2_IOMUX_PIN_NUM_CLK 6 -#define SPI2_IOMUX_PIN_NUM_MOSI 7 -#define SPI2_IOMUX_PIN_NUM_CS 10 - -#endif +// GPSPI2 IOMUX PINs +#define SPI2_FUNC_NUM 2 +#define SPI2_IOMUX_PIN_NUM_MISO 2 +#define SPI2_IOMUX_PIN_NUM_HD 4 +#define SPI2_IOMUX_PIN_NUM_WP 5 +#define SPI2_IOMUX_PIN_NUM_CLK 6 +#define SPI2_IOMUX_PIN_NUM_MOSI 7 +#define SPI2_IOMUX_PIN_NUM_CS 10 diff --git a/components/soc/esp32c3/include/soc/spi_pins.h b/components/soc/esp32c3/include/soc/spi_pins.h index 665dfabde3..c72957a1ee 100644 --- a/components/soc/esp32c3/include/soc/spi_pins.h +++ b/components/soc/esp32c3/include/soc/spi_pins.h @@ -1,34 +1,25 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +#pragma once -#ifndef _SOC_SPI_PINS_H_ -#define _SOC_SPI_PINS_H_ +// MSPI IOMUX PINs +#define MSPI_FUNC_NUM 0 +#define MSPI_IOMUX_PIN_NUM_HD 12 +#define MSPI_IOMUX_PIN_NUM_WP 13 +#define MSPI_IOMUX_PIN_NUM_CS0 14 +#define MSPI_IOMUX_PIN_NUM_CLK 15 +#define MSPI_IOMUX_PIN_NUM_MOSI 16 +#define MSPI_IOMUX_PIN_NUM_MISO 17 -#define SPI_FUNC_NUM 0 -#define SPI_IOMUX_PIN_NUM_HD 12 -#define SPI_IOMUX_PIN_NUM_CS 14 -#define SPI_IOMUX_PIN_NUM_MOSI 16 -#define SPI_IOMUX_PIN_NUM_CLK 15 -#define SPI_IOMUX_PIN_NUM_MISO 17 -#define SPI_IOMUX_PIN_NUM_WP 13 - -#define SPI2_FUNC_NUM 2 -#define SPI2_IOMUX_PIN_NUM_MISO 2 -#define SPI2_IOMUX_PIN_NUM_HD 4 -#define SPI2_IOMUX_PIN_NUM_WP 5 -#define SPI2_IOMUX_PIN_NUM_CLK 6 -#define SPI2_IOMUX_PIN_NUM_MOSI 7 -#define SPI2_IOMUX_PIN_NUM_CS 10 - -#endif +// GPSPI2 IOMUX PINs +#define SPI2_FUNC_NUM 2 +#define SPI2_IOMUX_PIN_NUM_MISO 2 +#define SPI2_IOMUX_PIN_NUM_HD 4 +#define SPI2_IOMUX_PIN_NUM_WP 5 +#define SPI2_IOMUX_PIN_NUM_CLK 6 +#define SPI2_IOMUX_PIN_NUM_MOSI 7 +#define SPI2_IOMUX_PIN_NUM_CS 10 diff --git a/components/soc/esp32c5/include/soc/spi_pins.h b/components/soc/esp32c5/include/soc/spi_pins.h index 97257258be..2fad17b8cf 100644 --- a/components/soc/esp32c5/include/soc/spi_pins.h +++ b/components/soc/esp32c5/include/soc/spi_pins.h @@ -5,21 +5,22 @@ */ #pragma once -#include "soc/io_mux_reg.h" -// MSPI IO_MUX pin -#define SPI_FUNC_NUM 0 -#define SPI_IOMUX_PIN_NUM_CS SPI_CS0_GPIO_NUM -#define SPI_IOMUX_PIN_NUM_CLK SPI_CLK_GPIO_NUM -#define SPI_IOMUX_PIN_NUM_MOSI SPI_D_GPIO_NUM -#define SPI_IOMUX_PIN_NUM_MISO SPI_Q_GPIO_NUM -#define SPI_IOMUX_PIN_NUM_WP SPI_WP_GPIO_NUM -#define SPI_IOMUX_PIN_NUM_HD SPI_HD_GPIO_NUM +// MSPI IOMUX PINs +#define MSPI_FUNC_NUM 0 +#define MSPI_IOMUX_PIN_NUM_HD 20 +#define MSPI_IOMUX_PIN_NUM_WP 18 +#define MSPI_IOMUX_PIN_NUM_CS0 16 +#define MSPI_IOMUX_PIN_NUM_CLK 21 +#define MSPI_IOMUX_PIN_NUM_MOSI 22 +#define MSPI_IOMUX_PIN_NUM_MISO 17 +#define MSPI_IOMUX_PIN_NUM_CS1 15 -#define SPI2_FUNC_NUM 2 -#define SPI2_IOMUX_PIN_NUM_MISO 2 -#define SPI2_IOMUX_PIN_NUM_HD 4 -#define SPI2_IOMUX_PIN_NUM_WP 5 -#define SPI2_IOMUX_PIN_NUM_CLK 6 -#define SPI2_IOMUX_PIN_NUM_MOSI 7 -#define SPI2_IOMUX_PIN_NUM_CS 10 +// GPSPI2 IOMUX PINs +#define SPI2_FUNC_NUM 2 +#define SPI2_IOMUX_PIN_NUM_MISO 2 +#define SPI2_IOMUX_PIN_NUM_HD 4 +#define SPI2_IOMUX_PIN_NUM_WP 5 +#define SPI2_IOMUX_PIN_NUM_CLK 6 +#define SPI2_IOMUX_PIN_NUM_MOSI 7 +#define SPI2_IOMUX_PIN_NUM_CS 10 diff --git a/components/soc/esp32c6/include/soc/spi_pins.h b/components/soc/esp32c6/include/soc/spi_pins.h index 2cb3b76fbf..13e5ed58be 100644 --- a/components/soc/esp32c6/include/soc/spi_pins.h +++ b/components/soc/esp32c6/include/soc/spi_pins.h @@ -1,26 +1,25 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_SPI_PINS_H_ -#define _SOC_SPI_PINS_H_ +#pragma once -#define SPI_FUNC_NUM 0 -#define SPI_IOMUX_PIN_NUM_CS 24 -#define SPI_IOMUX_PIN_NUM_CLK 29 -#define SPI_IOMUX_PIN_NUM_MOSI 30 -#define SPI_IOMUX_PIN_NUM_MISO 25 -#define SPI_IOMUX_PIN_NUM_WP 26 -#define SPI_IOMUX_PIN_NUM_HD 28 +// MSPI IOMUX PINs +#define MSPI_FUNC_NUM 0 +#define MSPI_IOMUX_PIN_NUM_HD 28 +#define MSPI_IOMUX_PIN_NUM_WP 26 +#define MSPI_IOMUX_PIN_NUM_CS0 24 +#define MSPI_IOMUX_PIN_NUM_CLK 29 +#define MSPI_IOMUX_PIN_NUM_MOSI 30 +#define MSPI_IOMUX_PIN_NUM_MISO 25 -#define SPI2_FUNC_NUM 2 -#define SPI2_IOMUX_PIN_NUM_MISO 2 -#define SPI2_IOMUX_PIN_NUM_HD 4 -#define SPI2_IOMUX_PIN_NUM_WP 5 -#define SPI2_IOMUX_PIN_NUM_CLK 6 -#define SPI2_IOMUX_PIN_NUM_MOSI 7 -#define SPI2_IOMUX_PIN_NUM_CS 16 - -#endif +// GPSPI2 IOMUX PINs +#define SPI2_FUNC_NUM 2 +#define SPI2_IOMUX_PIN_NUM_MISO 2 +#define SPI2_IOMUX_PIN_NUM_HD 4 +#define SPI2_IOMUX_PIN_NUM_WP 5 +#define SPI2_IOMUX_PIN_NUM_CLK 6 +#define SPI2_IOMUX_PIN_NUM_MOSI 7 +#define SPI2_IOMUX_PIN_NUM_CS 16 diff --git a/components/soc/esp32c61/include/soc/io_mux_reg.h b/components/soc/esp32c61/include/soc/io_mux_reg.h index ef551d6861..11a3520c6b 100644 --- a/components/soc/esp32c61/include/soc/io_mux_reg.h +++ b/components/soc/esp32c61/include/soc/io_mux_reg.h @@ -124,14 +124,6 @@ extern "C" { #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) -#define SPI_HD_GPIO_NUM 19 -#define SPI_WP_GPIO_NUM 17 -#define SPI_CS0_GPIO_NUM 15 -#define SPI_CLK_GPIO_NUM 20 -#define SPI_D_GPIO_NUM 21 -#define SPI_Q_GPIO_NUM 16 -#define SPI_CS1_GPIO_NUM 14 - #define USB_INT_PHY0_DM_GPIO_NUM 12 #define USB_INT_PHY0_DP_GPIO_NUM 13 diff --git a/components/soc/esp32c61/include/soc/spi_pins.h b/components/soc/esp32c61/include/soc/spi_pins.h index 84755266ce..98b9c18ed7 100644 --- a/components/soc/esp32c61/include/soc/spi_pins.h +++ b/components/soc/esp32c61/include/soc/spi_pins.h @@ -4,13 +4,17 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define SPI_FUNC_NUM 0 -#define SPI_IOMUX_PIN_NUM_CS 24 -#define SPI_IOMUX_PIN_NUM_CLK 29 -#define SPI_IOMUX_PIN_NUM_MOSI 30 -#define SPI_IOMUX_PIN_NUM_MISO 25 -#define SPI_IOMUX_PIN_NUM_WP 26 -#define SPI_IOMUX_PIN_NUM_HD 28 +#pragma once + +// MSPI IOMUX PINs +#define MSPI_FUNC_NUM 0 +#define MSPI_IOMUX_PIN_NUM_CS1 14 +#define MSPI_IOMUX_PIN_NUM_CS0 15 +#define MSPI_IOMUX_PIN_NUM_CLK 20 +#define MSPI_IOMUX_PIN_NUM_MOSI 21 +#define MSPI_IOMUX_PIN_NUM_MISO 16 +#define MSPI_IOMUX_PIN_NUM_WP 17 +#define MSPI_IOMUX_PIN_NUM_HD 19 // GPSPI2 IOMUX PINs #define SPI2_FUNC_NUM 2 diff --git a/components/soc/esp32h2/include/soc/spi_pins.h b/components/soc/esp32h2/include/soc/spi_pins.h index 128a330054..2753a00662 100644 --- a/components/soc/esp32h2/include/soc/spi_pins.h +++ b/components/soc/esp32h2/include/soc/spi_pins.h @@ -1,26 +1,25 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_SPI_PINS_H_ -#define _SOC_SPI_PINS_H_ +#pragma once -#define SPI_FUNC_NUM 0 -#define SPI_IOMUX_PIN_NUM_HD 18 -#define SPI_IOMUX_PIN_NUM_CS 15 -#define SPI_IOMUX_PIN_NUM_MOSI 20 -#define SPI_IOMUX_PIN_NUM_CLK 19 -#define SPI_IOMUX_PIN_NUM_MISO 16 -#define SPI_IOMUX_PIN_NUM_WP 17 +// MSPI IOMUX PINs +#define MSPI_FUNC_NUM 0 +#define MSPI_IOMUX_PIN_NUM_HD 18 +#define MSPI_IOMUX_PIN_NUM_WP 17 +#define MSPI_IOMUX_PIN_NUM_CS0 15 +#define MSPI_IOMUX_PIN_NUM_CLK 19 +#define MSPI_IOMUX_PIN_NUM_MOSI 20 +#define MSPI_IOMUX_PIN_NUM_MISO 16 -#define SPI2_FUNC_NUM 2 -#define SPI2_IOMUX_PIN_NUM_MISO 0 -#define SPI2_IOMUX_PIN_NUM_HD 3 -#define SPI2_IOMUX_PIN_NUM_WP 2 -#define SPI2_IOMUX_PIN_NUM_CLK 4 -#define SPI2_IOMUX_PIN_NUM_MOSI 5 -#define SPI2_IOMUX_PIN_NUM_CS 1 - -#endif +// GPSPI2 IOMUX PINs +#define SPI2_FUNC_NUM 2 +#define SPI2_IOMUX_PIN_NUM_MISO 0 +#define SPI2_IOMUX_PIN_NUM_HD 3 +#define SPI2_IOMUX_PIN_NUM_WP 2 +#define SPI2_IOMUX_PIN_NUM_CLK 4 +#define SPI2_IOMUX_PIN_NUM_MOSI 5 +#define SPI2_IOMUX_PIN_NUM_CS 1 diff --git a/components/soc/esp32p4/include/soc/spi_pins.h b/components/soc/esp32p4/include/soc/spi_pins.h index 48b98b0169..7fff001433 100644 --- a/components/soc/esp32p4/include/soc/spi_pins.h +++ b/components/soc/esp32p4/include/soc/spi_pins.h @@ -1,11 +1,28 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +// MSPI IOMUX PINs +// On P4, SPI pins defined here are all wrong. these pins are individual pins, don't use normal GPIO pins anymore. +// Please check iomux_mspi_pin_struct/reg.h +#define GPIO_NUM_INVALID -1 +#define MSPI_IOMUX_PIN_NUM_CS1 GPIO_NUM_INVALID +#define MSPI_IOMUX_PIN_NUM_HD GPIO_NUM_INVALID +#define MSPI_IOMUX_PIN_NUM_WP GPIO_NUM_INVALID +#define MSPI_IOMUX_PIN_NUM_CS0 GPIO_NUM_INVALID +#define MSPI_IOMUX_PIN_NUM_CLK GPIO_NUM_INVALID +#define MSPI_IOMUX_PIN_NUM_MISO GPIO_NUM_INVALID +#define MSPI_IOMUX_PIN_NUM_MOSI GPIO_NUM_INVALID +#define MSPI_IOMUX_PIN_NUM_D4 GPIO_NUM_INVALID +#define MSPI_IOMUX_PIN_NUM_D5 GPIO_NUM_INVALID +#define MSPI_IOMUX_PIN_NUM_D6 GPIO_NUM_INVALID +#define MSPI_IOMUX_PIN_NUM_D7 GPIO_NUM_INVALID +#define MSPI_IOMUX_PIN_NUM_DQS GPIO_NUM_INVALID + // Normal IOMUX pins #define SPI2_FUNC_NUM 3 #define SPI2_IOMUX_PIN_NUM_HD 6 diff --git a/components/soc/esp32s2/include/soc/spi_pins.h b/components/soc/esp32s2/include/soc/spi_pins.h index 81ea5f0d2a..6a465e6ffd 100644 --- a/components/soc/esp32s2/include/soc/spi_pins.h +++ b/components/soc/esp32s2/include/soc/spi_pins.h @@ -1,37 +1,36 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once -#define SPI_FUNC_NUM 0 -#define SPI_IOMUX_PIN_NUM_HD 27 -#define SPI_IOMUX_PIN_NUM_CS 29 -#define SPI_IOMUX_PIN_NUM_MOSI 32 -#define SPI_IOMUX_PIN_NUM_CLK 30 -#define SPI_IOMUX_PIN_NUM_MISO 31 -#define SPI_IOMUX_PIN_NUM_WP 28 +// MSPI IOMUX PINs +#define MSPI_FUNC_NUM 0 +#define MSPI_IOMUX_PIN_NUM_CS1 26 +#define MSPI_IOMUX_PIN_NUM_HD 27 +#define MSPI_IOMUX_PIN_NUM_WP 28 +#define MSPI_IOMUX_PIN_NUM_CS0 29 +#define MSPI_IOMUX_PIN_NUM_CLK 30 +#define MSPI_IOMUX_PIN_NUM_MISO 31 +#define MSPI_IOMUX_PIN_NUM_MOSI 32 +#define MSPI_IOMUX_PIN_NUM_D4 33 +#define MSPI_IOMUX_PIN_NUM_D5 34 +#define MSPI_IOMUX_PIN_NUM_D6 35 +#define MSPI_IOMUX_PIN_NUM_D7 36 +#define MSPI_IOMUX_PIN_NUM_DQS 37 // There are 2 sets of GPIO pins which could be routed to FSPICS0, FSPICLK, FSPID, FSPIQ, FSPIHD, FSPIWP. // However, there is only one set of GPIO pins which could be routed to FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7. // As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows. -#define SPI2_FUNC_NUM 4 -#define SPI2_IOMUX_PIN_NUM_HD 9 -#define SPI2_IOMUX_PIN_NUM_CS 10 -#define SPI2_IOMUX_PIN_NUM_MOSI 11 -#define SPI2_IOMUX_PIN_NUM_CLK 12 -#define SPI2_IOMUX_PIN_NUM_MISO 13 -#define SPI2_IOMUX_PIN_NUM_WP 14 +#define SPI2_FUNC_NUM 4 +#define SPI2_IOMUX_PIN_NUM_HD 9 +#define SPI2_IOMUX_PIN_NUM_CS 10 +#define SPI2_IOMUX_PIN_NUM_MOSI 11 +#define SPI2_IOMUX_PIN_NUM_CLK 12 +#define SPI2_IOMUX_PIN_NUM_MISO 13 +#define SPI2_IOMUX_PIN_NUM_WP 14 // When using Octal SPI, we make use of SPI2_FUNC_NUM_OCT to route them as follows. #define SPI2_FUNC_NUM_OCT 2 diff --git a/components/soc/esp32s2/spi_periph.c b/components/soc/esp32s2/spi_periph.c index 7bf01d0e32..2dfcdfb20b 100644 --- a/components/soc/esp32s2/spi_periph.c +++ b/components/soc/esp32s2/spi_periph.c @@ -1,10 +1,9 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include #include "soc/spi_periph.h" /* @@ -25,17 +24,17 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .spihd_in = SPIHD_IN_IDX, .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */ .spics_in = 0,/* SPI cs is not an input signal*/ - .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, - .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, - .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, - .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, - .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, - .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, + .spiclk_iomux_pin = MSPI_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = MSPI_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = MSPI_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = MSPI_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = MSPI_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = MSPI_IOMUX_PIN_NUM_CS0, .irq = ETS_SPI1_INTR_SOURCE, .irq_dma = -1, .module = PERIPH_SPI_MODULE, .hw = (spi_dev_t *) &SPIMEM1, - .func = SPI_FUNC_NUM, + .func = MSPI_FUNC_NUM, }, { .spiclk_out = FSPICLK_OUT_MUX_IDX, diff --git a/components/soc/esp32s3/include/soc/spi_pins.h b/components/soc/esp32s3/include/soc/spi_pins.h index 05d338085c..5410ed5ad2 100644 --- a/components/soc/esp32s3/include/soc/spi_pins.h +++ b/components/soc/esp32s3/include/soc/spi_pins.h @@ -1,37 +1,36 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once -#define SPI_FUNC_NUM 0 -#define SPI_IOMUX_PIN_NUM_HD 27 -#define SPI_IOMUX_PIN_NUM_CS 29 -#define SPI_IOMUX_PIN_NUM_MOSI 32 -#define SPI_IOMUX_PIN_NUM_CLK 30 -#define SPI_IOMUX_PIN_NUM_MISO 31 -#define SPI_IOMUX_PIN_NUM_WP 28 +// MSPI IOMUX PINs +#define MSPI_FUNC_NUM 0 +#define MSPI_IOMUX_PIN_NUM_CS1 26 +#define MSPI_IOMUX_PIN_NUM_HD 27 +#define MSPI_IOMUX_PIN_NUM_WP 28 +#define MSPI_IOMUX_PIN_NUM_CS0 29 +#define MSPI_IOMUX_PIN_NUM_CLK 30 +#define MSPI_IOMUX_PIN_NUM_MISO 31 +#define MSPI_IOMUX_PIN_NUM_MOSI 32 +#define MSPI_IOMUX_PIN_NUM_D4 33 +#define MSPI_IOMUX_PIN_NUM_D5 34 +#define MSPI_IOMUX_PIN_NUM_D6 35 +#define MSPI_IOMUX_PIN_NUM_D7 36 +#define MSPI_IOMUX_PIN_NUM_DQS 37 // There are 2 sets of GPIO pins which could be routed to FSPICS0, FSPICLK, FSPID, FSPIQ, FSPIHD, FSPIWP. // However, there is only one set of GPIO pins which could be routed to FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7. // As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows. -#define SPI2_FUNC_NUM 4 -#define SPI2_IOMUX_PIN_NUM_HD 9 -#define SPI2_IOMUX_PIN_NUM_CS 10 -#define SPI2_IOMUX_PIN_NUM_MOSI 11 -#define SPI2_IOMUX_PIN_NUM_CLK 12 -#define SPI2_IOMUX_PIN_NUM_MISO 13 -#define SPI2_IOMUX_PIN_NUM_WP 14 +#define SPI2_FUNC_NUM 4 +#define SPI2_IOMUX_PIN_NUM_HD 9 +#define SPI2_IOMUX_PIN_NUM_CS 10 +#define SPI2_IOMUX_PIN_NUM_MOSI 11 +#define SPI2_IOMUX_PIN_NUM_CLK 12 +#define SPI2_IOMUX_PIN_NUM_MISO 13 +#define SPI2_IOMUX_PIN_NUM_WP 14 // When using Octal SPI, we make use of SPI2_FUNC_NUM_OCT to route them as follows. #define SPI2_FUNC_NUM_OCT 2 diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c index 7a41bdf5a7..45c060f7e4 100644 --- a/components/spi_flash/flash_ops.c +++ b/components/spi_flash/flash_ops.c @@ -157,8 +157,12 @@ void IRAM_ATTR esp_mspi_pin_init(void) void esp_mspi_pin_reserve(void) { uint64_t reserve_pin_mask = 0; + uint8_t mspi_io; for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) { - reserve_pin_mask |= BIT64(esp_mspi_get_io(i)); + mspi_io = esp_mspi_get_io(i); + if (mspi_io < 64) { // 'reserve_pin_mask' have 64 bits length + reserve_pin_mask |= BIT64(mspi_io); + } } esp_gpio_reserve(reserve_pin_mask); } @@ -207,18 +211,18 @@ void IRAM_ATTR spi_flash_set_vendor_required_regs(void) #endif static const uint8_t s_mspi_io_num_default[] = { - SPI_CLK_GPIO_NUM, - SPI_Q_GPIO_NUM, - SPI_D_GPIO_NUM, - SPI_CS0_GPIO_NUM, - SPI_HD_GPIO_NUM, - SPI_WP_GPIO_NUM, + MSPI_IOMUX_PIN_NUM_CLK, + MSPI_IOMUX_PIN_NUM_MISO, + MSPI_IOMUX_PIN_NUM_MOSI, + MSPI_IOMUX_PIN_NUM_CS0, + MSPI_IOMUX_PIN_NUM_HD, + MSPI_IOMUX_PIN_NUM_WP, #if SOC_SPI_MEM_SUPPORT_OPI_MODE - SPI_DQS_GPIO_NUM, - SPI_D4_GPIO_NUM, - SPI_D5_GPIO_NUM, - SPI_D6_GPIO_NUM, - SPI_D7_GPIO_NUM + MSPI_IOMUX_PIN_NUM_DQS, + MSPI_IOMUX_PIN_NUM_D4, + MSPI_IOMUX_PIN_NUM_D5, + MSPI_IOMUX_PIN_NUM_D6, + MSPI_IOMUX_PIN_NUM_D7 #endif // SOC_SPI_MEM_SUPPORT_OPI_MODE }; diff --git a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c index 033976c7e6..b9e2071244 100644 --- a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c +++ b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c @@ -33,8 +33,6 @@ #include "esp_private/spi_flash_os.h" #include "ccomp_timer.h" -#define FUNC_SPI 1 - static uint8_t sector_buf[4096]; static void get_chip_host(esp_flash_t* chip, spi_host_device_t* out_host_id, int* out_cs_id) diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index b8632275cf..a2537c7741 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -544,7 +544,6 @@ components/soc/esp32/include/soc/slc_reg.h components/soc/esp32/include/soc/slc_struct.h components/soc/esp32/include/soc/soc_pins.h components/soc/esp32/include/soc/soc_ulp.h -components/soc/esp32/include/soc/spi_pins.h components/soc/esp32/include/soc/syscon_reg.h components/soc/esp32/include/soc/syscon_struct.h components/soc/esp32/include/soc/touch_sensor_channel.h @@ -555,7 +554,6 @@ components/soc/esp32/include/soc/uhci_reg.h components/soc/esp32/include/soc/uhci_struct.h components/soc/esp32/include/soc/wdev_reg.h components/soc/esp32/ledc_periph.c -components/soc/esp32/spi_periph.c components/soc/esp32c3/include/soc/apb_saradc_reg.h components/soc/esp32c3/include/soc/assist_debug_reg.h components/soc/esp32c3/include/soc/bb_reg.h @@ -574,7 +572,6 @@ components/soc/esp32c3/include/soc/sensitive_reg.h components/soc/esp32c3/include/soc/sensitive_struct.h components/soc/esp32c3/include/soc/soc_pins.h components/soc/esp32c3/include/soc/spi_mem_reg.h -components/soc/esp32c3/include/soc/spi_pins.h components/soc/esp32c3/include/soc/systimer_reg.h components/soc/esp32c3/include/soc/systimer_struct.h components/soc/esp32c3/include/soc/uart_pins.h @@ -608,7 +605,6 @@ components/soc/esp32s2/include/soc/rtc_io_reg.h components/soc/esp32s2/include/soc/sens_reg.h components/soc/esp32s2/include/soc/sensitive_reg.h components/soc/esp32s2/include/soc/soc_ulp.h -components/soc/esp32s2/include/soc/spi_pins.h components/soc/esp32s2/include/soc/systimer_reg.h components/soc/esp32s2/include/soc/systimer_struct.h components/soc/esp32s2/include/soc/touch_sensor_channel.h @@ -658,7 +654,6 @@ components/soc/esp32s3/include/soc/sensitive_struct.h components/soc/esp32s3/include/soc/soc_ulp.h components/soc/esp32s3/include/soc/spi_mem_reg.h components/soc/esp32s3/include/soc/spi_mem_struct.h -components/soc/esp32s3/include/soc/spi_pins.h components/soc/esp32s3/include/soc/spi_reg.h components/soc/esp32s3/include/soc/spi_struct.h components/soc/esp32s3/include/soc/syscon_struct.h