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spi_flash: enable spi flash cache test on c6 h2

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This commit is contained in:
Jiang Guang Ming 2023-03-02 21:21:06 -08:00
parent 698752684e
commit 3556fe9326
3 changed files with 2 additions and 9 deletions
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3
components/esp_rom/esp32c6/ld/esp32c6.rom.spiflash.ld
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -21,7 +21,6 @@
spi_flash_disable_cache = 0x400001f0; spi_flash_disable_cache = 0x400001f0;
spi_flash_restore_cache = 0x400001f4; spi_flash_restore_cache = 0x400001f4;
spi_flash_cache_enabled = 0x400001f8; spi_flash_cache_enabled = 0x400001f8;
spi_flash_enable_cache = 0x400001fc;
esp_enable_cache_flash_wrap = 0x40000200; esp_enable_cache_flash_wrap = 0x40000200;

3
components/esp_rom/esp32h2/ld/esp32h2.rom.spiflash.ld
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -21,7 +21,6 @@
spi_flash_disable_cache = 0x400001e8; spi_flash_disable_cache = 0x400001e8;
spi_flash_restore_cache = 0x400001ec; spi_flash_restore_cache = 0x400001ec;
spi_flash_cache_enabled = 0x400001f0; spi_flash_cache_enabled = 0x400001f0;
spi_flash_enable_cache = 0x400001f4;
esp_enable_cache_flash_wrap = 0x400001f8; esp_enable_cache_flash_wrap = 0x400001f8;

5
components/spi_flash/test/test_cache_disabled.c
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@ -62,10 +62,6 @@ TEST_CASE("spi_flash_cache_enabled() works on both CPUs", "[spi_flash][esp_flash
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
#define C6_H2_ROM_IMPL (CONFIG_SPI_FLASH_ROM_IMPL && (CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2))
#if !C6_H2_ROM_IMPL
//TODO: IDF-6931
// This needs to sufficiently large array, otherwise it may end up in // This needs to sufficiently large array, otherwise it may end up in
// DRAM (e.g. size <= 8 bytes && ARCH == RISCV) // DRAM (e.g. size <= 8 bytes && ARCH == RISCV)
@ -104,7 +100,6 @@ TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][reset="
xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0); xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0);
vTaskDelay(1000/portTICK_PERIOD_MS); vTaskDelay(1000/portTICK_PERIOD_MS);
} }
#endif //#if !C6_H2_ROM_IMPL
#ifndef CONFIG_FREERTOS_UNICORE #ifndef CONFIG_FREERTOS_UNICORE