mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
efuse(c6): Adds adc calib efuses
This commit is contained in:
KonstantinKondrashov
laokaiyao
parent
caa044c289
commit
3550a2d185
@ -9,7 +9,7 @@
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table ab312e31f6976fdf923a9809093323fd
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// md5_digest_table 7bd417676a69ed11f4908b6146efeaeb
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -227,6 +227,74 @@ static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
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};
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static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB,
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};
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static const esp_efuse_desc_t WR_DIS_OCODE[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN1[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN1,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN2[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN2,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN3[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN3,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN0[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN0,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN1[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN1,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN2[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN2,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN3[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN3,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6,
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};
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static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
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{EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
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};
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@ -520,6 +588,74 @@ static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
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{EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID,
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};
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static const esp_efuse_desc_t TEMP_CALIB[] = {
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{EFUSE_BLK2, 128, 9}, // [] Temperature calibration data,
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};
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static const esp_efuse_desc_t OCODE[] = {
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{EFUSE_BLK2, 137, 8}, // [] ADC OCode,
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};
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static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = {
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{EFUSE_BLK2, 145, 10}, // [] ADC1 init code at atten0,
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};
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static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = {
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{EFUSE_BLK2, 155, 10}, // [] ADC1 init code at atten1,
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};
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static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = {
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{EFUSE_BLK2, 165, 10}, // [] ADC1 init code at atten2,
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};
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static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = {
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{EFUSE_BLK2, 175, 10}, // [] ADC1 init code at atten3,
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};
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static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = {
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{EFUSE_BLK2, 185, 10}, // [] ADC1 calibration voltage at atten0,
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};
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static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = {
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{EFUSE_BLK2, 195, 10}, // [] ADC1 calibration voltage at atten1,
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};
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static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = {
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{EFUSE_BLK2, 205, 10}, // [] ADC1 calibration voltage at atten2,
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};
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static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = {
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{EFUSE_BLK2, 215, 10}, // [] ADC1 calibration voltage at atten3,
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};
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static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH0[] = {
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{EFUSE_BLK2, 225, 4}, // [] ADC1 init code at atten0 ch0,
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};
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static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH1[] = {
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{EFUSE_BLK2, 229, 4}, // [] ADC1 init code at atten0 ch1,
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};
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static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH2[] = {
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{EFUSE_BLK2, 233, 4}, // [] ADC1 init code at atten0 ch2,
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};
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static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH3[] = {
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{EFUSE_BLK2, 237, 4}, // [] ADC1 init code at atten0 ch3,
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};
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static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH4[] = {
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{EFUSE_BLK2, 241, 4}, // [] ADC1 init code at atten0 ch4,
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};
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static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH5[] = {
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{EFUSE_BLK2, 245, 4}, // [] ADC1 init code at atten0 ch5,
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};
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static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH6[] = {
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{EFUSE_BLK2, 249, 4}, // [] ADC1 init code at atten0 ch6,
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};
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static const esp_efuse_desc_t USER_DATA[] = {
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{EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data,
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};
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@ -825,6 +961,91 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = {
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&WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = {
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&WR_DIS_OCODE[0], // [] wr_dis of OCODE
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[] = {
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&WR_DIS_ADC1_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[] = {
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&WR_DIS_ADC1_INIT_CODE_ATTEN1[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[] = {
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&WR_DIS_ADC1_INIT_CODE_ATTEN2[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[] = {
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&WR_DIS_ADC1_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[] = {
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&WR_DIS_ADC1_CAL_VOL_ATTEN0[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[] = {
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&WR_DIS_ADC1_CAL_VOL_ATTEN1[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[] = {
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&WR_DIS_ADC1_CAL_VOL_ATTEN2[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[] = {
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&WR_DIS_ADC1_CAL_VOL_ATTEN3[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[] = {
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&WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[] = {
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&WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[] = {
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&WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[] = {
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&WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[] = {
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&WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[] = {
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&WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[] = {
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&WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
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&WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
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NULL
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@ -1190,6 +1411,91 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = {
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&TEMP_CALIB[0], // [] Temperature calibration data
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
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&OCODE[0], // [] ADC OCode
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = {
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&ADC1_INIT_CODE_ATTEN0[0], // [] ADC1 init code at atten0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = {
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&ADC1_INIT_CODE_ATTEN1[0], // [] ADC1 init code at atten1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = {
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&ADC1_INIT_CODE_ATTEN2[0], // [] ADC1 init code at atten2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = {
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&ADC1_INIT_CODE_ATTEN3[0], // [] ADC1 init code at atten3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = {
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&ADC1_CAL_VOL_ATTEN0[0], // [] ADC1 calibration voltage at atten0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = {
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&ADC1_CAL_VOL_ATTEN1[0], // [] ADC1 calibration voltage at atten1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = {
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&ADC1_CAL_VOL_ATTEN2[0], // [] ADC1 calibration voltage at atten2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = {
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&ADC1_CAL_VOL_ATTEN3[0], // [] ADC1 calibration voltage at atten3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0[] = {
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&ADC1_INIT_CODE_ATTEN0_CH0[0], // [] ADC1 init code at atten0 ch0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1[] = {
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&ADC1_INIT_CODE_ATTEN0_CH1[0], // [] ADC1 init code at atten0 ch1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2[] = {
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&ADC1_INIT_CODE_ATTEN0_CH2[0], // [] ADC1 init code at atten0 ch2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3[] = {
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&ADC1_INIT_CODE_ATTEN0_CH3[0], // [] ADC1 init code at atten0 ch3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4[] = {
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&ADC1_INIT_CODE_ATTEN0_CH4[0], // [] ADC1 init code at atten0 ch4
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5[] = {
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&ADC1_INIT_CODE_ATTEN0_CH5[0], // [] ADC1 init code at atten0 ch5
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6[] = {
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&ADC1_INIT_CODE_ATTEN0_CH6[0], // [] ADC1 init code at atten0 ch6
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
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&USER_DATA[0], // [BLOCK_USR_DATA] User data
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NULL
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@ -9,7 +9,7 @@
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# this will generate new source files, next rebuild all the sources.
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# !!!!!!!!!!! #
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# This file was generated by regtools.py based on the efuses.yaml file with the version: 0a6c6206f42d0f0b7aeaceb8cecf1fc2
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# This file was generated by regtools.py based on the efuses.yaml file with the version: 709e8ea096e8a03a10006d40d5451a49
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WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
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WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
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@ -64,6 +64,23 @@ WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis
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WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
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WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
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WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
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WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB
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WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
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WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0
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WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1
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WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2
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WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
@ -141,6 +158,23 @@ FLASH_CAP, EFUSE_BLK1, 128, 3, []
|
||||
FLASH_TEMP, EFUSE_BLK1, 131, 2, []
|
||||
FLASH_VENDOR, EFUSE_BLK1, 133, 3, []
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
TEMP_CALIB, EFUSE_BLK2, 128, 9, [] Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 145, 10, [] ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 155, 10, [] ADC1 init code at atten1
|
||||
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 165, 10, [] ADC1 init code at atten2
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 175, 10, [] ADC1 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 185, 10, [] ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 195, 10, [] ADC1 calibration voltage at atten1
|
||||
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 205, 10, [] ADC1 calibration voltage at atten2
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 215, 10, [] ADC1 calibration voltage at atten3
|
||||
ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK2, 225, 4, [] ADC1 init code at atten0 ch0
|
||||
ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK2, 229, 4, [] ADC1 init code at atten0 ch1
|
||||
ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK2, 233, 4, [] ADC1 init code at atten0 ch2
|
||||
ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK2, 237, 4, [] ADC1 init code at atten0 ch3
|
||||
ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK2, 241, 4, [] ADC1 init code at atten0 ch4
|
||||
ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK2, 245, 4, [] ADC1 init code at atten0 ch5
|
||||
ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK2, 249, 4, [] ADC1 init code at atten0 ch6
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table ab312e31f6976fdf923a9809093323fd
|
||||
// md5_digest_table 7bd417676a69ed11f4908b6146efeaeb
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -80,6 +80,23 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
@ -179,6 +196,23 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
|
||||
@ -799,49 +799,168 @@ extern "C" {
|
||||
* Register $n of BLOCK2 (system).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
|
||||
/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the fourth 32 bits of the first part of system data.
|
||||
/** EFUSE_TEMP_CALIB : R; bitpos: [8:0]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
|
||||
#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_4_S 0
|
||||
#define EFUSE_TEMP_CALIB 0x000001FFU
|
||||
#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
|
||||
#define EFUSE_TEMP_CALIB_V 0x000001FFU
|
||||
#define EFUSE_TEMP_CALIB_S 0
|
||||
/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
|
||||
* ADC OCode
|
||||
*/
|
||||
#define EFUSE_OCODE 0x000000FFU
|
||||
#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S)
|
||||
#define EFUSE_OCODE_V 0x000000FFU
|
||||
#define EFUSE_OCODE_S 9
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
|
||||
* ADC1 init code at atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0 0x000003FFU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_V 0x000003FFU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_S 17
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
|
||||
* ADC1 init code at atten1
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN1 0x0000001FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN1_V 0x0000001FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN1_S 27
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA5_REG register
|
||||
* Register $n of BLOCK2 (system).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
|
||||
/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the fifth 32 bits of the first part of system data.
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
|
||||
* ADC1 init code at atten1
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
|
||||
#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_S 0
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN1_1 0x0000001FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V 0x0000001FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S 0
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
|
||||
* ADC1 init code at atten2
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN2_M (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN2_S 5
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
|
||||
* ADC1 init code at atten3
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN3 0x000003FFU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN3_M (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN3_V 0x000003FFU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN3_S 15
|
||||
/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:25]; default: 0;
|
||||
* ADC1 calibration voltage at atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0 0x0000007FU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_M (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S)
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_V 0x0000007FU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_S 25
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA6_REG register
|
||||
* Register $n of BLOCK2 (system).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
|
||||
/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the sixth 32 bits of the first part of system data.
|
||||
/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* ADC1 calibration voltage at atten0
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
|
||||
#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_S 0
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_1 0x00000007U
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S)
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V 0x00000007U
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S 0
|
||||
/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [12:3]; default: 0;
|
||||
* ADC1 calibration voltage at atten1
|
||||
*/
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN1 0x000003FFU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN1_M (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S)
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN1_V 0x000003FFU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN1_S 3
|
||||
/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [22:13]; default: 0;
|
||||
* ADC1 calibration voltage at atten2
|
||||
*/
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN2_M (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S)
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN2_S 13
|
||||
/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [31:23]; default: 0;
|
||||
* ADC1 calibration voltage at atten3
|
||||
*/
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3 0x000001FFU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3_M (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S)
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3_V 0x000001FFU
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3_S 23
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA7_REG register
|
||||
* Register $n of BLOCK2 (system).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
|
||||
/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the seventh 32 bits of the first part of system data.
|
||||
/** EFUSE_ADC1_CAL_VOL_ATTEN3_1 : R; bitpos: [0]; default: 0;
|
||||
* ADC1 calibration voltage at atten3
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
|
||||
#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_S 0
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3_1 (BIT(0))
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_M (EFUSE_ADC1_CAL_VOL_ATTEN3_1_V << EFUSE_ADC1_CAL_VOL_ATTEN3_1_S)
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_V 0x00000001U
|
||||
#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_S 0
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH0 : R; bitpos: [4:1]; default: 0;
|
||||
* ADC1 init code at atten0 ch0
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_V 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_S 1
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH1 : R; bitpos: [8:5]; default: 0;
|
||||
* ADC1 init code at atten0 ch1
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_V 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_S 5
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH2 : R; bitpos: [12:9]; default: 0;
|
||||
* ADC1 init code at atten0 ch2
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_V 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_S 9
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH3 : R; bitpos: [16:13]; default: 0;
|
||||
* ADC1 init code at atten0 ch3
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_V 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_S 13
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH4 : R; bitpos: [20:17]; default: 0;
|
||||
* ADC1 init code at atten0 ch4
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_V 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_S 17
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH5 : R; bitpos: [24:21]; default: 0;
|
||||
* ADC1 init code at atten0 ch5
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_V 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_S 21
|
||||
/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH6 : R; bitpos: [28:25]; default: 0;
|
||||
* ADC1 init code at atten0 ch6
|
||||
*/
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_S)
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_V 0x0000000FU
|
||||
#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_S 25
|
||||
/** EFUSE_RESERVED_2_253 : R; bitpos: [31:29]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_253 0x00000007U
|
||||
#define EFUSE_RESERVED_2_253_M (EFUSE_RESERVED_2_253_V << EFUSE_RESERVED_2_253_S)
|
||||
#define EFUSE_RESERVED_2_253_V 0x00000007U
|
||||
#define EFUSE_RESERVED_2_253_S 29
|
||||
|
||||
/** EFUSE_RD_USR_DATA0_REG register
|
||||
* Register $n of BLOCK3 (user).
|
||||
|
||||
@ -639,10 +639,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the fourth 32 bits of the first part of system data.
|
||||
/** temp_calib : R; bitpos: [8:0]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
uint32_t sys_data_part1_4:32;
|
||||
uint32_t temp_calib:9;
|
||||
/** ocode : R; bitpos: [16:9]; default: 0;
|
||||
* ADC OCode
|
||||
*/
|
||||
uint32_t ocode:8;
|
||||
/** adc1_init_code_atten0 : R; bitpos: [26:17]; default: 0;
|
||||
* ADC1 init code at atten0
|
||||
*/
|
||||
uint32_t adc1_init_code_atten0:10;
|
||||
/** adc1_init_code_atten1 : R; bitpos: [31:27]; default: 0;
|
||||
* ADC1 init code at atten1
|
||||
*/
|
||||
uint32_t adc1_init_code_atten1:5;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data4_reg_t;
|
||||
@ -652,10 +664,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the fifth 32 bits of the first part of system data.
|
||||
/** adc1_init_code_atten1_1 : R; bitpos: [4:0]; default: 0;
|
||||
* ADC1 init code at atten1
|
||||
*/
|
||||
uint32_t sys_data_part1_5:32;
|
||||
uint32_t adc1_init_code_atten1_1:5;
|
||||
/** adc1_init_code_atten2 : R; bitpos: [14:5]; default: 0;
|
||||
* ADC1 init code at atten2
|
||||
*/
|
||||
uint32_t adc1_init_code_atten2:10;
|
||||
/** adc1_init_code_atten3 : R; bitpos: [24:15]; default: 0;
|
||||
* ADC1 init code at atten3
|
||||
*/
|
||||
uint32_t adc1_init_code_atten3:10;
|
||||
/** adc1_cal_vol_atten0 : R; bitpos: [31:25]; default: 0;
|
||||
* ADC1 calibration voltage at atten0
|
||||
*/
|
||||
uint32_t adc1_cal_vol_atten0:7;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data5_reg_t;
|
||||
@ -665,10 +689,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the sixth 32 bits of the first part of system data.
|
||||
/** adc1_cal_vol_atten0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* ADC1 calibration voltage at atten0
|
||||
*/
|
||||
uint32_t sys_data_part1_6:32;
|
||||
uint32_t adc1_cal_vol_atten0_1:3;
|
||||
/** adc1_cal_vol_atten1 : R; bitpos: [12:3]; default: 0;
|
||||
* ADC1 calibration voltage at atten1
|
||||
*/
|
||||
uint32_t adc1_cal_vol_atten1:10;
|
||||
/** adc1_cal_vol_atten2 : R; bitpos: [22:13]; default: 0;
|
||||
* ADC1 calibration voltage at atten2
|
||||
*/
|
||||
uint32_t adc1_cal_vol_atten2:10;
|
||||
/** adc1_cal_vol_atten3 : R; bitpos: [31:23]; default: 0;
|
||||
* ADC1 calibration voltage at atten3
|
||||
*/
|
||||
uint32_t adc1_cal_vol_atten3:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data6_reg_t;
|
||||
@ -678,10 +714,42 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the seventh 32 bits of the first part of system data.
|
||||
/** adc1_cal_vol_atten3_1 : R; bitpos: [0]; default: 0;
|
||||
* ADC1 calibration voltage at atten3
|
||||
*/
|
||||
uint32_t sys_data_part1_7:32;
|
||||
uint32_t adc1_cal_vol_atten3_1:1;
|
||||
/** adc1_init_code_atten0_ch0 : R; bitpos: [4:1]; default: 0;
|
||||
* ADC1 init code at atten0 ch0
|
||||
*/
|
||||
uint32_t adc1_init_code_atten0_ch0:4;
|
||||
/** adc1_init_code_atten0_ch1 : R; bitpos: [8:5]; default: 0;
|
||||
* ADC1 init code at atten0 ch1
|
||||
*/
|
||||
uint32_t adc1_init_code_atten0_ch1:4;
|
||||
/** adc1_init_code_atten0_ch2 : R; bitpos: [12:9]; default: 0;
|
||||
* ADC1 init code at atten0 ch2
|
||||
*/
|
||||
uint32_t adc1_init_code_atten0_ch2:4;
|
||||
/** adc1_init_code_atten0_ch3 : R; bitpos: [16:13]; default: 0;
|
||||
* ADC1 init code at atten0 ch3
|
||||
*/
|
||||
uint32_t adc1_init_code_atten0_ch3:4;
|
||||
/** adc1_init_code_atten0_ch4 : R; bitpos: [20:17]; default: 0;
|
||||
* ADC1 init code at atten0 ch4
|
||||
*/
|
||||
uint32_t adc1_init_code_atten0_ch4:4;
|
||||
/** adc1_init_code_atten0_ch5 : R; bitpos: [24:21]; default: 0;
|
||||
* ADC1 init code at atten0 ch5
|
||||
*/
|
||||
uint32_t adc1_init_code_atten0_ch5:4;
|
||||
/** adc1_init_code_atten0_ch6 : R; bitpos: [28:25]; default: 0;
|
||||
* ADC1 init code at atten0 ch6
|
||||
*/
|
||||
uint32_t adc1_init_code_atten0_ch6:4;
|
||||
/** reserved_2_253 : R; bitpos: [31:29]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_2_253:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data7_reg_t;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user