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feat(esp32p4): added esp_rom support

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This commit is contained in:
Armando 2023-07-11 16:54:13 +08:00
parent 59ed00a784
commit 3461449494
40 changed files with 6627 additions and 0 deletions
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22
components/esp_rom/CMakeLists.txt
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@ -122,6 +122,13 @@ if(BOOTLOADER_BUILD)
if(CONFIG_HAL_WDT_USE_ROM_IMPL)
rom_linker_script("wdt")
endif()
elseif(target STREQUAL "esp32p4")
rom_linker_script("newlib")
if(CONFIG_HAL_WDT_USE_ROM_IMPL)
rom_linker_script("wdt")
endif()
rom_linker_script("version")
endif()
else() # Regular app build
@ -258,6 +265,21 @@ else() # Regular app build
rom_linker_script("newlib-nano")
endif()
elseif(target STREQUAL "esp32p4")
rom_linker_script("newlib")
rom_linker_script("version")
# esp32p4 rom doesn't have esp_flash driver
if(CONFIG_HAL_WDT_USE_ROM_IMPL)
rom_linker_script("wdt")
endif()
if(CONFIG_NEWLIB_NANO_FORMAT)
# nano formatting functions in ROM are also built for 64-bit time_t.
rom_linker_script("newlib-nano")
endif()
endif()
if(CONFIG_HEAP_TLSF_USE_ROM_IMPL)

0
components/esp_rom/esp32p4/.gitkeep
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48
components/esp_rom/esp32p4/Kconfig.soc_caps.in Normal file
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@ -0,0 +1,48 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config ESP_ROM_HAS_CRC_LE
bool
default y
config ESP_ROM_HAS_CRC_BE
bool
default y
config ESP_ROM_UART_CLK_IS_XTAL
bool
default y
config ESP_ROM_USB_SERIAL_DEVICE_NUM
int
default 3
config ESP_ROM_HAS_RETARGETABLE_LOCKING
bool
default y
config ESP_ROM_GET_CLK_FREQ
bool
default y
config ESP_ROM_HAS_RVFPLIB
bool
default y
config ESP_ROM_HAS_HAL_WDT
bool
default y
config ESP_ROM_HAS_HAL_SYSTIMER
bool
default y
config ESP_ROM_HAS_LAYOUT_TABLE
bool
default y
config ESP_ROM_WDT_INIT_PATCH
bool
default y

19
components/esp_rom/esp32p4/esp_rom_caps.h Normal file
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@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian
#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian
#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM
#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM.
#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking
#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib
#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver
#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver
#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table
#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock

57
components/esp_rom/esp32p4/ld/esp32p4.rom.api.ld Normal file
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@ -0,0 +1,57 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** ROM APIs
*/
PROVIDE ( esp_rom_crc32_le = crc32_le );
PROVIDE ( esp_rom_crc16_le = crc16_le );
PROVIDE ( esp_rom_crc8_le = crc8_le );
PROVIDE ( esp_rom_crc32_be = crc32_be );
PROVIDE ( esp_rom_crc16_be = crc16_be );
PROVIDE ( esp_rom_crc8_be = crc8_be );
PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio );
PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup );
PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv );
PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold );
PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in );
PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );
PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char2 );
PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
PROVIDE ( esp_rom_md5_init = MD5Init );
PROVIDE ( esp_rom_md5_update = MD5Update );
PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_software_reset_system = software_reset );
PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable );
PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea );
PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix );
PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs);
PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction );
PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command );

606
components/esp_rom/esp32p4/ld/esp32p4.rom.ld Normal file
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@ -0,0 +1,606 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32p4.rom.ld for esp32p4
*
*
* Generated from ./target/esp32p4/interface-esp32p4.yml md5sum d91797f41641e3e0180293939810e553
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group common
***************************************/
/* Functions */
rtc_get_reset_reason = 0x4fc00018;
rtc_get_wakeup_cause = 0x4fc0001c;
rtc_unhold_all_pads = 0x4fc00020;
ets_printf = 0x4fc00024;
ets_install_putc1 = 0x4fc00028;
ets_install_putc2 = 0x4fc0002c;
ets_install_uart_printf = 0x4fc00030;
ets_install_usb_printf = 0x4fc00034;
ets_get_printf_channel = 0x4fc00038;
ets_delay_us = 0x4fc0003c;
ets_get_cpu_frequency = 0x4fc00040;
ets_update_cpu_frequency = 0x4fc00044;
ets_install_lock = 0x4fc00048;
UartRxString = 0x4fc0004c;
UartGetCmdLn = 0x4fc00050;
uart_tx_one_char = 0x4fc00054;
uart_tx_one_char2 = 0x4fc00058;
uart_tx_one_char3 = 0x4fc0005c;
uart_rx_one_char = 0x4fc00060;
uart_rx_one_char_block = 0x4fc00064;
uart_rx_intr_handler = 0x4fc00068;
uart_rx_readbuff = 0x4fc0006c;
uartAttach = 0x4fc00070;
uart_tx_flush = 0x4fc00074;
uart_tx_wait_idle = 0x4fc00078;
uart_div_modify = 0x4fc0007c;
ets_write_char_uart = 0x4fc00080;
uart_tx_switch = 0x4fc00084;
uart_buff_switch = 0x4fc00088;
roundup2 = 0x4fc0008c;
multofup = 0x4fc00090;
software_reset = 0x4fc00094;
software_reset_cpu = 0x4fc00098;
ets_clk_assist_debug_clock_enable = 0x4fc0009c;
clear_super_wdt_reset_flag = 0x4fc000a0;
disable_default_watchdog = 0x4fc000a4;
ets_set_appcpu_boot_addr = 0x4fc000a8;
send_packet = 0x4fc000ac;
recv_packet = 0x4fc000b0;
GetUartDevice = 0x4fc000b4;
UartDwnLdProc = 0x4fc000b8;
GetSecurityInfoProc = 0x4fc000bc;
Uart_Init = 0x4fc000c0;
ets_set_user_start = 0x4fc000c4;
/* Data (.data, .bss, .rodata) */
ets_rom_layout_p = 0x4fc1fffc;
ets_ops_table_ptr = 0x4ff3fff4;
g_saved_pc = 0x4ff3fff8;
/***************************************
Group miniz
***************************************/
/* Functions */
mz_adler32 = 0x4fc000c8;
mz_free = 0x4fc000cc;
tdefl_compress = 0x4fc000d0;
tdefl_compress_buffer = 0x4fc000d4;
tdefl_compress_mem_to_heap = 0x4fc000d8;
tdefl_compress_mem_to_mem = 0x4fc000dc;
tdefl_compress_mem_to_output = 0x4fc000e0;
tdefl_get_adler32 = 0x4fc000e4;
tdefl_get_prev_return_status = 0x4fc000e8;
tdefl_init = 0x4fc000ec;
tdefl_write_image_to_png_file_in_memory = 0x4fc000f0;
tdefl_write_image_to_png_file_in_memory_ex = 0x4fc000f4;
tinfl_decompress = 0x4fc000f8;
tinfl_decompress_mem_to_callback = 0x4fc000fc;
tinfl_decompress_mem_to_heap = 0x4fc00100;
tinfl_decompress_mem_to_mem = 0x4fc00104;
/***************************************
Group spi_extmem_common
***************************************/
/* Functions */
esp_rom_spi_cmd_config = 0x4fc00108;
esp_rom_spi_cmd_start = 0x4fc0010c;
esp_rom_spi_set_op_mode = 0x4fc00110;
esp_rom_spi_set_dtr_swap_mode = 0x4fc00114;
/***************************************
Group spiflash_legacy
***************************************/
/* Functions */
esp_rom_spiflash_wait_idle = 0x4fc00118;
esp_rom_spiflash_write_encrypted = 0x4fc0011c;
esp_rom_spiflash_write_encrypted_dest = 0x4fc00120;
esp_rom_spiflash_write_encrypted_enable = 0x4fc00124;
esp_rom_spiflash_write_encrypted_disable = 0x4fc00128;
esp_rom_spiflash_erase_chip = 0x4fc0012c;
_esp_rom_spiflash_erase_sector = 0x4fc00130;
_esp_rom_spiflash_erase_block = 0x4fc00134;
_esp_rom_spiflash_write = 0x4fc00138;
_esp_rom_spiflash_read = 0x4fc0013c;
_esp_rom_spiflash_unlock = 0x4fc00140;
_SPIEraseArea = 0x4fc00144;
_SPI_write_enable = 0x4fc00148;
esp_rom_spiflash_erase_sector = 0x4fc0014c;
esp_rom_spiflash_erase_block = 0x4fc00150;
esp_rom_spiflash_write = 0x4fc00154;
esp_rom_spiflash_read = 0x4fc00158;
esp_rom_spiflash_unlock = 0x4fc0015c;
SPIEraseArea = 0x4fc00160;
SPI_write_enable = 0x4fc00164;
esp_rom_spiflash_config_param = 0x4fc00168;
esp_rom_spiflash_read_user_cmd = 0x4fc0016c;
esp_rom_spiflash_select_qio_pins = 0x4fc00170;
esp_rom_spi_flash_auto_sus_res = 0x4fc00174;
esp_rom_spi_flash_send_resume = 0x4fc00178;
esp_rom_spi_flash_update_id = 0x4fc0017c;
esp_rom_spiflash_config_clk = 0x4fc00180;
esp_rom_spiflash_config_readmode = 0x4fc00184;
esp_rom_spiflash_read_status = 0x4fc00188;
esp_rom_spiflash_read_statushigh = 0x4fc0018c;
esp_rom_spiflash_write_status = 0x4fc00190;
esp_rom_spiflash_write_disable = 0x4fc00194;
spi_cache_mode_switch = 0x4fc00198;
spi_common_set_dummy_output = 0x4fc0019c;
spi_common_set_flash_cs_timing = 0x4fc001a0;
esp_rom_spi_set_address_bit_len = 0x4fc001a4;
SPILock = 0x4fc001a8;
SPIMasterReadModeCnfig = 0x4fc001ac;
SPI_Common_Command = 0x4fc001b0;
SPI_WakeUp = 0x4fc001b4;
SPI_block_erase = 0x4fc001b8;
SPI_chip_erase = 0x4fc001bc;
SPI_init = 0x4fc001c0;
SPI_page_program = 0x4fc001c4;
SPI_read_data = 0x4fc001c8;
SPI_sector_erase = 0x4fc001cc;
SelectSpiFunction = 0x4fc001d0;
SetSpiDrvs = 0x4fc001d4;
Wait_SPI_Idle = 0x4fc001d8;
spi_dummy_len_fix = 0x4fc001dc;
Disable_QMode = 0x4fc001e0;
Enable_QMode = 0x4fc001e4;
spi_flash_attach = 0x4fc001e8;
spi_flash_get_chip_size = 0x4fc001ec;
spi_flash_guard_set = 0x4fc001f0;
spi_flash_guard_get = 0x4fc001f4;
spi_flash_read_encrypted = 0x4fc001f8;
/* Data (.data, .bss, .rodata) */
rom_spiflash_legacy_funcs = 0x4ff3ffec;
rom_spiflash_legacy_data = 0x4ff3ffe8;
g_flash_guard_ops = 0x4ff3fff0;
/***************************************
Group hal_systimer
***************************************/
/* Functions */
systimer_hal_init = 0x4fc00228;
systimer_hal_deinit = 0x4fc0022c;
systimer_hal_set_tick_rate_ops = 0x4fc00230;
systimer_hal_get_counter_value = 0x4fc00234;
systimer_hal_get_time = 0x4fc00238;
systimer_hal_set_alarm_target = 0x4fc0023c;
systimer_hal_set_alarm_period = 0x4fc00240;
systimer_hal_get_alarm_value = 0x4fc00244;
systimer_hal_enable_alarm_int = 0x4fc00248;
systimer_hal_on_apb_freq_update = 0x4fc0024c;
systimer_hal_counter_value_advance = 0x4fc00250;
systimer_hal_enable_counter = 0x4fc00254;
systimer_hal_select_alarm_mode = 0x4fc00258;
systimer_hal_connect_alarm_counter = 0x4fc0025c;
systimer_hal_counter_can_stall_by_cpu = 0x4fc00260;
/***************************************
Group cache
***************************************/
/* Functions */
Cache_Get_L1_ICache_Line_Size = 0x4fc003c4;
Cache_Get_L1_DCache_Line_Size = 0x4fc003c8;
Cache_Get_L2_Cache_Line_Size = 0x4fc003cc;
Cache_Get_Mode = 0x4fc003d0;
Cache_Set_L2_Cache_Mode = 0x4fc003d4;
Cache_Address_Through_Cache = 0x4fc003d8;
ROM_Boot_Cache_Init = 0x4fc003dc;
Cache_Sync_Addr = 0x4fc003e0;
Cache_Invalidate_Addr = 0x4fc003e4;
Cache_Invalidate_Addr_Gid = 0x4fc003e8;
Cache_Clean_Addr = 0x4fc003ec;
Cache_Clean_Addr_Gid = 0x4fc003f0;
Cache_WriteBack_Addr = 0x4fc003f4;
Cache_WriteBack_Addr_Gid = 0x4fc003f8;
Cache_WriteBack_Invalidate_Addr = 0x4fc003fc;
Cache_WriteBack_Invalidate_Addr_Gid = 0x4fc00400;
Cache_Invalidate_All = 0x4fc00404;
Cache_Invalidate_All_Gid = 0x4fc00408;
Cache_Clean_All = 0x4fc0040c;
Cache_Clean_All_Gid = 0x4fc00410;
Cache_WriteBack_All = 0x4fc00414;
Cache_WriteBack_All_Gid = 0x4fc00418;
Cache_WriteBack_Invalidate_All = 0x4fc0041c;
Cache_WriteBack_Invalidate_All_Gid = 0x4fc00420;
Cache_Mask_All = 0x4fc00424;
Cache_Suspend_L1_CORE0_ICache_Autoload = 0x4fc00428;
Cache_Resume_L1_CORE0_ICache_Autoload = 0x4fc0042c;
Cache_Suspend_L1_CORE1_ICache_Autoload = 0x4fc00430;
Cache_Resume_L1_CORE1_ICache_Autoload = 0x4fc00434;
Cache_Suspend_L1_DCache_Autoload = 0x4fc00438;
Cache_Resume_L1_DCache_Autoload = 0x4fc0043c;
Cache_Suspend_L2_Cache_Autoload = 0x4fc00440;
Cache_Resume_L2_Cache_Autoload = 0x4fc00444;
Cache_Start_L1_CORE0_ICache_Preload = 0x4fc00448;
Cache_L1_CORE0_ICache_Preload_Done = 0x4fc0044c;
Cache_End_L1_CORE0_ICache_Preload = 0x4fc00450;
Cache_Start_L1_CORE1_ICache_Preload = 0x4fc00454;
Cache_L1_CORE1_ICache_Preload_Done = 0x4fc00458;
Cache_End_L1_CORE1_ICache_Preload = 0x4fc0045c;
Cache_Start_L1_DCache_Preload = 0x4fc00460;
Cache_L1_DCache_Preload_Done = 0x4fc00464;
Cache_End_L1_DCache_Preload = 0x4fc00468;
Cache_Start_L2_Cache_Preload = 0x4fc0046c;
Cache_L2_Cache_Preload_Done = 0x4fc00470;
Cache_End_L2_Cache_Preload = 0x4fc00474;
Cache_Config_L1_CORE0_ICache_Autoload = 0x4fc00478;
Cache_Enable_L1_CORE0_ICache_Autoload = 0x4fc0047c;
Cache_Disable_L1_CORE0_ICache_Autoload = 0x4fc00480;
Cache_Config_L1_CORE1_ICache_Autoload = 0x4fc00484;
Cache_Enable_L1_CORE1_ICache_Autoload = 0x4fc00488;
Cache_Disable_L1_CORE1_ICache_Autoload = 0x4fc0048c;
Cache_Config_L1_DCache_Autoload = 0x4fc00490;
Cache_Enable_L1_DCache_Autoload = 0x4fc00494;
Cache_Disable_L1_DCache_Autoload = 0x4fc00498;
Cache_Config_L2_Cache_Autoload = 0x4fc0049c;
Cache_Enable_L2_Cache_Autoload = 0x4fc004a0;
Cache_Disable_L2_Cache_Autoload = 0x4fc004a4;
Cache_Enable_L1_CORE0_ICache_PreLock = 0x4fc004a8;
Cache_Disable_L1_CORE0_ICache_PreLock = 0x4fc004ac;
Cache_Enable_L1_CORE1_ICache_PreLock = 0x4fc004b0;
Cache_Disable_L1_CORE1_ICache_PreLock = 0x4fc004b4;
Cache_Enable_L1_DCache_PreLock = 0x4fc004b8;
Cache_Disable_L1_DCache_PreLock = 0x4fc004bc;
Cache_Enable_L2_Cache_PreLock = 0x4fc004c0;
Cache_Disable_L2_Cache_PreLock = 0x4fc004c4;
Cache_Lock_Addr = 0x4fc004c8;
Cache_Unlock_Addr = 0x4fc004cc;
Cache_Disable_L1_CORE0_ICache = 0x4fc004d0;
Cache_Enable_L1_CORE0_ICache = 0x4fc004d4;
Cache_Suspend_L1_CORE0_ICache = 0x4fc004d8;
Cache_Resume_L1_CORE0_ICache = 0x4fc004dc;
Cache_Disable_L1_CORE1_ICache = 0x4fc004e0;
Cache_Enable_L1_CORE1_ICache = 0x4fc004e4;
Cache_Suspend_L1_CORE1_ICache = 0x4fc004e8;
Cache_Resume_L1_CORE1_ICache = 0x4fc004ec;
Cache_Disable_L1_DCache = 0x4fc004f0;
Cache_Enable_L1_DCache = 0x4fc004f4;
Cache_Suspend_L1_DCache = 0x4fc004f8;
Cache_Resume_L1_DCache = 0x4fc004fc;
Cache_Disable_L2_Cache = 0x4fc00500;
Cache_Enable_L2_Cache = 0x4fc00504;
Cache_Suspend_L2_Cache = 0x4fc00508;
Cache_Resume_L2_Cache = 0x4fc0050c;
Cache_FLASH_MMU_Init = 0x4fc00510;
Cache_PSRAM_MMU_Init = 0x4fc00514;
Cache_FLASH_MMU_Set = 0x4fc00518;
Cache_FLASH_MMU_Set_Secure = 0x4fc0051c;
Cache_PSRAM_MMU_Set = 0x4fc00520;
Cache_PSRAM_MMU_Set_Secure = 0x4fc00524;
Cache_Count_Flash_Pages = 0x4fc00528;
Cache_Flash_To_SPIRAM_Copy = 0x4fc0052c;
Cache_Travel_Tag_Memory = 0x4fc00530;
Cache_Travel_Tag_Memory2 = 0x4fc00534;
Cache_Get_Virtual_Addr = 0x4fc00538;
Cache_Set_IDROM_MMU_Size = 0x4fc0053c;
flash2spiram_instruction_offset = 0x4fc00540;
flash2spiram_rodata_offset = 0x4fc00544;
flash_instr_rodata_start_page = 0x4fc00548;
flash_instr_rodata_end_page = 0x4fc0054c;
Cache_Set_IDROM_MMU_Info = 0x4fc00550;
Cache_Get_IROM_MMU_End = 0x4fc00554;
Cache_Get_DROM_MMU_End = 0x4fc00558;
/* Data (.data, .bss, .rodata) */
rom_cache_op_cb = 0x4ff3ffdc;
rom_cache_internal_table_ptr = 0x4ff3ffd8;
/***************************************
Group clock
***************************************/
/* Functions */
ets_clk_get_xtal_freq = 0x4fc0055c;
ets_clk_get_cpu_freq = 0x4fc00560;
/***************************************
Group gpio
***************************************/
/* Functions */
gpio_input_get = 0x4fc00564;
gpio_input_get_high = 0x4fc00568;
gpio_matrix_in = 0x4fc0056c;
gpio_matrix_out = 0x4fc00570;
gpio_output_disable = 0x4fc00574;
gpio_output_enable = 0x4fc00578;
gpio_output_set = 0x4fc0057c;
gpio_output_set_high = 0x4fc00580;
gpio_pad_hold = 0x4fc00584;
gpio_pad_input_disable = 0x4fc00588;
gpio_pad_input_enable = 0x4fc0058c;
gpio_pad_pulldown = 0x4fc00590;
gpio_pad_pullup = 0x4fc00594;
gpio_pad_select_gpio = 0x4fc00598;
gpio_pad_set_drv = 0x4fc0059c;
gpio_pad_unhold = 0x4fc005a0;
gpio_pin_wakeup_disable = 0x4fc005a4;
gpio_pin_wakeup_enable = 0x4fc005a8;
gpio_bypass_matrix_in = 0x4fc005ac;
/***************************************
Group interrupts
***************************************/
/* Functions */
esprv_intc_int_set_priority = 0x4fc005b0;
esprv_intc_int_set_threshold = 0x4fc005b4;
esprv_intc_int_enable = 0x4fc005b8;
esprv_intc_int_disable = 0x4fc005bc;
esprv_intc_int_set_type = 0x4fc005c0;
PROVIDE( intr_handler_set = 0x4fc005c4 );
intr_matrix_set = 0x4fc005c8;
ets_intr_lock = 0x4fc005cc;
ets_intr_unlock = 0x4fc005d0;
ets_isr_attach = 0x4fc005d4;
ets_isr_mask = 0x4fc005d8;
ets_isr_unmask = 0x4fc005dc;
/***************************************
Group crypto
***************************************/
/* Functions */
md5_vector = 0x4fc005e0;
MD5Init = 0x4fc005e4;
MD5Update = 0x4fc005e8;
MD5Final = 0x4fc005ec;
crc32_le = 0x4fc005f0;
crc16_le = 0x4fc005f4;
crc8_le = 0x4fc005f8;
crc32_be = 0x4fc005fc;
crc16_be = 0x4fc00600;
crc8_be = 0x4fc00604;
esp_crc8 = 0x4fc00608;
ets_sha_enable = 0x4fc0060c;
ets_sha_disable = 0x4fc00610;
ets_sha_get_state = 0x4fc00614;
ets_sha_init = 0x4fc00618;
ets_sha_process = 0x4fc0061c;
ets_sha_starts = 0x4fc00620;
ets_sha_update = 0x4fc00624;
ets_sha_finish = 0x4fc00628;
ets_sha_clone = 0x4fc0062c;
ets_hmac_enable = 0x4fc00630;
ets_hmac_disable = 0x4fc00634;
ets_hmac_calculate_message = 0x4fc00638;
ets_hmac_calculate_downstream = 0x4fc0063c;
ets_hmac_invalidate_downstream = 0x4fc00640;
ets_jtag_enable_temporarily = 0x4fc00644;
ets_aes_enable = 0x4fc00648;
ets_aes_disable = 0x4fc0064c;
ets_aes_setkey = 0x4fc00650;
ets_aes_block = 0x4fc00654;
ets_aes_setkey_dec = 0x4fc00658;
ets_aes_setkey_enc = 0x4fc0065c;
ets_bigint_enable = 0x4fc00660;
ets_bigint_disable = 0x4fc00664;
ets_bigint_multiply = 0x4fc00668;
ets_bigint_modmult = 0x4fc0066c;
ets_bigint_modexp = 0x4fc00670;
ets_bigint_wait_finish = 0x4fc00674;
ets_bigint_getz = 0x4fc00678;
ets_ds_enable = 0x4fc0067c;
ets_ds_disable = 0x4fc00680;
ets_ds_start_sign = 0x4fc00684;
ets_ds_is_busy = 0x4fc00688;
ets_ds_finish_sign = 0x4fc0068c;
ets_ds_encrypt_params = 0x4fc00690;
ets_mgf1_sha256 = 0x4fc00694;
/* Data (.data, .bss, .rodata) */
crc32_le_table_ptr = 0x4fc1fff8;
crc16_le_table_ptr = 0x4fc1fff4;
crc8_le_table_ptr = 0x4fc1fff0;
crc32_be_table_ptr = 0x4fc1ffec;
crc16_be_table_ptr = 0x4fc1ffe8;
crc8_be_table_ptr = 0x4fc1ffe4;
/***************************************
Group efuse
***************************************/
/* Functions */
ets_efuse_read = 0x4fc00698;
ets_efuse_program = 0x4fc0069c;
ets_efuse_clear_program_registers = 0x4fc006a0;
ets_efuse_write_key = 0x4fc006a4;
ets_efuse_get_read_register_address = 0x4fc006a8;
ets_efuse_get_key_purpose = 0x4fc006ac;
ets_efuse_key_block_unused = 0x4fc006b0;
ets_efuse_find_unused_key_block = 0x4fc006b4;
ets_efuse_rs_calculate = 0x4fc006b8;
ets_efuse_count_unused_key_blocks = 0x4fc006bc;
ets_efuse_secure_boot_enabled = 0x4fc006c0;
ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4fc006c4;
ets_efuse_cache_encryption_enabled = 0x4fc006c8;
ets_efuse_download_modes_disabled = 0x4fc006cc;
ets_efuse_find_purpose = 0x4fc006d0;
ets_efuse_force_send_resume = 0x4fc006d4;
ets_efuse_get_flash_delay_us = 0x4fc006d8;
ets_efuse_get_uart_print_control = 0x4fc006dc;
ets_efuse_direct_boot_mode_disabled = 0x4fc006e0;
ets_efuse_security_download_modes_enabled = 0x4fc006e4;
ets_efuse_jtag_disabled = 0x4fc006e8;
ets_efuse_usb_print_is_disabled = 0x4fc006ec;
ets_efuse_usb_download_mode_disabled = 0x4fc006f0;
ets_efuse_usb_device_disabled = 0x4fc006f4;
ets_efuse_get_km_huk_gen_state = 0x4fc006f8;
ets_efuse_get_km_deploy_only_once = 0x4fc006fc;
ets_efuse_get_force_use_km_key = 0x4fc00700;
ets_efuse_xts_key_length_256 = 0x4fc00704;
ets_efuse_get_km_key_lock = 0x4fc00708;
/***************************************
Group key_mgr
***************************************/
/* Functions */
esp_rom_check_recover_key = 0x4fc0070c;
esp_rom_km_huk_conf = 0x4fc00710;
esp_rom_km_huk_risk = 0x4fc00714;
/***************************************
Group secureboot
***************************************/
/* Functions */
ets_emsa_pss_verify = 0x4fc00718;
ets_rsa_pss_verify = 0x4fc0071c;
ets_ecdsa_verify = 0x4fc00720;
ets_secure_boot_verify_bootloader_with_keys = 0x4fc00724;
ets_secure_boot_verify_signature = 0x4fc00728;
ets_secure_boot_read_key_digests = 0x4fc0072c;
ets_secure_boot_revoke_public_key_digest = 0x4fc00730;
/***************************************
Group usb_device_uart
***************************************/
/* Functions */
usb_serial_device_rx_one_char = 0x4fc008a8;
usb_serial_device_rx_one_char_block = 0x4fc008ac;
usb_serial_device_tx_flush = 0x4fc008b0;
usb_serial_device_tx_one_char = 0x4fc008b4;
/***************************************
Group usb_dwcotg_uart
***************************************/
/* Functions */
Uart_Init_USB = 0x4fc008b8;
usb_serial_otg_rx_one_char = 0x4fc008bc;
usb_serial_otg_rx_one_char_block = 0x4fc008c0;
usb_serial_otg_tx_flush = 0x4fc008c4;
usb_serial_otg_tx_one_char = 0x4fc008c8;
/* Data (.data, .bss, .rodata) */
uart_acm_dev = 0x4ff3ffd4;
/***************************************
Group usb_dwcotg_module
***************************************/
/* Functions */
cdc_acm_class_handle_req = 0x4fc008cc;
cdc_acm_init = 0x4fc008d0;
cdc_acm_fifo_fill = 0x4fc008d4;
cdc_acm_rx_fifo_cnt = 0x4fc008d8;
cdc_acm_fifo_read = 0x4fc008dc;
cdc_acm_irq_tx_enable = 0x4fc008e0;
cdc_acm_irq_tx_disable = 0x4fc008e4;
cdc_acm_irq_state_enable = 0x4fc008e8;
cdc_acm_irq_state_disable = 0x4fc008ec;
cdc_acm_irq_tx_ready = 0x4fc008f0;
cdc_acm_irq_rx_enable = 0x4fc008f4;
cdc_acm_irq_rx_disable = 0x4fc008f8;
cdc_acm_irq_rx_ready = 0x4fc008fc;
cdc_acm_irq_is_pending = 0x4fc00900;
cdc_acm_irq_callback_set = 0x4fc00904;
cdc_acm_line_ctrl_set = 0x4fc00908;
cdc_acm_line_ctrl_get = 0x4fc0090c;
cdc_acm_poll_out = 0x4fc00910;
chip_usb_dw_did_persist = 0x4fc00914;
chip_usb_dw_init = 0x4fc00918;
chip_usb_detach = 0x4fc0091c;
chip_usb_dw_prepare_persist = 0x4fc00920;
chip_usb_get_persist_flags = 0x4fc00924;
chip_usb_set_persist_flags = 0x4fc00928;
cpio_start = 0x4fc0092c;
cpio_feed = 0x4fc00930;
cpio_done = 0x4fc00934;
cpio_destroy = 0x4fc00938;
dfu_flash_init = 0x4fc0093c;
dfu_flash_erase = 0x4fc00940;
dfu_flash_program = 0x4fc00944;
dfu_flash_read = 0x4fc00948;
dfu_flash_attach = 0x4fc0094c;
dfu_cpio_callback = 0x4fc00950;
dfu_updater_get_err = 0x4fc00954;
dfu_updater_clear_err = 0x4fc00958;
dfu_updater_enable = 0x4fc0095c;
dfu_updater_begin = 0x4fc00960;
dfu_updater_feed = 0x4fc00964;
dfu_updater_end = 0x4fc00968;
dfu_updater_set_raw_addr = 0x4fc0096c;
dfu_updater_flash_read = 0x4fc00970;
usb_dc_prepare_persist = 0x4fc00974;
usb_dw_isr_handler = 0x4fc00978;
usb_dc_attach = 0x4fc0097c;
usb_dc_detach = 0x4fc00980;
usb_dc_reset = 0x4fc00984;
usb_dc_set_address = 0x4fc00988;
usb_dc_ep_check_cap = 0x4fc0098c;
usb_dc_ep_configure = 0x4fc00990;
usb_dc_ep_set_stall = 0x4fc00994;
usb_dc_ep_clear_stall = 0x4fc00998;
usb_dc_ep_halt = 0x4fc0099c;
usb_dc_ep_is_stalled = 0x4fc009a0;
usb_dc_ep_enable = 0x4fc009a4;
usb_dc_ep_disable = 0x4fc009a8;
usb_dc_ep_flush = 0x4fc009ac;
usb_dc_ep_write_would_block = 0x4fc009b0;
usb_dc_ep_write = 0x4fc009b4;
usb_dc_ep_read_wait = 0x4fc009b8;
usb_dc_ep_read_continue = 0x4fc009bc;
usb_dc_ep_read = 0x4fc009c0;
usb_dc_ep_set_callback = 0x4fc009c4;
usb_dc_set_status_callback = 0x4fc009c8;
usb_dc_ep_mps = 0x4fc009cc;
usb_dc_check_poll_for_interrupts = 0x4fc009d0;
mac_addr_to_serial_str_desc = 0x4fc009d4;
usb_set_current_descriptor = 0x4fc009d8;
usb_get_descriptor = 0x4fc009dc;
usb_dev_resume = 0x4fc009e0;
usb_dev_get_configuration = 0x4fc009e4;
usb_set_config = 0x4fc009e8;
usb_deconfig = 0x4fc009ec;
usb_enable = 0x4fc009f0;
usb_disable = 0x4fc009f4;
usb_write_would_block = 0x4fc009f8;
usb_write = 0x4fc009fc;
usb_read = 0x4fc00a00;
usb_ep_set_stall = 0x4fc00a04;
usb_ep_clear_stall = 0x4fc00a08;
usb_ep_read_wait = 0x4fc00a0c;
usb_ep_read_continue = 0x4fc00a10;
usb_transfer_ep_callback = 0x4fc00a14;
usb_transfer = 0x4fc00a18;
usb_cancel_transfer = 0x4fc00a1c;
usb_transfer_sync = 0x4fc00a20;
usb_dfu_set_detach_cb = 0x4fc00a24;
dfu_class_handle_req = 0x4fc00a28;
dfu_status_cb = 0x4fc00a2c;
dfu_custom_handle_req = 0x4fc00a30;
usb_dfu_init = 0x4fc00a34;
usb_dfu_force_detach = 0x4fc00a38;
usb_dev_deinit = 0x4fc00a3c;
usb_dw_ctrl_deinit = 0x4fc00a40;
/* Data (.data, .bss, .rodata) */
s_usb_osglue = 0x4ff3ffc8;

95
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32p4.rom.libgcc.ld for esp32p4
*
*
* Generated from ./target/esp32p4/interface-esp32p4.yml md5sum d91797f41641e3e0180293939810e553
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group libgccdf
***************************************/
/* Functions */
__absvdi2 = 0x4fc00734;
__absvsi2 = 0x4fc00738;
__adddf3 = 0x4fc0073c;
__addvdi3 = 0x4fc00740;
__addvsi3 = 0x4fc00744;
__ashldi3 = 0x4fc00748;
__ashrdi3 = 0x4fc0074c;
__bswapdi2 = 0x4fc00750;
__bswapsi2 = 0x4fc00754;
__clear_cache = 0x4fc00758;
__clrsbdi2 = 0x4fc0075c;
__clrsbsi2 = 0x4fc00760;
__clzdi2 = 0x4fc00764;
__clzsi2 = 0x4fc00768;
__cmpdi2 = 0x4fc0076c;
__ctzdi2 = 0x4fc00770;
__ctzsi2 = 0x4fc00774;
__divdc3 = 0x4fc00778;
__divdf3 = 0x4fc0077c;
__divdi3 = 0x4fc00780;
__divsc3 = 0x4fc00784;
__divsi3 = 0x4fc00788;
__eqdf2 = 0x4fc0078c;
__extendsfdf2 = 0x4fc00790;
__ffsdi2 = 0x4fc00794;
__ffssi2 = 0x4fc00798;
__fixdfdi = 0x4fc0079c;
__fixdfsi = 0x4fc007a0;
__fixsfdi = 0x4fc007a4;
__fixunsdfsi = 0x4fc007a8;
__fixunssfdi = 0x4fc007ac;
__fixunssfsi = 0x4fc007b0;
__floatdidf = 0x4fc007b4;
__floatdisf = 0x4fc007b8;
__floatsidf = 0x4fc007bc;
__floatundidf = 0x4fc007c0;
__floatundisf = 0x4fc007c4;
__floatunsidf = 0x4fc007c8;
__gcc_bcmp = 0x4fc007cc;
__gedf2 = 0x4fc007d0;
__gtdf2 = 0x4fc007d4;
__ledf2 = 0x4fc007d8;
__lshrdi3 = 0x4fc007dc;
__ltdf2 = 0x4fc007e0;
__moddi3 = 0x4fc007e4;
__modsi3 = 0x4fc007e8;
__muldc3 = 0x4fc007ec;
__muldf3 = 0x4fc007f0;
__muldi3 = 0x4fc007f4;
__mulsc3 = 0x4fc007f8;
__mulsi3 = 0x4fc007fc;
__mulvdi3 = 0x4fc00800;
__mulvsi3 = 0x4fc00804;
__nedf2 = 0x4fc00808;
__negdf2 = 0x4fc0080c;
__negdi2 = 0x4fc00810;
__negvdi2 = 0x4fc00814;
__negvsi2 = 0x4fc00818;
__paritysi2 = 0x4fc0081c;
__popcountdi2 = 0x4fc00820;
__popcountsi2 = 0x4fc00824;
__powidf2 = 0x4fc00828;
__subdf3 = 0x4fc0082c;
__subvdi3 = 0x4fc00830;
__subvsi3 = 0x4fc00834;
__ucmpdi2 = 0x4fc00838;
__udivdi3 = 0x4fc0083c;
__udivmoddi4 = 0x4fc00840;
__udivsi3 = 0x4fc00844;
__udiv_w_sdiv = 0x4fc00848;
__umoddi3 = 0x4fc0084c;
__umodsi3 = 0x4fc00850;
__unorddf2 = 0x4fc00854;
__extenddftf2 = 0x4fc00858;
__trunctfdf2 = 0x4fc0085c;

32
components/esp_rom/esp32p4/ld/esp32p4.rom.newlib-nano.ld Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32p4.rom.newlib-nano.ld for esp32p4
*
*
* Generated from ./target/esp32p4/interface-esp32p4.yml md5sum d91797f41641e3e0180293939810e553
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group newlib_nano_format
***************************************/
/* Functions */
__sprint_r = 0x4fc00394;
_fiprintf_r = 0x4fc00398;
_fprintf_r = 0x4fc0039c;
_printf_common = 0x4fc003a0;
_printf_i = 0x4fc003a4;
_vfiprintf_r = 0x4fc003a8;
_vfprintf_r = 0x4fc003ac;
fiprintf = 0x4fc003b0;
fprintf = 0x4fc003b4;
printf = 0x4fc003b8;
vfiprintf = 0x4fc003bc;
vfprintf = 0x4fc003c0;

99
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32p4.rom.newlib.ld for esp32p4
*
*
* Generated from ./target/esp32p4/interface-esp32p4.yml md5sum d91797f41641e3e0180293939810e553
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group newlib
***************************************/
/* Functions */
esp_rom_newlib_init_common_mutexes = 0x4fc00264;
memset = 0x4fc00268;
memcpy = 0x4fc0026c;
memmove = 0x4fc00270;
memcmp = 0x4fc00274;
strcpy = 0x4fc00278;
strncpy = 0x4fc0027c;
strcmp = 0x4fc00280;
strncmp = 0x4fc00284;
strlen = 0x4fc00288;
strstr = 0x4fc0028c;
bzero = 0x4fc00290;
_isatty_r = 0x4fc00294;
sbrk = 0x4fc00298;
isalnum = 0x4fc0029c;
isalpha = 0x4fc002a0;
isascii = 0x4fc002a4;
isblank = 0x4fc002a8;
iscntrl = 0x4fc002ac;
isdigit = 0x4fc002b0;
islower = 0x4fc002b4;
isgraph = 0x4fc002b8;
isprint = 0x4fc002bc;
ispunct = 0x4fc002c0;
isspace = 0x4fc002c4;
isupper = 0x4fc002c8;
toupper = 0x4fc002cc;
tolower = 0x4fc002d0;
toascii = 0x4fc002d4;
memccpy = 0x4fc002d8;
memchr = 0x4fc002dc;
memrchr = 0x4fc002e0;
strcasecmp = 0x4fc002e4;
strcasestr = 0x4fc002e8;
strcat = 0x4fc002ec;
strdup = 0x4fc002f0;
strchr = 0x4fc002f4;
strcspn = 0x4fc002f8;
strcoll = 0x4fc002fc;
strlcat = 0x4fc00300;
strlcpy = 0x4fc00304;
strlwr = 0x4fc00308;
strncasecmp = 0x4fc0030c;
strncat = 0x4fc00310;
strndup = 0x4fc00314;
strnlen = 0x4fc00318;
strrchr = 0x4fc0031c;
strsep = 0x4fc00320;
strspn = 0x4fc00324;
strtok_r = 0x4fc00328;
strupr = 0x4fc0032c;
longjmp = 0x4fc00330;
setjmp = 0x4fc00334;
abs = 0x4fc00338;
div = 0x4fc0033c;
labs = 0x4fc00340;
ldiv = 0x4fc00344;
qsort = 0x4fc00348;
rand_r = 0x4fc0034c;
rand = 0x4fc00350;
srand = 0x4fc00354;
utoa = 0x4fc00358;
itoa = 0x4fc0035c;
atoi = 0x4fc00360;
atol = 0x4fc00364;
strtol = 0x4fc00368;
strtoul = 0x4fc0036c;
fflush = 0x4fc00370;
_fflush_r = 0x4fc00374;
_fwalk = 0x4fc00378;
_fwalk_reent = 0x4fc0037c;
__smakebuf_r = 0x4fc00380;
__swhatbuf_r = 0x4fc00384;
__swbuf_r = 0x4fc00388;
__swbuf = 0x4fc0038c;
__swsetup_r = 0x4fc00390;
/* Data (.data, .bss, .rodata) */
syscall_table_ptr = 0x4ff3ffe4;
_global_impure_ptr = 0x4ff3ffe0;

101
components/esp_rom/esp32p4/ld/esp32p4.rom.rvfp.ld Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32p4.rom.rvfp.ld for esp32p4
*
*
* Generated from ./target/esp32p4/interface-esp32p4.yml md5sum d91797f41641e3e0180293939810e553
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group rvfplibdf
***************************************/
/* Functions */
__adddf3 = 0x4fc00860;
__eqdf2 = 0x4fc00864;
__fixdfdi = 0x4fc00868;
__fixdfsi = 0x4fc0086c;
__fixsfdi = 0x4fc00870;
__fixunsdfsi = 0x4fc00874;
__fixunssfdi = 0x4fc00878;
__floatdidf = 0x4fc0087c;
__floatsidf = 0x4fc00880;
__floatundidf = 0x4fc00884;
__floatunsidf = 0x4fc00888;
__gedf2 = 0x4fc0088c;
__gtdf2 = 0x4fc00890;
__ledf2 = 0x4fc00894;
__ltdf2 = 0x4fc00898;
__muldf3 = 0x4fc0089c;
__nedf2 = 0x4fc008a0;
__subdf3 = 0x4fc008a4;
/***************************************
Group libgcc
***************************************/
/* Functions */
__absvdi2 = 0x4fc00734;
__absvsi2 = 0x4fc00738;
__addvdi3 = 0x4fc00740;
__addvsi3 = 0x4fc00744;
__ashldi3 = 0x4fc00748;
__ashrdi3 = 0x4fc0074c;
__bswapdi2 = 0x4fc00750;
__bswapsi2 = 0x4fc00754;
__clear_cache = 0x4fc00758;
__clrsbdi2 = 0x4fc0075c;
__clrsbsi2 = 0x4fc00760;
__clzdi2 = 0x4fc00764;
__clzsi2 = 0x4fc00768;
__cmpdi2 = 0x4fc0076c;
__ctzdi2 = 0x4fc00770;
__ctzsi2 = 0x4fc00774;
__divdc3 = 0x4fc00778;
__divdf3 = 0x4fc0077c;
__divdi3 = 0x4fc00780;
__divsc3 = 0x4fc00784;
__divsi3 = 0x4fc00788;
__extendsfdf2 = 0x4fc00790;
__ffsdi2 = 0x4fc00794;
__ffssi2 = 0x4fc00798;
__fixunssfsi = 0x4fc007b0;
__floatdisf = 0x4fc007b8;
__floatundisf = 0x4fc007c4;
__gcc_bcmp = 0x4fc007cc;
__lshrdi3 = 0x4fc007dc;
__moddi3 = 0x4fc007e4;
__modsi3 = 0x4fc007e8;
__muldc3 = 0x4fc007ec;
__muldi3 = 0x4fc007f4;
__mulsc3 = 0x4fc007f8;
__mulsi3 = 0x4fc007fc;
__mulvdi3 = 0x4fc00800;
__mulvsi3 = 0x4fc00804;
__negdf2 = 0x4fc0080c;
__negdi2 = 0x4fc00810;
__negvdi2 = 0x4fc00814;
__negvsi2 = 0x4fc00818;
__paritysi2 = 0x4fc0081c;
__popcountdi2 = 0x4fc00820;
__popcountsi2 = 0x4fc00824;
__powidf2 = 0x4fc00828;
__subvdi3 = 0x4fc00830;
__subvsi3 = 0x4fc00834;
__ucmpdi2 = 0x4fc00838;
__udivdi3 = 0x4fc0083c;
__udivmoddi4 = 0x4fc00840;
__udivsi3 = 0x4fc00844;
__udiv_w_sdiv = 0x4fc00848;
__umoddi3 = 0x4fc0084c;
__umodsi3 = 0x4fc00850;
__unorddf2 = 0x4fc00854;
__extenddftf2 = 0x4fc00858;
__trunctfdf2 = 0x4fc0085c;

13
components/esp_rom/esp32p4/ld/esp32p4.rom.version.ld Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM version variables for esp32p4
*
* These addresses should be compatible with any ROM version for this chip.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
_rom_chip_id = 0x4fc00010;
_rom_eco_version = 0x4fc00014;

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components/esp_rom/esp32p4/ld/esp32p4.rom.wdt.ld Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32p4.rom.wdt.ld for esp32p4
*
*
* Generated from ./target/esp32p4/interface-esp32p4.yml md5sum d91797f41641e3e0180293939810e553
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group hal_wdt
***************************************/
/* Functions */
wdt_hal_init = 0x4fc001fc;
wdt_hal_deinit = 0x4fc00200;
wdt_hal_config_stage = 0x4fc00204;
wdt_hal_write_protect_disable = 0x4fc00208;
wdt_hal_write_protect_enable = 0x4fc0020c;
wdt_hal_enable = 0x4fc00210;
wdt_hal_disable = 0x4fc00214;
wdt_hal_handle_intr = 0x4fc00218;
wdt_hal_feed = 0x4fc0021c;
wdt_hal_set_flashboot_en = 0x4fc00220;
wdt_hal_is_enabled = 0x4fc00224;

56
components/esp_rom/esp32p4/ld/esp32p4lp.rom.ld Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32p4lp.rom.ld for esp32p4lp
*
*
* Generated from ./target/esp32p4lp/interface-esp32p4lp.yml md5sum 0751c805e21bd23f11b74dcc1f7e8007
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group common
***************************************/
/* Functions */
rtc_get_reset_reason = 0x50100098;
rtc_get_wakeup_cause = 0x5010009c;
ets_printf = 0x501000a0;
ets_install_putc1 = 0x501000a4;
ets_install_uart_printf = 0x501000a8;
ets_delay_us = 0x501000ac;
uart_tx_one_char = 0x501000b0;
uart_tx_flush = 0x501000b4;
uart_tx_wait_idle = 0x501000b8;
uartAttach = 0x501000bc;
Uart_Init = 0x501000c0;
GetUartDevice = 0x501000c4;
/***************************************
Group crypto
***************************************/
/* Functions */
crc32_le = 0x501000c8;
crc16_le = 0x501000cc;
crc8_le = 0x501000d0;
esp_crc8 = 0x501000d4;
/***************************************
Group interrupts
***************************************/
/* Functions */
ets_intr_lock = 0x501000d8;
ets_intr_unlock = 0x501000dc;
PROVIDE( intr_handler_set = 0x501000e0 );
ets_isr_attach = 0x501000e4;
ets_isr_mask = 0x501000e8;
ets_isr_unmask = 0x501000ec;

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32p4lp.rom.newlib.ld for esp32p4lp
*
*
* Generated from ./target/esp32p4lp/interface-esp32p4lp.yml md5sum 0751c805e21bd23f11b74dcc1f7e8007
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group newlib
***************************************/
/* Functions */
memset = 0x501000f0;
memcpy = 0x501000f4;
memmove = 0x501000f8;
memcmp = 0x501000fc;
strcpy = 0x50100100;
strncpy = 0x50100104;
strcmp = 0x50100108;
strncmp = 0x5010010c;
strlen = 0x50100110;
strstr = 0x50100114;
bzero = 0x50100118;
isalnum = 0x5010011c;
isalpha = 0x50100120;
isascii = 0x50100124;
isblank = 0x50100128;
iscntrl = 0x5010012c;
isdigit = 0x50100130;
islower = 0x50100134;
isgraph = 0x50100138;
isprint = 0x5010013c;
ispunct = 0x50100140;
isspace = 0x50100144;
isupper = 0x50100148;
toupper = 0x5010014c;
tolower = 0x50100150;
toascii = 0x50100154;
memccpy = 0x50100158;
memchr = 0x5010015c;
memrchr = 0x50100160;
strcasecmp = 0x50100164;
strcasestr = 0x50100168;
strcat = 0x5010016c;
strchr = 0x50100170;
strcspn = 0x50100174;
strcoll = 0x50100178;
strlcat = 0x5010017c;
strlcpy = 0x50100180;
strlwr = 0x50100184;
strncasecmp = 0x50100188;
strncat = 0x5010018c;
strnlen = 0x50100190;
strrchr = 0x50100194;
strsep = 0x50100198;
strspn = 0x5010019c;
strtok_r = 0x501001a0;
strupr = 0x501001a4;
longjmp = 0x501001a8;
setjmp = 0x501001ac;
abs = 0x501001b0;
div = 0x501001b4;
labs = 0x501001b8;
ldiv = 0x501001bc;
qsort = 0x501001c0;
atoi = 0x501001c4;
atol = 0x501001c8;
itoa = 0x501001cc;
utoa = 0x501001d0;

13
components/esp_rom/esp32p4/ld/esp32p4lp.rom.version.ld Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM version variables for esp32p4lp
*
* These addresses should be compatible with any ROM version for this chip.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
_rom_chip_id = 0x50100090;
_rom_eco_version = 0x50100094;

0
components/esp_rom/include/esp32p4/.gitkeep
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_AES_H_
#define _ROM_AES_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
#define AES_BLOCK_SIZE 16
enum AES_TYPE {
AES_ENC,
AES_DEC,
};
enum AES_BITS {
AES128,
AES192,
AES256
};
void ets_aes_enable(void);
void ets_aes_disable(void);
void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap,
bool in_word_swap, bool in_byte_swap,
bool out_word_swap, bool out_byte_swap);
int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits);
int ets_aes_setkey_enc(const void *key, enum AES_BITS bits);
int ets_aes_setkey_dec(const void *key, enum AES_BITS bits);
void ets_aes_block(const void *input, void *output);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_AES_H_ */

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_BIGINT_H_
#define _ROM_BIGINT_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
void ets_bigint_enable(void);
void ets_bigint_disable(void);
int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words);
int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words);
int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words);
void ets_bigint_wait_finish(void);
int ets_bigint_getz(uint32_t *z, uint32_t len_words);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_BIGINT_H_ */

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ROM_CRC_H
#define ROM_CRC_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup crc_apis, uart configuration and communication related apis
* @brief crc apis
*/
/** @addtogroup crc_apis
* @{
*/
/* Standard CRC8/16/32 algorithms. */
// CRC-8 x8+x2+x1+1 0x07
// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS
// CRC32:
//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
//If your buf is not continuous, you can use the first result to be the second parameter.
/**
* @brief Crc32 value that is in little endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc32 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc16 value that is in little endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc16 value that is in big endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc8 value that is in little endian.
*
* @param uint8_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc8 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#define ETS_DS_MAX_BITS 3072
#define ETS_DS_IV_LEN 16
/* Length of parameter 'C' stored in flash (not including IV)
Comprises encrypted Y, M, rinv, md (32), mprime (4), length (4), padding (8)
Note that if ETS_DS_MAX_BITS<4096, 'C' needs to be split up when writing to hardware
*/
#define ETS_DS_C_LEN ((ETS_DS_MAX_BITS * 3 / 8) + 32 + 8 + 8)
/* Encrypted ETS data. Recommended to store in flash in this format.
*/
typedef struct {
/* RSA LENGTH register parameters
* (number of words in RSA key & operands, minus one).
*
*
* This value must match the length field encrypted and stored in 'c',
* or invalid results will be returned. (The DS peripheral will
* always use the value in 'c', not this value, so an attacker can't
* alter the DS peripheral results this way, it will just truncate or
* extend the message and the resulting signature in software.)
*/
unsigned rsa_length;
/* IV value used to encrypt 'c' */
uint8_t iv[ETS_DS_IV_LEN];
/* Encrypted Digital Signature parameters. Result of AES-CBC encryption
of plaintext values. Includes an encrypted message digest.
*/
uint8_t c[ETS_DS_C_LEN];
} ets_ds_data_t;
typedef enum {
ETS_DS_OK,
ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */
ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */
ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */
ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */
} ets_ds_result_t;
void ets_ds_enable(void);
void ets_ds_disable(void);
/*
* @brief Start signing a message (or padded message digest) using the Digital Signature peripheral
*
* - @param message Pointer to message (or padded digest) containing the message to sign. Should be
* (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data
* in flash.
*
* Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling
* this function, and is responsible for calling ets_ds_finish_sign() and then
* ets_hmac_invalidate_downstream() afterwards.
*
* @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid,
* EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly.
*/
ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data);
/*
* @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign()
*
* A result of false indicates that a call to ets_ds_finish_sign() will not block.
*
* Only valid if ets_ds_enable() has been called.
*/
bool ets_ds_is_busy(void);
/* @brief Finish signing a message using the Digital Signature peripheral
*
* Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until
* peripheral is no longer busy.
*
* - @param signature Pointer to buffer to contain the signature. Should be
* (data->rsa_length + 1)*4 bytes long.
* - @param data Should match the 'data' parameter passed to ets_ds_start_sign()
*
* @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid,
* ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the
* encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a
* digest is produced anyhow.)
*/
ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data);
/* Plaintext parameters used by Digital Signature.
Not used for signing with DS peripheral, but can be encrypted
in-device by calling ets_ds_encrypt_params()
*/
typedef struct {
uint32_t Y[ETS_DS_MAX_BITS / 32];
uint32_t M[ETS_DS_MAX_BITS / 32];
uint32_t Rb[ETS_DS_MAX_BITS / 32];
uint32_t M_prime;
uint32_t length;
} ets_ds_p_data_t;
typedef enum {
ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */
ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */
} ets_ds_key_t;
/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral
*
* @param data Output buffer to store encrypted data, suitable for later use generating signatures.
* @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time.
* @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored.
* @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased.
* @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral)
*
* @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters.
*/
ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type);
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */
typedef enum {
ECDSA_CURVE_P192 = 1,
ECDSA_CURVE_P256 = 2
} ECDSA_CURVE;
int ets_ecdsa_verify(const uint8_t *key, const uint8_t *sig, ECDSA_CURVE curve_id, const uint8_t *digest, uint8_t *verified_digest);
#ifdef __cplusplus
}
#endif

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components/esp_rom/include/esp32p4/rom/efuse.h Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_EFUSE_H_
#define _ROM_EFUSE_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
/** \defgroup efuse_APIs efuse APIs
* @brief ESP32 efuse read/write APIs
* @attention
*
*/
/** @addtogroup efuse_APIs
* @{
*/
typedef enum {
ETS_EFUSE_KEY_PURPOSE_USER = 0,
ETS_EFUSE_KEY_PURPOSE_RESERVED = 1,
ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4,
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5,
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6,
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7,
ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8,
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9,
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10,
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11,
ETS_EFUSE_KEY_PURPOSE_MAX,
} ets_efuse_purpose_t;
typedef enum {
ETS_EFUSE_BLOCK0 = 0,
ETS_EFUSE_MAC_SPI_SYS_0 = 1,
ETS_EFUSE_BLOCK_SYS_PART1_DATA = 2,
ETS_EFUSE_BLOCK_USR_DATA = 3,
ETS_EFUSE_BLOCK_KEY0 = 4,
ETS_EFUSE_BLOCK_KEY1 = 5,
ETS_EFUSE_BLOCK_KEY2 = 6,
ETS_EFUSE_BLOCK_KEY3 = 7,
ETS_EFUSE_BLOCK_KEY4 = 8,
ETS_EFUSE_BLOCK_KEY5 = 9,
ETS_EFUSE_BLOCK_SYS_PART2_DATA = 10,
ETS_EFUSE_BLOCK_MAX,
} ets_efuse_block_t;
/**
* @brief set timing accroding the apb clock, so no read error or write error happens.
*
* @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M.
*
* @return : 0 if success, others if clock not accepted
*/
int ets_efuse_set_timing(uint32_t clock);
/**
* @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again.
*/
void ets_efuse_start(void);
/**
* @brief Efuse read operation: copies data from physical efuses to efuse read registers.
*
* @param null
*
* @return : 0 if success, others if apb clock is not accepted
*/
int ets_efuse_read(void);
/**
* @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time.
*
* @note This function does not update read efuses, call ets_efuse_read() once all programming is complete.
*
* @return : 0 if success, others if apb clock is not accepted
*/
int ets_efuse_program(ets_efuse_block_t block);
/**
* @brief Set all Efuse program registers to zero.
*
* Call this before writing new data to the program registers.
*/
void ets_efuse_clear_program_registers(void);
/**
* @brief Program a block of key data to an efuse block
*
* @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused).
* @param purpose Purpose to set for this key. Purpose must be already unset.
* @param data Pointer to data to write.
* @param data_len Length of data to write.
*
* @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose)
*/
int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len);
/* @brief Return the address of a particular efuse block's first read register
*
* @param block Index of efuse block to look up
*
* @return 0 if block is invalid, otherwise a numeric read register address
* of the first word in the block.
*/
uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block);
/**
* @brief Return the current purpose set for an efuse key block
*
* @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6.
*/
ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block);
/**
* @brief Find a key block with the particular purpose set
*
* @param purpose Purpose to search for.
* @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists.
* @return true if found, false if not found. If false, value at key_block pointer is unchanged.
*/
bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block);
/**
* Return true if the key block is unused, false otherwise.
*
* An unused key block is all zero content, not read or write protected,
* and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER)
*
* @param key_block key block to check.
*
* @return true if key block is unused, false if key block or used
* or the specified block index is not a key block.
*/
bool ets_efuse_key_block_unused(ets_efuse_block_t key_block);
/**
* @brief Search for an unused key block and return the first one found.
*
* See @ref ets_efuse_key_block_unused for a description of an unused key block.
*
* @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found.
*/
ets_efuse_block_t ets_efuse_find_unused_key_block(void);
/**
* @brief Return the number of unused efuse key blocks (0-6)
*/
unsigned ets_efuse_count_unused_key_blocks(void);
/**
* @brief Calculate Reed-Solomon Encoding values for a block of efuse data.
*
* @param data Pointer to data buffer (length 32 bytes)
* @param rs_values Pointer to write encoded data to (length 12 bytes)
*/
void ets_efuse_rs_calculate(const void *data, void *rs_values);
/**
* @brief Read spi flash pads configuration from Efuse
*
* @return
* - 0 for default SPI pins.
* - 1 for default HSPI pins.
* - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
* EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
* WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
*/
uint32_t ets_efuse_get_spiconfig(void);
/**
* @brief Read spi flash wp pad from Efuse
*
* @return
* - 0x3f for invalid.
* - 0~46 is valid.
*/
uint32_t ets_efuse_get_wp_pad(void);
/**
* @brief Read opi flash pads configuration from Efuse
*
* @return
* - 0 for default SPI pins.
* - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for:
* DQS, D4, D5, D6, D7 accordingly.
*/
uint32_t ets_efuse_get_opiconfig(void);
/**
* @brief Read if download mode disabled from Efuse
*
* @return
* - true for efuse disable download mode.
* - false for efuse doesn't disable download mode.
*/
bool ets_efuse_download_modes_disabled(void);
/**
* @brief Read if legacy spi flash boot mode disabled from Efuse
*
* @return
* - true for efuse disable legacy spi flash boot mode.
* - false for efuse doesn't disable legacy spi flash boot mode.
*/
bool ets_efuse_legacy_spi_boot_mode_disabled(void);
/**
* @brief Read if uart print control value from Efuse
*
* @return
* - 0 for uart force print.
* - 1 for uart print when GPIO8 is low when digital reset.
* 2 for uart print when GPIO8 is high when digital reset.
* 3 for uart force slient
*/
uint32_t ets_efuse_get_uart_print_control(void);
/**
* @brief Read if USB-Serial-JTAG print during rom boot is disabled from Efuse
*
* @return
* - 1 for efuse disable USB-Serial-JTAG print during rom boot.
* - 0 for efuse doesn't disable USB-Serial-JTAG print during rom boot.
*/
uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void);
/**
* @brief Read if usb download mode disabled from Efuse
*
* (Also returns true if security download mode is enabled, as this mode
* disables USB download.)
*
* @return
* - true for efuse disable usb download mode.
* - false for efuse doesn't disable usb download mode.
*/
bool ets_efuse_usb_download_mode_disabled(void);
/**
* @brief Read if tiny basic mode disabled from Efuse
*
* @return
* - true for efuse disable tiny basic mode.
* - false for efuse doesn't disable tiny basic mode.
*/
bool ets_efuse_tiny_basic_mode_disabled(void);
/**
* @brief Read if usb module disabled from Efuse
*
* @return
* - true for efuse disable usb module.
* - false for efuse doesn't disable usb module.
*/
bool ets_efuse_usb_module_disabled(void);
/**
* @brief Read if security download modes enabled from Efuse
*
* @return
* - true for efuse enable security download mode.
* - false for efuse doesn't enable security download mode.
*/
bool ets_efuse_security_download_modes_enabled(void);
/**
* @brief Return true if secure boot is enabled in EFuse
*/
bool ets_efuse_secure_boot_enabled(void);
/**
* @brief Return true if secure boot aggressive revoke is enabled in EFuse
*/
bool ets_efuse_secure_boot_aggressive_revoke_enabled(void);
/**
* @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse
*/
bool ets_efuse_cache_encryption_enabled(void);
/**
* @brief Return true if EFuse indicates an external phy needs to be used for USB
*/
bool ets_efuse_usb_use_ext_phy(void);
/**
* @brief Return true if EFuse indicates USB device persistence is disabled
*/
bool ets_efuse_usb_force_nopersist(void);
/**
* @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU
*/
bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void);
/**
* @brief Return true if EFuse indicates an opi flash is attached.
*/
bool ets_efuse_flash_opi_mode(void);
/**
* @brief Return true if EFuse indicates to send a flash resume command.
*/
bool ets_efuse_force_send_resume(void);
/**
* @brief return the time in us ROM boot need wait flash to power on from Efuse
*
* @return
* - uint32_t the time in us.
*/
uint32_t ets_efuse_get_flash_delay_us(void);
#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0
#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6
#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12
#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18
#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24
#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
/**
* @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into
* the JTAG_CTRL registers.
*
* Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse.
*
* Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match.
*
* @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user.
* @param key_block Index of a key block containing the source for this key.
*
* @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled.
*/
int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block);
/**
* @brief A crc8 algorithm used for MAC addresses in efuse
*
* @param unsigned char const *p : Pointer to original data.
*
* @param unsigned int len : Data length in byte.
*
* @return unsigned char: Crc value.
*/
unsigned char esp_crc8(unsigned char const *p, unsigned int len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_EFUSE_H_ */

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Note: Most of esp_flash APIs in ROM are compatible with headers in ESP-IDF, this function
just adds ROM-specific parts
*/
struct spi_flash_chip_t;
typedef struct esp_flash_t esp_flash_t;
/* Structure to wrap "global" data used by esp_flash in ROM */
typedef struct {
/* Default SPI flash chip, ie main chip attached to the MCU
This chip is used if the 'chip' argument passed to esp_flash_xxx API functions is ever NULL
*/
esp_flash_t *default_chip;
/* Global API OS notification start/end/chip_check functions
These are used by ROM if no other host functions are configured.
*/
struct {
esp_err_t (*start)(esp_flash_t *chip);
esp_err_t (*end)(esp_flash_t *chip, esp_err_t err);
esp_err_t (*chip_check)(esp_flash_t **inout_chip);
} api_funcs;
} esp_flash_rom_global_data_t;
/** Access a pointer to the global data used by the ROM spi_flash driver
*/
esp_flash_rom_global_data_t *esp_flash_get_rom_global_data(void);
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_ETS_SYS_H_
#define _ROM_ETS_SYS_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup ets_sys_apis, ets system related apis
* @brief ets system apis
*/
/** @addtogroup ets_sys_apis
* @{
*/
/************************************************************************
* NOTE
* Many functions in this header files can't be run in FreeRTOS.
* Please see the comment of the Functions.
* There are also some functions that doesn't work on FreeRTOS
* without listed in the header, such as:
* xtos functions start with "_xtos_" in ld file.
*
***********************************************************************
*/
/** \defgroup ets_apis, Espressif Task Scheduler related apis
* @brief ets apis
*/
/** @addtogroup ets_apis
* @{
*/
typedef enum {
ETS_OK = 0, /**< return successful in ets*/
ETS_FAILED = 1 /**< return failed in ets*/
} ETS_STATUS;
typedef ETS_STATUS ets_status_t;
typedef uint32_t ETSSignal;
typedef uint32_t ETSParam;
typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/
struct ETSEventTag {
ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/
ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/
};
typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/
typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/
/**
* @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it.
*
* @param none
*
* @return none
*/
void ets_run(void);
/**
* @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep.
*
* @param ets_idle_cb_t func : The callback function.
*
* @param void *arg : Argument of the callback.
*
* @return None
*/
void ets_set_idle_cb(ets_idle_cb_t func, void *arg);
/**
* @brief Init a task with processer, priority, queue to receive Event, queue length.
*
* @param ETSTask task : The task processer.
*
* @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task.
*
* @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used.
*
* @param uint8_t qlen : Queue length.
*
* @return None
*/
void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen);
/**
* @brief Post an event to an Task.
*
* @param uint8_t prio : Priority of the Task.
*
* @param ETSSignal sig : Event signal.
*
* @param ETSParam par : Event parameter
*
* @return ETS_OK : post successful
* @return ETS_FAILED : post failed
*/
ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
/**
* @}
*/
/** \defgroup ets_boot_apis, Boot routing related apis
* @brief ets boot apis
*/
/** @addtogroup ets_apis
* @{
*/
extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/
/**
* @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
* When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
*
* @param uint32_t start : the PRO Entry code address value in uint32_t
*
* @return None
*/
void ets_set_user_start(uint32_t start);
void ets_set_appcpu_boot_addr(uint32_t start);
/**
* @}
*/
/** \defgroup ets_printf_apis, ets_printf related apis used in ets
* @brief ets printf apis
*/
/** @addtogroup ets_printf_apis
* @{
*/
/**
* @brief Printf the strings to uart or other devices, similar with printf, simple than printf.
* Can not print float point data format, or longlong data format.
* So we maybe only use this in ROM.
*
* @param const char *fmt : See printf.
*
* @param ... : See printf.
*
* @return int : the length printed to the output device.
*/
int ets_printf(const char *fmt, ...);
/**
* @brief Get the uart channel of ets_printf(uart_tx_one_char).
*
* @return uint8_t uart channel used by ets_printf(uart_tx_one_char).
*/
uint8_t ets_get_printf_channel(void);
/**
* @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
* Can not print float point data format, or longlong data format
*
* @param char c : char to output.
*
* @return None
*/
void ets_write_char_uart(char c);
/**
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
* To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
*
* @param void (*)(char) p: Output function to install.
*
* @return None
*/
void ets_install_putc1(void (*p)(char c));
/**
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
* To install putc2, which is defaulted installed as NULL.
*
* @param void (*)(char) p: Output function to install.
*
* @return None
*/
void ets_install_putc2(void (*p)(char c));
/**
* @brief Install putc1 as ets_write_char_uart.
* In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
*
* @param None
*
* @return None
*/
void ets_install_uart_printf(void);
#define ETS_PRINTF(...) ets_printf(...)
#define ETS_ASSERT(v) do { \
if (!(v)) { \
ets_printf("%s %u \n", __FILE__, __LINE__); \
while (1) {}; \
} \
} while (0);
/**
* @}
*/
/** \defgroup ets_timer_apis, ets_timer related apis used in ets
* @brief ets timer apis
*/
/** @addtogroup ets_timer_apis
* @{
*/
typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
typedef struct _ETSTIMER_ {
struct _ETSTIMER_ *timer_next; /**< timer linker*/
uint32_t timer_expire; /**< abstruct time when timer expire*/
uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/
ETSTimerFunc *timer_func; /**< timer handler*/
void *timer_arg; /**< timer handler argument*/
} ETSTimer;
/**
* @brief Init ets timer, this timer range is 640 us to 429496 ms
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_timer_init(void);
/**
* @brief In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_timer_deinit(void);
/**
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param uint32_t tmout : Timer value in ms, range is 1 to 429496.
*
* @param bool repeat : Timer is periodic repeated.
*
* @return None
*/
void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
/**
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param uint32_t tmout : Timer value in us, range is 1 to 429496729.
*
* @param bool repeat : Timer is periodic repeated.
*
* @return None
*/
void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
/**
* @brief Disarm an ets timer.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @return None
*/
void ets_timer_disarm(ETSTimer *timer);
/**
* @brief Set timer callback and argument.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param ETSTimerFunc *pfunction : Timer callback.
*
* @param void *parg : Timer callback argument.
*
* @return None
*/
void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
/**
* @brief Unset timer callback and argument to NULL.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @return None
*/
void ets_timer_done(ETSTimer *ptimer);
/**
* @brief CPU do while loop for some time.
* In FreeRTOS task, please call FreeRTOS apis.
*
* @param uint32_t us : Delay time in us.
*
* @return None
*/
void ets_delay_us(uint32_t us);
/**
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
* Call this function when CPU frequency is changed.
*
* @param uint32_t ticks_per_us : CPU ticks per us.
*
* @return None
*/
void ets_update_cpu_frequency(uint32_t ticks_per_us);
/**
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
*
* @note This function only sets the tick rate for the current CPU. It is located in ROM,
* so the deep sleep stub can use it even if IRAM is not initialized yet.
*
* @param uint32_t ticks_per_us : CPU ticks per us.
*
* @return None
*/
void ets_update_cpu_frequency_rom(uint32_t ticks_per_us);
/**
* @brief Get the real CPU ticks per us to the ets.
* This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
*
* @param None
*
* @return uint32_t : CPU ticks per us record in ets.
*/
uint32_t ets_get_cpu_frequency(void);
/**
* @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store.
*
* @param None
*
* @return uint32_t : if stored in efuse(not 0)
* clock = ets_efuse_get_xtal_freq() * 1000000;
* else if analog_8M in efuse
* clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock();
* else clock = 40M.
*/
uint32_t ets_get_xtal_freq(void);
/**
* @brief Get the apb divior by xtal frequency.
* When any types of reset happen, the default value is 2.
*
* @param None
*
* @return uint32_t : 1 or 2.
*/
uint32_t ets_get_xtal_div(void);
/**
* @brief Get apb_freq value, If value not stored in RTC_STORE5, than store.
*
* @param None
*
* @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
* clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
* else store ets_get_detected_xtal_freq() in.
*/
uint32_t ets_get_apb_freq(void);
/**
* @}
*/
/** \defgroup ets_intr_apis, ets interrupt configure related apis
* @brief ets intr apis
*/
/** @addtogroup ets_intr_apis
* @{
*/
typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
/**
* @brief Attach a interrupt handler to a CPU interrupt number.
* This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param int i : CPU interrupt number.
*
* @param ets_isr_t func : Interrupt handler.
*
* @param void *arg : argument of the handler.
*
* @return None
*/
void ets_isr_attach(int i, ets_isr_t func, void *arg);
/**
* @brief Mask the interrupts which show in mask bits.
* This function equals to _xtos_ints_off(mask).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
*
* @return None
*/
void ets_isr_mask(uint32_t mask);
/**
* @brief Unmask the interrupts which show in mask bits.
* This function equals to _xtos_ints_on(mask).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
*
* @return None
*/
void ets_isr_unmask(uint32_t unmask);
/**
* @brief Lock the interrupt to level 2.
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_intr_lock(void);
/**
* @brief Unlock the interrupt to level 0.
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_intr_unlock(void);
/**
* @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt).
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_waiti0(void);
/**
* @brief Attach an CPU interrupt to a hardware source.
* We have 4 steps to use an interrupt:
* 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
* 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
* 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM);
* 4.Enable interrupt in the module.
*
* @param int cpu_no : The CPU which the interrupt number belongs.
*
* @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
*
* @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
*
* @return None
*/
void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
/**
* @}
*/
#ifndef MAC2STR
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
#endif
#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
typedef enum {
OK = 0,
FAIL,
PENDING,
BUSY,
CANCEL,
} STATUS;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_ETS_SYS_H_ */

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/gpio_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup gpio_apis, uart configuration and communication related apis
* @brief gpio apis
*/
/** @addtogroup gpio_apis
* @{
*/
#define GPIO_REG_READ(reg) READ_PERI_REG(reg)
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
#define GPIO_ID_PIN0 0
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
#define GPIO_FUNC_IN_HIGH 0x38
#define GPIO_FUNC_IN_LOW 0x3C
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
typedef enum {
GPIO_PIN_INTR_DISABLE = 0,
GPIO_PIN_INTR_POSEDGE = 1,
GPIO_PIN_INTR_NEGEDGE = 2,
GPIO_PIN_INTR_ANYEDGE = 3,
GPIO_PIN_INTR_LOLEVEL = 4,
GPIO_PIN_INTR_HILEVEL = 5
} GPIO_INT_TYPE;
#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
((gpio_no < 32) ? gpio_output_set(bit_value<<gpio_no, (bit_value ? 0 : 1)<<gpio_no, 1<<gpio_no,0) : \
gpio_output_set_high(bit_value<<(gpio_no - 32), (bit_value ? 0 : 1)<<(gpio_no - 32), 1<<(gpio_no -32),0))
#define GPIO_DIS_OUTPUT(gpio_no) ((gpio_no < 32) ? gpio_output_set(0,0,0, 1<<gpio_no) : gpio_output_set_high(0,0,0, 1<<(gpio_no - 32)))
#define GPIO_INPUT_GET(gpio_no) ((gpio_no < 32) ? ((gpio_input_get()>>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0))
/* GPIO interrupt handler, registered through gpio_intr_handler_register */
typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg);
/**
* @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet
* to initialize "output enables" and pin configurations for each gpio pin.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void gpio_init(void);
/**
* @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
* @param uint32_t set_mask : the gpios that need high level.
*
* @param uint32_t clear_mask : the gpios that need low level.
*
* @param uint32_t enable_mask : the gpios that need be changed.
*
* @param uint32_t disable_mask : the gpios that need diable output.
*
* @return None
*/
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
* @param uint32_t set_mask : the gpios that need high level.
*
* @param uint32_t clear_mask : the gpios that need low level.
*
* @param uint32_t enable_mask : the gpios that need be changed.
*
* @param uint32_t disable_mask : the gpios that need diable output.
*
* @return None
*/
void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Sample the value of GPIO input pins(0-31) and returns a bitmask.
*
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
*/
uint32_t gpio_input_get(void);
/**
* @brief Sample the value of GPIO input pins(32-39) and returns a bitmask.
*
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32.
*/
uint32_t gpio_input_get_high(void);
/**
* @brief Register an application-specific interrupt handler for GPIO pin interrupts.
* Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack.
* Please do not call this function in SDK.
*
* @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler
*
* @param void *arg : gpio application-specific interrupt handler argument.
*
* @return None
*/
void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg);
/**
* @brief Get gpio interrupts which happens but not processed.
* Please do not call this function in SDK.
*
* @param None
*
* @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0.
*/
uint32_t gpio_intr_pending(void);
/**
* @brief Get gpio interrupts which happens but not processed.
* Please do not call this function in SDK.
*
* @param None
*
* @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32.
*/
uint32_t gpio_intr_pending_high(void);
/**
* @brief Ack gpio interrupts to process pending interrupts.
* Please do not call this function in SDK.
*
* @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0.
*
* @return None
*/
void gpio_intr_ack(uint32_t ack_mask);
/**
* @brief Ack gpio interrupts to process pending interrupts.
* Please do not call this function in SDK.
*
* @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32.
*
* @return None
*/
void gpio_intr_ack_high(uint32_t ack_mask);
/**
* @brief Set GPIO to wakeup the ESP32.
* Please do not call this function in SDK.
*
* @param uint32_t i: gpio number.
*
* @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
*
* @return None
*/
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
/**
* @brief disable GPIOs to wakeup the ESP32.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
*
* @param uint32_t gpio : gpio number, 0~0x2f
* gpio == 0x3C, input 0 to signal
* gpio == 0x3A, input nothing to signal
* gpio == 0x38, input 1 to signal
*
* @param uint32_t signal_idx : signal index.
*
* @param bool inv : the signal is inv or not
*
* @return None
*/
void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
*
* @param uint32_t gpio : gpio number, 0~0x2f
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x100, cancel output put to the gpio
*
* @param bool out_inv : the signal output is invert or not
*
* @param bool oen_inv : the signal output enable is invert or not
*
* @return None
*/
void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
/**
* @brief Select pad as a gpio function from IOMUX.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_select_gpio(uint32_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @param uint32_t drv : 0-3
*
* @return None
*/
void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
/**
* @brief Pull up the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_pullup(uint32_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_pulldown(uint32_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_unhold(uint32_t gpio_num);
/**
* @brief Hold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_hold(uint32_t gpio_num);
/**
* @brief enable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_input_enable(uint32_t gpio_num);
/**
* @brief disable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_input_disable(uint32_t gpio_num);
/**
* @}
*/
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_HMAC_H_
#define _ROM_HMAC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdlib.h>
#include "efuse.h"
void ets_hmac_enable(void);
void ets_hmac_disable(void);
/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP)
to digest a message.
*/
int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac);
/* Calculate a downstream HMAC message to temporarily enable JTAG, or
to generate a Digital Signature data decryption key.
- purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE
or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG
- key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6.
This efuse block must have the corresponding purpose set in "purpose", or
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL.
The result of this HMAC calculation is only made available "downstream" to the
corresponding hardware module, and cannot be accessed by software.
*/
int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose);
/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream().
*
* - purpose must match a previous call to ets_hmac_calculate_downstream().
*
* After this function is called, the corresponding internal operation (JTAG or DS) will no longer
* have access to the generated key.
*/
int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose);
#ifdef __cplusplus
}
#endif
#endif // _ROM_HMAC_H_

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_LIBC_STUBS_H_
#define _ROM_LIBC_STUBS_H_
#include <sys/lock.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <stdarg.h>
#include <reent.h>
#include <errno.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
ESP32-C6 ROM code contains implementations of some of C library functions.
Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
implementation defined in the following struct.
The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to
set the address
So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
application must allocate syscall table structure for each CPU being used, and populate it with pointers
to actual implementations of corresponding syscalls.
*/
struct syscall_stub_table {
struct _reent *(*__getreent)(void);
void *(*_malloc_r)(struct _reent *r, size_t);
void (*_free_r)(struct _reent *r, void *);
void *(*_realloc_r)(struct _reent *r, void *, size_t);
void *(*_calloc_r)(struct _reent *r, size_t, size_t);
void (*_abort)(void);
int (*_system_r)(struct _reent *r, const char *);
int (*_rename_r)(struct _reent *r, const char *, const char *);
clock_t (*_times_r)(struct _reent *r, struct tms *);
int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
void (*_raise_r)(struct _reent *r);
int (*_unlink_r)(struct _reent *r, const char *);
int (*_link_r)(struct _reent *r, const char *, const char *);
int (*_stat_r)(struct _reent *r, const char *, struct stat *);
int (*_fstat_r)(struct _reent *r, int, struct stat *);
void *(*_sbrk_r)(struct _reent *r, ptrdiff_t);
int (*_getpid_r)(struct _reent *r);
int (*_kill_r)(struct _reent *r, int, int);
void (*_exit_r)(struct _reent *r, int);
int (*_close_r)(struct _reent *r, int);
int (*_open_r)(struct _reent *r, const char *, int, int);
int (*_write_r)(struct _reent *r, int, const void *, int);
int (*_lseek_r)(struct _reent *r, int, int, int);
int (*_read_r)(struct _reent *r, int, void *, int);
void (*_retarget_lock_init)(_LOCK_T *lock);
void (*_retarget_lock_init_recursive)(_LOCK_T *lock);
void (*_retarget_lock_close)(_LOCK_T lock);
void (*_retarget_lock_close_recursive)(_LOCK_T lock);
void (*_retarget_lock_acquire)(_LOCK_T lock);
void (*_retarget_lock_acquire_recursive)(_LOCK_T lock);
int (*_retarget_lock_try_acquire)(_LOCK_T lock);
int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock);
void (*_retarget_lock_release)(_LOCK_T lock);
void (*_retarget_lock_release_recursive)(_LOCK_T lock);
int (*_printf_float)(struct _reent *data, void *pdata, FILE *fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list *ap);
int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
void (*__assert_func) (const char *file, int line, const char *func, const char *failedexpr) __attribute__((noreturn));
void (*__sinit) (struct _reent *r);
void (*_cleanup_r) (struct _reent *r);
};
extern struct syscall_stub_table *syscall_table_ptr;
#ifdef __cplusplus
} // extern "C"
#endif
#endif /* _ROM_LIBC_STUBS_H_ */

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_LLDESC_H_
#define _ROM_LLDESC_H_
#include <stdint.h>
#include "sys/queue.h"
#include "esp_rom_lldesc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define LLDESC_TX_MBLK_SIZE 268 /* */
#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */
#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/
#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/
#ifdef ESP_MAC_5
#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */
#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12
#else
#ifdef SBUF_RXTX
#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */
#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */
#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */
#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */
#endif
#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */
#ifdef IEEE80211_RX_AMPDU
#define LLDESC_RX_MBLK_NUM 30
#else
#define LLDESC_RX_MBLK_NUM 10
#endif /*IEEE80211_RX_AMPDU*/
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8
#endif /* !ESP_MAC_5 */
typedef struct tx_ampdu_entry_s {
uint32_t sub_len : 12,
dili_num : 7,
: 1,
null_byte: 2,
data : 1,
enc : 1,
seq : 8;
} tx_ampdu_entry_t;
typedef struct lldesc_chain_s {
lldesc_t *head;
lldesc_t *tail;
} lldesc_chain_t;
#ifdef SBUF_RXTX
enum sbuf_mask_s {
SBUF_MOVE_NO = 0,
SBUF_MOVE_TX2RX,
SBUF_MOVE_RX2TX,
} ;
#define SBUF_MOVE_STEP 8
#endif
#define LLDESC_SIZE sizeof(struct lldesc_s)
/* SLC Descriptor */
#define LLDESC_OWNER_MASK 0x80000000
#define LLDESC_OWNER_SHIFT 31
#define LLDESC_SW_OWNED 0
#define LLDESC_HW_OWNED 1
#define LLDESC_EOF_MASK 0x40000000
#define LLDESC_EOF_SHIFT 30
#define LLDESC_SOSF_MASK 0x20000000
#define LLDESC_SOSF_SHIFT 29
#define LLDESC_LENGTH_MASK 0x00fff000
#define LLDESC_LENGTH_SHIFT 12
#define LLDESC_SIZE_MASK 0x00000fff
#define LLDESC_SIZE_SHIFT 0
#define LLDESC_ADDR_MASK 0x000fffff
void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t *mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner,
lldesc_t **head,
#ifdef TO_HOST_RESTART
lldesc_t **one_before_tail,
#endif
lldesc_t **tail);
lldesc_t *lldesc_num2link(lldesc_t *head, uint16_t nblks);
lldesc_t *lldesc_set_owner(lldesc_t *head, uint16_t nblks, uint8_t owner);
static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
{
lldesc_t *ds = head;
uint32_t len = 0;
while (ds) {
len += ds->length;
ds = STAILQ_NEXT(ds, qe);
}
return len;
}
static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
{
ds->owner = owner;
ds->eof = eof;
ds->sosf = sosf;
ds->length = len;
}
#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \
(_desc)->owner = (_owner); \
(_desc)->eof = (_eof); \
(_desc)->sosf = (_sosf); \
(_desc)->length = (_len); \
} while(0)
#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
#ifdef __cplusplus
}
#endif
#endif /* _ROM_LLDESC_H_ */

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/*
* SPDX-FileCopyrightText: 2003-2005, Jouni Malinen <j@w1.fi>
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* MD5 internal definitions
* Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Alternatively, this software may be distributed under the terms of BSD
* license.
*
* See README and COPYING for more details.
*/
#ifndef _ROM_MD5_HASH_H_
#define _ROM_MD5_HASH_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
struct MD5Context {
uint32_t buf[4];
uint32_t bits[2];
uint8_t in[64];
};
void MD5Init(struct MD5Context *context);
void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len);
void MD5Final(unsigned char digest[16], struct MD5Context *context);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_MD5_HASH_H_ */

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_OPI_FLASH_H_
#define _ROM_OPI_FLASH_H_
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include <stdbool.h>
#include "spi_flash.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint8_t mode;
uint8_t cmd_bit_len;
uint16_t cmd;
uint32_t addr;
uint8_t addr_bit_len;
uint8_t dummy_bit_len;
uint8_t data_bit_len;
uint8_t cs_sel: 4;
uint8_t is_pe: 4;
} esp_rom_opiflash_cmd_t;
typedef struct {
uint8_t addr_bit_len;
uint8_t dummy_bit_len;
uint16_t cmd;
uint8_t cmd_bit_len;
uint8_t var_dummy_en;
} esp_rom_opiflash_spi0rd_t;
typedef struct {
esp_rom_opiflash_cmd_t rdid;
esp_rom_opiflash_cmd_t rdsr;
esp_rom_opiflash_cmd_t wren;
esp_rom_opiflash_cmd_t se;
esp_rom_opiflash_cmd_t be64k;
esp_rom_opiflash_cmd_t read;
esp_rom_opiflash_cmd_t pp;
esp_rom_opiflash_spi0rd_t cache_rd_cmd;
bool usr_ecc_en;
} esp_rom_opiflash_def_t;
typedef struct {
uint16_t cmd; /*!< Command value */
uint16_t cmdBitLen; /*!< Command byte length*/
uint32_t *addr; /*!< Point to address value*/
uint32_t addrBitLen; /*!< Address byte length*/
uint32_t *txData; /*!< Point to send data buffer*/
uint32_t txDataBitLen; /*!< Send data byte length.*/
uint32_t *rxData; /*!< Point to recevie data buffer*/
uint32_t rxDataBitLen; /*!< Recevie Data byte length.*/
uint32_t dummyBitLen;
} esp_rom_spi_cmd_t;
#define ESP_ROM_OPIFLASH_MUX_TAKE()
#define ESP_ROM_OPIFLASH_MUX_GIVE()
#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0))
#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1))
// Definition of MX25UM25645G Octa Flash
// SPI status register
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
#define FLASH_OP_MODE_RDCMD_DOUT 0x3B
#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000
#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000
#define ESP_ROM_FLASH_PAGE_SIZE 256
// FLASH commands
#define ROM_FLASH_CMD_RDID 0x9F
#define ROM_FLASH_CMD_WRSR 0x01
#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
#define ROM_FLASH_CMD_WREN 0x06
#define ROM_FLASH_CMD_WRDI 0x04
#define ROM_FLASH_CMD_RDSR 0x05
#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
#define ROM_FLASH_CMD_ERASE_SEC 0x20
#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52
#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8
#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */
#define ROM_FLASH_CMD_RSTEN 0x66
#define ROM_FLASH_CMD_RST 0x99
#define ROM_FLASH_CMD_SE4B 0x21
#define ROM_FLASH_CMD_SE4B_OCT 0xDE21
#define ROM_FLASH_CMD_BE4B 0xDC
#define ROM_FLASH_CMD_BE4B_OCT 0x23DC
#define ROM_FLASH_CMD_RSTEN_OCT 0x9966
#define ROM_FLASH_CMD_RST_OCT 0x6699
#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC
#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE
#define ROM_FLASH_CMD_FSTRD4B 0x0C
#define ROM_FLASH_CMD_PP4B 0x12
#define ROM_FLASH_CMD_PP4B_OCT 0xED12
#define ROM_FLASH_CMD_RDID_OCT 0x609F
#define ROM_FLASH_CMD_WREN_OCT 0xF906
#define ROM_FLASH_CMD_RDSR_OCT 0xFA05
#define ROM_FLASH_CMD_RDCR2 0x71
#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71
#define ROM_FLASH_CMD_WRCR2 0x72
#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72
// Definitions for GigaDevice GD25LX256E Flash
#define ROM_FLASH_CMD_RDFSR_GD 0x70
#define ROM_FLASH_CMD_RD_GD 0x03
#define ROM_FLASH_CMD_RD4B_GD 0x13
#define ROM_FLASH_CMD_FSTRD_GD 0x0B
#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C
#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B
#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C
#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB
#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC
#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD
#define ROM_FLASH_CMD_PP_GD 0x02
#define ROM_FLASH_CMD_PP4B_GD 0x12
#define ROM_FLASH_CMD_PP_OOUT_GD 0x82
#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84
#define ROM_FLASH_CMD_PP_OIO_GD 0xC2
#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E
#define ROM_FLASH_CMD_SE_GD 0x20
#define ROM_FLASH_CMD_SE4B_GD 0x21
#define ROM_FLASH_CMD_BE32K_GD 0x52
#define ROM_FLASH_CMD_BE32K4B_GD 0x5C
#define ROM_FLASH_CMD_BE64K_GD 0xD8
#define ROM_FLASH_CMD_BE64K4B_GD 0xDC
#define ROM_FLASH_CMD_EN4B_GD 0xB7
#define ROM_FLASH_CMD_DIS4B_GD 0xE9
extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def;
/**
* @brief init legacy driver for Octal Flash
*/
void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t *flash_cmd_def);
// spi user mode command config
/**
* @brief Config the spi user command
* @param spi_num spi port
* @param pcmd pointer to accept the spi command struct
*/
void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd);
/**
* @brief Start a spi user command sequence
* @param spi_num spi port
* @param rx_buf buffer pointer to receive data
* @param rx_len receive data length in byte
* @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
* @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission
*/
void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase);
/**
* @brief Config opi flash pads according to efuse settings.
*/
void esp_rom_opiflash_pin_config(void);
// set SPI read/write mode
/**
* @brief Set SPI operation mode
* @param spi_num spi port
* @param mode Flash Read Mode
*/
void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
/**
* @brief Set data swap mode in DTR(DDR) mode
* @param spi_num spi port
* @param wr_swap to decide whether to swap fifo data in dtr write operation
* @param rd_swap to decide whether to swap fifo data in dtr read operation
*/
void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap);
/**
* @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
* @param spi_num spi port
*/
void esp_rom_opiflash_mode_reset(int spi_num);
/**
* @brief To execute a flash operation command
* @param spi_num spi port
* @param mode Flash Read Mode
* @param cmd data to send in command field
* @param cmd_bit_len bit length of command field
* @param addr data to send in address field
* @param addr_bit_len bit length of address field
* @param dummy_bits bit length of dummy field
* @param mosi_data data buffer to be sent in mosi field
* @param mosi_bit_len bit length of data buffer to be sent in mosi field
* @param miso_data data buffer to accept data in miso field
* @param miso_bit_len bit length of data buffer to accept data in miso field
* @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1
* @param is_write_erase_operation to indicate whether this a write or erase flash operation
*/
void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode,
uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len,
int dummy_bits,
uint8_t* mosi_data, int mosi_bit_len,
uint8_t* miso_data, int miso_bit_len,
uint32_t cs_mask,
bool is_write_erase_operation);
/**
* @brief send reset command to opi flash
* @param spi_num spi port
* @param mode Flash Operation Mode
*/
void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode);
/**
* @brief to read opi flash ID
* @note command format would be defined in initialization
* @param[out] out_id buffer to accept id
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *out_id);
/**
* @brief to read opi flash status register
* @note command format would be defined in initialization
* @return opi flash status value
*/
uint8_t esp_rom_opiflash_rdsr(void);
/**
* @brief wait opi flash status register to be idle
* @note command format would be defined in initialization
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(void);
/**
* @brief to erase flash sector
* @note command format would be defined in initialization
* @param sector_num the sector to be erased
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(uint32_t sector_num);
/**
* @brief to erase flash block
* @note command format would be defined in initialization
* @param block_num the block to be erased
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(uint32_t block_num);
/**
* @brief to erase a flash area define by start address and length
* @note command format would be defined in initialization
* @param start_addr the start address to be erased
* @param area_len the erea length to be erased
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr, uint32_t area_len);
/**
* @brief to read data from opi flash
* @note command format would be defined in initialization
* @param flash_addr flash address to read data from
* @param data_addr data buffer to accept the data
* @param len data length to be read
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr, void *data_addr, int len);
/**
* @brief to write data to opi flash
* @note command format would be defined in initialization
* @param flash_addr flash address to write data to
* @param data_addr data buffer to write to flash
* @param len data length to write
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr, const uint32_t *data_addr, int len);
/**
* @brief send WREN command
* @note command format would be defined in initialization
* @param arg not used, set to NULL
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_wren(void* arg);
/**
* @brief to configure SPI0 read flash command format for cache
* @note command format would be defined in initialization
*
*/
void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const esp_rom_opiflash_spi0rd_t *cache);
esp_rom_spiflash_result_t esp_rom_opiflash_read_raw(uint32_t flash_addr, uint8_t* buf, int len);
#ifdef __cplusplus
}
#endif
#endif

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define SUPPORT_BTDM 0
#define SUPPORT_BTBB 0
#define SUPPORT_WIFI 0
#define SUPPORT_USB_DWCOTG 1
#define SUPPORT_COEXIST 0
#define SUPPORT_MBEDTLS 0
/* Structure and functions for returning ROM global layout
*
* This is for address symbols defined in the linker script, which may change during ECOs.
*/
typedef struct {
void *dram0_stack_shared_mem_start;
void *dram0_rtos_reserved_start;
void *stack_sentry;
void *stack;
#if (CORE_NUM == 2)
void *stack_sentry_app;
void *stack_app;
#endif
#if SUPPORT_BTDM
void *data_start_btdm;
void *data_end_btdm;
void *bss_start_btdm;
void *bss_end_btdm;
void *data_start_btdm_rom;
void *data_start_interface_btdm;
void *data_end_interface_btdm;
void *bss_start_interface_btdm;
void *bss_end_interface_btdm;
#endif
#if SUPPORT_BTBB
void *dram_start_btbbrom;
void *dram_end_btbbrom;
#endif
#if SUPPORT_BTDM || SUPPORT_WIFI
void *dram_start_phyrom;
void *dram_end_phyrom;
#endif
#if SUPPORT_WIFI
void *dram_start_net80211;
void *dram_end_net80211;
void *data_start_interface_net80211;
void *data_end_interface_net80211;
void *bss_start_interface_net80211;
void *bss_end_interface_net80211;
void *dram_start_pp;
void *dram_end_pp;
void *data_start_interface_pp;
void *data_end_interface_pp;
void *bss_start_interface_pp;
void *bss_end_interface_pp;
#endif
#if SUPPORT_COEXIST
void *dram_start_coexist;
void *dram_end_coexist;
void *data_start_interface_coexist;
void *data_end_interface_coexist;
void *bss_start_interface_coexist;
void *bss_end_interface_coexist;
#endif
#if SUPPORT_MBEDTLS
void *dram_start_mbedtls_rom;
void *dram_end_mbedtls_rom;
#endif
#if SUPPORT_USB_DWCOTG
void *dram_start_usb_dwcotg_rom;
void *dram_end_usb_dwcotg_rom;
#endif
void *dram_start_uart_rom;
void *dram_end_uart_rom;
} ets_rom_layout_t;
extern const ets_rom_layout_t *const ets_rom_layout_p;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_RSA_PSS_H_
#define _ROM_RSA_PSS_H_
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
#define ETS_SIG_LEN 384 /* Bytes */
#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */
typedef struct {
uint8_t n[384]; /* Public key modulus */
uint32_t e; /* Public key exponent */
uint8_t rinv[384];
uint32_t mdash;
} ets_rsa_pubkey_t;
bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest);
void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask);
bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash);
#ifdef __cplusplus
}
#endif
#endif

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <stdint.h>
#include "esp_assert.h"
#include "soc/soc.h"
#include "soc/lp_system_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup rtc_apis, rtc registers and memory related apis
* @brief rtc apis
*/
/** @addtogroup rtc_apis
* @{
*/
/**************************************************************************************
* Note: *
* Some Rtc memory and registers are used, in ROM or in internal library. *
* Please do not use reserved or used rtc memory or registers. *
* *
*************************************************************************************
* LP Memory & Store Register usage
*************************************************************************************
* rtc memory addr type size usage
* 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
* 0x3f421000+SIZE_CP Slow 8192-SIZE_CP
*
* 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code
*
*************************************************************************************
* RTC store registers usage
* RTC_CNTL_STORE0_REG Reserved
* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
* RTC_CNTL_STORE2_REG Boot time, low word
* RTC_CNTL_STORE3_REG Boot time, high word
* RTC_CNTL_STORE4_REG External XTAL frequency
* RTC_CNTL_STORE5_REG APB bus frequency
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
*************************************************************************************
*/
#define RTC_SLOW_CLK_CAL_REG LP_SYSTEM_REG_LP_STORE1_REG
#define RTC_BOOT_TIME_LOW_REG LP_SYSTEM_REG_LP_STORE2_REG
#define RTC_BOOT_TIME_HIGH_REG LP_SYSTEM_REG_LP_STORE3_REG
#define RTC_XTAL_FREQ_REG LP_SYSTEM_REG_LP_STORE4_REG
#define RTC_APB_FREQ_REG LP_SYSTEM_REG_LP_STORE5_REG
#define RTC_ENTRY_ADDR_REG LP_SYSTEM_REG_LP_STORE6_REG
#define RTC_RESET_CAUSE_REG LP_SYSTEM_REG_LP_STORE6_REG
#define RTC_MEMORY_CRC_REG LP_SYSTEM_REG_LP_STORE7_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
typedef enum {
AWAKE = 0, //<CPU ON
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
} SLEEP_MODE;
typedef enum {
NO_MEAN = 0,
POWERON_RESET = 1, /**<1, Vbat power on reset*/
RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core (hp system)*/
DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core (hp system)*/
SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core (hp system)*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core (hp system)*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core (hp system)*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core (hp system)*/
TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
EFUSE_RESET = 20, /**<20, efuse reset digital core (hp system)*/
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core (hp system)*/
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core (hp system)*/
JTAG_RESET = 24, /**<24, jtag reset CPU*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
// ESP32P4-TODO
//_Static_assert((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
//_Static_assert((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
//_Static_assert((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
typedef enum {
NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0,
EXT_EVENT1_TRIG = BIT1,
GPIO_TRIG = BIT2,
TIMER_EXPIRE = BIT3,
SDIO_TRIG = BIT4,
MAC_TRIG = BIT5,
UART0_TRIG = BIT6,
UART1_TRIG = BIT7,
TOUCH_TRIG = BIT8,
SAR_TRIG = BIT9,
BT_TRIG = BIT10,
RISCV_TRIG = BIT11,
XTAL_DEAD_TRIG = BIT12,
RISCV_TRAP_TRIG = BIT13,
USB_TRIG = BIT14
} WAKEUP_REASON;
typedef enum {
DISEN_WAKEUP = NO_SLEEP,
EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
GPIO_TRIG_EN = GPIO_TRIG,
TIMER_EXPIRE_EN = TIMER_EXPIRE,
SDIO_TRIG_EN = SDIO_TRIG,
MAC_TRIG_EN = MAC_TRIG,
UART0_TRIG_EN = UART0_TRIG,
UART1_TRIG_EN = UART1_TRIG,
TOUCH_TRIG_EN = TOUCH_TRIG,
SAR_TRIG_EN = SAR_TRIG,
BT_TRIG_EN = BT_TRIG,
RISCV_TRIG_EN = RISCV_TRIG,
XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG,
RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG,
USB_TRIG_EN = USB_TRIG
} WAKEUP_ENABLE;
/**
* @brief Get the reset reason for CPU.
*
* @param int cpu_no : CPU no.
*
* @return RESET_REASON
*/
RESET_REASON rtc_get_reset_reason(int cpu_no);
/**
* @brief Get the wakeup cause for CPU.
*
* @param int cpu_no : CPU no.
*
* @return WAKEUP_REASON
*/
WAKEUP_REASON rtc_get_wakeup_cause(void);
/**
* @brief Suppress ROM log by setting specific RTC control register.
* @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
*
* @param None
*
* @return None
*/
static inline void rtc_suppress_rom_log(void)
{
/* To disable logging in the ROM, only the least significant bit of the register is used,
* but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
* you need to write to this register in the same format.
* Namely, the upper 16 bits and lower should be the same.
*/
// REG_SET_BIT(LP_SYS_LP_STORE4_REG, RTC_DISABLE_ROM_LOG);
abort();
}
/**
* @brief Software Reset digital core.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*
* @param None
*
* @return None
*/
void software_reset(void);
/**
* @brief Software Reset digital core.
*
* It is not recommended to use this function in esp-idf, use
* esp_restart() instead.
*
* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
*
* @return None
*/
void software_reset_cpu(int cpu_no);
/**
* @}
*/
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "ets_sys.h"
#include "ecdsa.h"
#include "rsa_pss.h"
#include "esp_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#if CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT
typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t;
typedef struct ets_secure_boot_signature ets_secure_boot_signature_t;
typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t;
/* Anti-FI measure: use full words for success/fail, instead of
0/non-zero
*/
typedef enum {
SB_SUCCESS = 0x3A5A5AA5,
SB_FAILED = 0x7533885E,
} ets_secure_boot_status_t;
/* Verify bootloader image (reconfigures cache to map),
with key digests provided as parameters.)
Can be used to verify secure boot status before enabling
secure boot permanently.
If stage_load parameter is true, bootloader is copied into staging
buffer in RAM at the same time.
If result is SB_SUCCESS, the "simple hash" of the bootloader is
copied into verified_hash.
*/
ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load);
/* Read key digests from efuse. Any revoked/missing digests will be
marked as NULL
*/
ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys);
/* Verify supplied signature against supplied digest, using
supplied trusted key digests.
Doesn't reconfigure cache or any other hardware access except for RSA peripheral.
If result is SB_SUCCESS, the image_digest value is copied into verified_digest.
*/
ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest);
/* Revoke a public key digest in efuse.
@param index Digest to revoke. Must be 0, 1 or 2.
*/
void ets_secure_boot_revoke_public_key_digest(int index);
#define CRC_SIGN_BLOCK_LEN 1196
#define SIG_BLOCK_PADDING 4096
#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7
/* Secure Boot V2 signature block
(Up to 3 in a signature sector are appended to the image)
*/
#if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME
struct ets_secure_boot_sig_block {
uint8_t magic_byte;
uint8_t version;
uint8_t _reserved1;
uint8_t _reserved2;
uint8_t image_digest[32];
ets_rsa_pubkey_t key;
uint8_t signature[384];
uint32_t block_crc;
uint8_t _padding[16];
};
#elif CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME
struct __attribute((packed)) ets_secure_boot_sig_block {
uint8_t magic_byte;
uint8_t version;
uint8_t _reserved1;
uint8_t _reserved2;
uint8_t image_digest[32];
struct {
struct {
uint8_t curve_id; /* ETS_ECDSA_CURVE_P192 / ETS_ECDSA_CURVE_P256 */
uint8_t point[64]; /* X followed by Y (both little-endian), plus zero bytes if P192 */
} key;
uint8_t signature[64]; /* r followed by s (both little-endian) */
uint8_t padding[1031];
} ecdsa;
uint32_t block_crc; /* note: crc covers all bytes in the structure before it, regardless of version field */
uint8_t _padding[16];
};
#endif
ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size");
#define SECURE_BOOT_NUM_BLOCKS 3
/* V2 Secure boot signature sector (up to 3 blocks) */
struct ets_secure_boot_signature {
ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS];
uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)];
};
ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size");
#define MAX_KEY_DIGESTS 3
struct ets_secure_boot_key_digests {
const void *key_digests[MAX_KEY_DIGESTS];
bool allow_key_revoke;
};
#endif /* CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT */
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SHA_H_
#define _ROM_SHA_H_
#include <stdint.h>
#include <stdbool.h>
#include "ets_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SHA1 = 0,
SHA2_224,
SHA2_256,
SHA_TYPE_MAX
} SHA_TYPE;
typedef struct SHAContext {
bool start;
bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved
SHA_TYPE type;
uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16
unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128
uint32_t total_bits[4];
} SHA_CTX;
void ets_sha_enable(void);
void ets_sha_disable(void);
ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type);
ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t);
void ets_sha_get_state(SHA_CTX *ctx);
void ets_sha_process(SHA_CTX *ctx, const unsigned char *input);
void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx);
ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SHA_H_ */

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1)
#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1)
#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1)
#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1)
#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1)
#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1)
#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1)
#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1)
#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1)
#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1)
#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1)
#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1)
#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1)
#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1)
#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1)
#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1)
#define SPI0_R_QIO_DUMMY_CYCLELEN 5
#define SPI0_R_QIO_ADDR_BITSLEN 23
#define SPI0_R_FAST_DUMMY_CYCLELEN 7
#define SPI0_R_DIO_DUMMY_CYCLELEN 3
#define SPI0_R_FAST_ADDR_BITSLEN 23
#define SPI0_R_SIO_ADDR_BITSLEN 23
#define SPI1_R_QIO_DUMMY_CYCLELEN 5
#define SPI1_R_QIO_ADDR_BITSLEN 23
#define SPI1_R_FAST_DUMMY_CYCLELEN 7
#define SPI1_R_DIO_DUMMY_CYCLELEN 3
#define SPI1_R_DIO_ADDR_BITSLEN 23
#define SPI1_R_FAST_ADDR_BITSLEN 23
#define SPI1_R_SIO_ADDR_BITSLEN 23
#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23
#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B
//SPI address register
#define ESP_ROM_SPIFLASH_BYTES_LEN 24
#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf
typedef void (* spi_flash_func_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t);
typedef struct {
uint8_t pp_addr_bit_len;
uint8_t se_addr_bit_len;
uint8_t be_addr_bit_len;
uint8_t rd_addr_bit_len;
uint32_t read_sub_len;
uint32_t write_sub_len;
spi_flash_op_t unlock;
spi_flash_erase_t erase_sector;
spi_flash_erase_t erase_block;
spi_flash_rd_t read;
spi_flash_wr_t write;
spi_flash_ewr_t encrypt_write;
spi_flash_func_t check_sus;
spi_flash_wren_t wren;
spi_flash_op_t wait_idle;
spi_flash_erase_area_t erase_area;
} spiflash_legacy_funcs_t;
typedef struct {
uint8_t data_length;
uint8_t read_cmd0;
uint8_t read_cmd1;
uint8_t write_cmd;
uint16_t data_mask;
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: always keeping false.
*
* @return None
*/
void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy);
/**
* @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief Write status to Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t status_value : Value to .
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : write OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value);
/**
* @brief Use a command to Read Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t*status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd);
/**
* @brief Config SPI Flash read mode when init.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
*
* This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
/**
* @brief Config SPI Flash clock divisor.
* Please do not call this function in SDK.
*
* @param uint8_t freqdiv: clock divisor.
*
* @param uint8_t spi: 0 for SPI0, 1 for SPI1.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
/**
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param None.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
/**
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param None.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
/**
* @brief Update SPI Flash parameter.
* Please do not call this function in SDK.
*
* @param uint32_t deviceId : Device ID read from SPI, the low 32 bit.
*
* @param uint32_t chip_size : The Flash size.
*
* @param uint32_t block_size : The Flash block size.
*
* @param uint32_t sector_size : The Flash sector size.
*
* @param uint32_t page_size : The Flash page size.
*
* @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Update error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
/**
* @brief Erase whole flash chip.
* Please do not call this function in SDK.
*
* @param None
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void);
/**
* @brief Erase a 64KB block of flash
* Uses SPI flash command D8H.
* Please do not call this function in SDK.
*
* @param uint32_t block_num : Which block to erase.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num);
/**
* @brief Erase a sector of flash.
* Uses SPI flash command 20H.
* Please do not call this function in SDK.
*
* @param uint32_t sector_num : Which sector to erase.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num);
/**
* @brief Erase some sectors.
* Please do not call this function in SDK.
*
* @param uint32_t start_addr : Start addr to erase, should be sector aligned.
*
* @param uint32_t area_len : Length to erase, should be sector aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len);
/**
* @brief Write Data to Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t dest_addr : Address to write, should be 4 bytes aligned.
*
* @param const uint32_t *src : The pointer to data which is to write.
*
* @param uint32_t len : Length to write, should be 4 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len);
/**
* @brief Read Data from Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
*
* @param uint32_t *dest : The buf to read the data.
*
* @param uint32_t len : Length to read, should be 4 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len);
/**
* @brief SPI1 go into encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void esp_rom_spiflash_write_encrypted_enable(void);
/**
* @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
*
* @param uint32_t *data : The pointer to data which is to write.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data);
/**
* @brief SPI1 go out of encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void esp_rom_spiflash_write_encrypted_disable(void);
/**
* @brief Write data to flash with transparent encryption.
* @note Sectors to be written should already be erased.
*
* @note Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 byte aligned.
*
* @param uint32_t *data : The pointer to data to write. Note, this pointer must
* be 32 bit aligned and the content of the data will be
* modified by the encryption function.
*
* @param uint32_t len : Length to write, should be 32 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully.
* ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
/** @brief Wait until SPI flash write operation is complete
*
* @note Please do not call this function in SDK.
*
* Reads the Write In Progress bit of the SPI flash status register,
* repeats until this bit is zero (indicating write complete).
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete
* ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
/** @brief Enable Quad I/O pin functions
*
* @note Please do not call this function in SDK.
*
* Sets the HD & WP pin functions for Quad I/O modes, based on the
* efuse SPI pin configuration.
*
* @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
*
* @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
* - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
* - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
* - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
* to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
* Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
*/
void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
/**
* @brief Clear WEL bit unconditionally.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
/**
* @brief Set WREN bit.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
#ifdef __cplusplus
}
#endif

432
components/esp_rom/include/esp32p4/rom/uart.h Normal file
View File

@ -0,0 +1,432 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_UART_H_
#define _ROM_UART_H_
#include "esp_types.h"
#include "esp_attr.h"
#include "ets_sys.h"
#include "soc/soc.h"
#include "soc/uart_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup uart_apis, uart configuration and communication related apis
* @brief uart apis
*/
/** @addtogroup uart_apis
* @{
*/
#define RX_BUFF_SIZE 0x400
#define TX_BUFF_SIZE 100
//uart int enalbe register ctrl bits
#define UART_RCV_INTEN BIT0
#define UART_TRX_INTEN BIT1
#define UART_LINE_STATUS_INTEN BIT2
//uart int identification ctrl bits
#define UART_INT_FLAG_MASK 0x0E
//uart fifo ctrl bits
#define UART_CLR_RCV_FIFO BIT1
#define UART_CLR_TRX_FIFO BIT2
#define UART_RCVFIFO_TRG_LVL_BITS BIT6
//uart line control bits
#define UART_DIV_LATCH_ACCESS_BIT BIT7
//uart line status bits
#define UART_RCV_DATA_RDY_FLAG BIT0
#define UART_RCV_OVER_FLOW_FLAG BIT1
#define UART_RCV_PARITY_ERR_FLAG BIT2
#define UART_RCV_FRAME_ERR_FLAG BIT3
#define UART_BRK_INT_FLAG BIT4
#define UART_TRX_FIFO_EMPTY_FLAG BIT5
#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg
#define UART_RCV_ERR_FLAG BIT7
//send and receive message frame head
#define FRAME_FLAG 0x7E
typedef enum {
UART_LINE_STATUS_INT_FLAG = 0x06,
UART_RCV_FIFO_INT_FLAG = 0x04,
UART_RCV_TMOUT_INT_FLAG = 0x0C,
UART_TXBUFF_EMPTY_INT_FLAG = 0x02
} UartIntType; //consider bit0 for int_flag
typedef enum {
RCV_ONE_BYTE = 0x0,
RCV_FOUR_BYTE = 0x1,
RCV_EIGHT_BYTE = 0x2,
RCV_FOURTEEN_BYTE = 0x3
} UartRcvFifoTrgLvl;
typedef enum {
FIVE_BITS = 0x0,
SIX_BITS = 0x1,
SEVEN_BITS = 0x2,
EIGHT_BITS = 0x3
} UartBitsNum4Char;
typedef enum {
ONE_STOP_BIT = 1,
ONE_HALF_STOP_BIT = 2,
TWO_STOP_BIT = 3
} UartStopBitsNum;
typedef enum {
NONE_BITS = 0,
ODD_BITS = 2,
EVEN_BITS = 3
} UartParityMode;
typedef enum {
STICK_PARITY_DIS = 0,
STICK_PARITY_EN = 2
} UartExistParity;
typedef enum {
BIT_RATE_9600 = 9600,
BIT_RATE_19200 = 19200,
BIT_RATE_38400 = 38400,
BIT_RATE_57600 = 57600,
BIT_RATE_115200 = 115200,
BIT_RATE_230400 = 230400,
BIT_RATE_460800 = 460800,
BIT_RATE_921600 = 921600
} UartBautRate;
typedef enum {
NONE_CTRL,
HARDWARE_CTRL,
XON_XOFF_CTRL
} UartFlowCtrl;
typedef enum {
EMPTY,
UNDER_WRITE,
WRITE_OVER
} RcvMsgBuffState;
typedef struct {
uint8_t *pRcvMsgBuff;
uint8_t *pWritePos;
uint8_t *pReadPos;
uint8_t TrigLvl;
RcvMsgBuffState BuffState;
} RcvMsgBuff;
typedef struct {
uint32_t TrxBuffSize;
uint8_t *pTrxBuff;
} TrxMsgBuff;
typedef enum {
BAUD_RATE_DET,
WAIT_SYNC_FRM,
SRCH_MSG_HEAD,
RCV_MSG_BODY,
RCV_ESC_CHAR,
} RcvMsgState;
typedef struct {
UartBautRate baut_rate;
UartBitsNum4Char data_bits;
UartExistParity exist_parity;
UartParityMode parity; // chip size in byte
UartStopBitsNum stop_bits;
UartFlowCtrl flow_ctrl;
uint8_t buff_uart_no; //indicate which uart use tx/rx buffer
RcvMsgBuff rcv_buff;
// TrxMsgBuff trx_buff;
RcvMsgState rcv_state;
int received;
} UartDevice;
/**
* @brief Init uart device struct value and reset uart0/uart1 rx.
* Please do not call this function in SDK.
*
* @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL
*
* @return None
*/
void uartAttach(void *rxBuffer);
/**
* @brief Init uart0 or uart1 for UART download booting mode.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, else for UART1.
*
* @param uint32_t clock : clock used by uart module, to adjust baudrate.
*
* @return None
*/
void Uart_Init(uint8_t uart_no, uint32_t clock);
/**
* @brief Modify uart baudrate.
* This function will reset RX/TX fifo for uart.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @param uint32_t DivLatchValue : (clock << 4)/baudrate.
*
* @return None
*/
void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
/**
* @brief Init uart0 or uart1 for UART download booting mode.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected;
* 1, two UART modules, hard to detect, detect and return.
*
* @return None
*/
int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync);
/**
* @brief Switch printf channel of uart_tx_one_char.
* Please do not call this function when printf.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None
*/
void uart_tx_switch(uint8_t uart_no);
/**
* @brief Switch message exchange channel for UART download booting.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None
*/
void uart_buff_switch(uint8_t uart_no);
/**
* @brief Output a char to printf channel, wait until fifo not full.
*
* @param None
*
* @return OK.
*/
STATUS uart_tx_one_char(uint8_t TxChar);
/**
* @brief Output a char to message exchange channel, wait until fifo not full.
* Please do not call this function in SDK.
*
* @param None
*
* @return OK.
*/
STATUS uart_tx_one_char2(uint8_t TxChar);
/**
* @brief Wait until uart tx full empty.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None.
*/
void uart_tx_flush(uint8_t uart_no);
/**
* @brief Wait until uart tx full empty and the last char send ok.
*
* @param uart_no : 0 for UART0, 1 for UART1
*
* The function defined in ROM code has a bug, so we define the correct version
* here for compatibility.
*/
void uart_tx_wait_idle(uint8_t uart_no);
/**
* @brief Get an input char from message channel.
* Please do not call this function in SDK.
*
* @param uint8_t *pRxChar : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS uart_rx_one_char(uint8_t *pRxChar);
/**
* @brief Get an input char from message channel, wait until successful.
* Please do not call this function in SDK.
*
* @param None
*
* @return char : input char value.
*/
char uart_rx_one_char_block(void);
/**
* @brief Get an input string line from message channel.
* Please do not call this function in SDK.
*
* @param uint8_t *pString : the pointer to store the string.
*
* @param uint8_t MaxStrlen : the max string length, incude '\0'.
*
* @return OK.
*/
STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
/**
* @brief Process uart recevied information in the interrupt handler.
* Please do not call this function in SDK.
*
* @param void *para : the message receive buffer.
*
* @return None
*/
void uart_rx_intr_handler(void *para);
/**
* @brief Get an char from receive buffer.
* Please do not call this function in SDK.
*
* @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
*
* @param uint8_t *pRxByte : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
/**
* @brief Get all chars from receive buffer.
* Please do not call this function in SDK.
*
* @param uint8_t *pCmdLn : the pointer to store the string.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS UartGetCmdLn(uint8_t *pCmdLn);
/**
* @brief Get uart configuration struct.
* Please do not call this function in SDK.
*
* @param None
*
* @return UartDevice * : uart configuration struct pointer.
*/
UartDevice *GetUartDevice(void);
/**
* @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to output string.
*
* @param int len : the string length.
*
* @return None.
*/
void send_packet(uint8_t *p, int len);
/**
* @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to input string.
*
* @param int len : If string length > len, the string will be truncated.
*
* @param uint8_t is_sync : 0, only one UART module;
* 1, two UART modules.
*
* @return int : the length of the string.
*/
int recv_packet(uint8_t *p, int len, uint8_t is_sync);
/**
* @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *pData : the pointer to input string.
*
* @param uint16_t DataLen : the string length.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS SendMsg(uint8_t *pData, uint16_t DataLen);
/**
* @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *pData : the pointer to input string.
*
* @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated.
*
* @param uint8_t is_sync : 0, only one UART module;
* 1, two UART modules.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync);
/**
* @brief Check if this UART is in download connection.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return ETS_NO_BOOT = 0 for no.
* SEL_UART_BOOT = BIT(1) for yes.
*/
uint8_t UartConnCheck(uint8_t uart_no);
/**
* @brief Initialize the USB ACM UART
* Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have.
*
* @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code
* @param cdc_acm_work_mem_len Length of work mem
*/
void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len);
/**
* @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'.
*/
void uart_usb_enable_reset_on_rts(void);
extern UartDevice UartDev;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _ROM_UART_H_ */

1
components/esp_rom/include/esp_rom_spiflash.h
View File

@ -29,6 +29,7 @@ typedef enum {
ESP_ROM_SPIFLASH_OIO_STR_MODE,
ESP_ROM_SPIFLASH_OIO_DTR_MODE,
ESP_ROM_SPIFLASH_QPI_MODE,
ESP_ROM_SPIFLASH_OPI_HEX_DTR_MODE,
} esp_rom_spiflash_read_mode_t;
typedef struct {

1
tools/ci/check_public_headers_exceptions.txt
View File

@ -106,6 +106,7 @@ components/esp_rom/include/esp32s3/rom/rtc.h
components/esp_rom/include/esp32c2/rom/rtc.h
components/esp_rom/include/esp32c6/rom/rtc.h
components/esp_rom/include/esp32h2/rom/rtc.h
components/esp_rom/include/esp32p4/rom/rtc.h
components/esp_rom/include/esp32/rom/sha.h
components/esp_rom/include/esp32/rom/secure_boot.h
components/esp_rom/include/esp32c3/rom/spi_flash.h