diff --git a/Kconfig b/Kconfig index 06e6a970d1..ca09ec94bc 100644 --- a/Kconfig +++ b/Kconfig @@ -135,7 +135,6 @@ mainmenu "Espressif IoT Development Framework Configuration" default "y" if IDF_TARGET="esp32c61" select FREERTOS_UNICORE select IDF_TARGET_ARCH_RISCV - select IDF_ENV_FPGA config IDF_TARGET_LINUX bool diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt index fbe9adf5fd..c1f8eb6fdb 100644 --- a/components/bootloader_support/CMakeLists.txt +++ b/components/bootloader_support/CMakeLists.txt @@ -15,7 +15,7 @@ set(srcs "src/secure_boot.c" ) -if(NOT CONFIG_IDF_ENV_FPGA) +if(NOT CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING) # For FPGA ENV, bootloader_random implementation is implemented in `bootloader_random.c` list(APPEND srcs "src/bootloader_random_${IDF_TARGET}.c") endif() diff --git a/components/bootloader_support/src/bootloader_random.c b/components/bootloader_support/src/bootloader_random.c index 7bdb516e10..abab981e44 100644 --- a/components/bootloader_support/src/bootloader_random.c +++ b/components/bootloader_support/src/bootloader_random.c @@ -83,10 +83,10 @@ } #endif // BOOTLOADER_BUILD -#if CONFIG_IDF_ENV_FPGA +#if CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING static void s_non_functional(const char *func) { - ESP_EARLY_LOGW("rand", "%s non-functional for FPGA builds", func); + ESP_EARLY_LOGW("rand", "%s non-functional as RNG has not been supported yet", func); } void bootloader_random_enable() @@ -98,4 +98,4 @@ void bootloader_random_disable() { s_non_functional(__func__); } -#endif // CONFIG_IDF_ENV_FPGA +#endif // CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING diff --git a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c index 2e83ebccff..7021c408f8 100644 --- a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c +++ b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c @@ -39,7 +39,6 @@ #include "esp_efuse.h" #include "hal/mmu_hal.h" #include "hal/cache_hal.h" -#include "hal/clk_tree_ll.h" #include "soc/lp_wdt_reg.h" #include "hal/efuse_hal.h" #include "hal/lpwdt_ll.h" @@ -86,15 +85,6 @@ static void bootloader_super_wdt_auto_feed(void) static inline void bootloader_hardware_init(void) { - // In 80MHz flash mode, ROM sets the mspi module clk divider to 2, fix it here -#if CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_APP_BUILD_TYPE_RAM - clk_ll_mspi_fast_set_hs_divider(6); - esp_rom_spiflash_config_clk(1, 0); - esp_rom_spiflash_config_clk(1, 1); - esp_rom_spiflash_fix_dummylen(0, 1); - esp_rom_spiflash_fix_dummylen(1, 1); -#endif - regi2c_ctrl_ll_master_enable_clock(true); regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this? regi2c_ctrl_ll_master_configure_clock(); diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 6847c845fc..b897c05c34 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -174,7 +174,6 @@ if(NOT BOOTLOADER_BUILD) "sleep_modes.c" "sleep_wake_stub.c" "sleep_gpio.c" - "port/esp_clk_tree_common.c" ) endif() else() diff --git a/components/esp_hw_support/port/esp32c5/Kconfig.rtc b/components/esp_hw_support/port/esp32c5/Kconfig.rtc index 7a035f52c0..b02d6e6cc0 100644 --- a/components/esp_hw_support/port/esp32c5/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32c5/Kconfig.rtc @@ -5,7 +5,7 @@ choice RTC_CLK_SRC Choose which clock is used as RTC clock source. config RTC_CLK_SRC_INT_RC - bool "Internal 136kHz RC oscillator" + bool "Internal 136 kHz RC oscillator" config RTC_CLK_SRC_EXT_CRYS bool "External 32 kHz crystal" select ESP_SYSTEM_RTC_EXT_XTAL diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index b449d37414..97da0750e8 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -172,14 +172,10 @@ void rtc_clk_init(rtc_clk_config_t cfg); /** * @brief Get main XTAL frequency * - * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to - * rtc_clk_init function - * * @return XTAL frequency, one of soc_xtal_freq_t */ soc_xtal_freq_t rtc_clk_xtal_freq_get(void); - /** * @brief Enable or disable 32 kHz XTAL oscillator * @param en true to enable, false to disable diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index c369fcac4d..a02bdb9acc 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -17,7 +17,7 @@ #include "esp_rom_sys.h" #include "hal/clk_tree_ll.h" #include "hal/regi2c_ctrl_ll.h" -#include "soc/io_mux_reg.h" +#include "hal/gpio_ll.h" #include "soc/lp_aon_reg.h" #include "esp_private/sleep_event.h" @@ -54,7 +54,7 @@ void rtc_clk_32k_enable(bool enable) void rtc_clk_32k_enable_external(void) { // EXT_OSC_SLOW_GPIO_NUM == GPIO_NUM_0 - PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG); + gpio_ll_input_enable(&GPIO, EXT_OSC_SLOW_GPIO_NUM); REG_SET_BIT(LP_AON_GPIO_HOLD0_REG, BIT(EXT_OSC_SLOW_GPIO_NUM)); clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL); } @@ -334,32 +334,28 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) { soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); uint32_t source_freq_mhz; - uint32_t freq_mhz; - uint32_t div = clk_ll_cpu_get_divider(); // div = freq of SOC_ROOT_CLK / freq of CPU_CLK switch (source) { case SOC_CPU_CLK_SRC_XTAL: { source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get(); - freq_mhz = source_freq_mhz / div; break; } case SOC_CPU_CLK_SRC_PLL_F160M: { source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; - freq_mhz = source_freq_mhz / div; break; } case SOC_CPU_CLK_SRC_PLL_F240M: { source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ; - freq_mhz = source_freq_mhz / div; break; } case SOC_CPU_CLK_SRC_RC_FAST: source_freq_mhz = 20; - freq_mhz = source_freq_mhz / div; break; default: ESP_HW_LOGE(TAG, "unsupported frequency configuration"); abort(); } + uint32_t div = clk_ll_cpu_get_divider(); + uint32_t freq_mhz = source_freq_mhz / div; // freq of CPU_CLK = freq of SOC_ROOT_CLK / cpu_div *out_config = (rtc_cpu_freq_config_t) { .source = source, .source_freq_mhz = source_freq_mhz, @@ -420,32 +416,26 @@ static uint32_t rtc_clk_ahb_freq_get(void) { soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); uint32_t soc_root_freq_mhz; - uint32_t divider; switch (source) { case SOC_CPU_CLK_SRC_XTAL: soc_root_freq_mhz = rtc_clk_xtal_freq_get(); - divider = clk_ll_ahb_get_divider(); break; case SOC_CPU_CLK_SRC_PLL_F160M: soc_root_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; - divider = clk_ll_ahb_get_divider(); break; case SOC_CPU_CLK_SRC_PLL_F240M: soc_root_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ; - divider = clk_ll_ahb_get_divider(); break; case SOC_CPU_CLK_SRC_RC_FAST: soc_root_freq_mhz = 20; - divider = clk_ll_ahb_get_divider(); break; default: // Unknown SOC_ROOT clock source soc_root_freq_mhz = 0; - divider = 1; ESP_HW_LOGE(TAG, "Invalid SOC_ROOT_CLK"); break; } - return soc_root_freq_mhz / divider; + return soc_root_freq_mhz / clk_ll_ahb_get_divider(); } uint32_t rtc_clk_apb_freq_get(void) diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c index 81e452e71a..b659bd2ba5 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c @@ -90,6 +90,8 @@ void rtc_clk_init(rtc_clk_config_t cfg) // XTAL freq determined by efuse, and can be directly informed from register field PCR_CLK_XTAL_FREQ + // No need to wait UART0 TX idle since its default clock source is XTAL, should not be affected by system clock configuration + /* Set CPU frequency */ rtc_clk_cpu_freq_get_config(&old_config); uint32_t freq_before = old_config.freq_mhz; diff --git a/components/esp_hw_support/port/esp32c5/rtc_time.c b/components/esp_hw_support/port/esp32c5/rtc_time.c index 76e77e06f5..1c4694a479 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_time.c +++ b/components/esp_hw_support/port/esp32c5/rtc_time.c @@ -15,8 +15,6 @@ #include "soc/pcr_reg.h" #include "esp_rom_sys.h" #include "assert.h" -#include "hal/efuse_hal.h" -#include "soc/chip_revision.h" #include "esp_private/periph_ctrl.h" __attribute__((unused)) static const char *TAG = "rtc_time"; @@ -108,7 +106,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc if (cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) { expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; } else if (cal_clk == RTC_CAL_RC_FAST) { - expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_TICK_DIV_BITS; + expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; } else { expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } @@ -127,7 +125,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc /*The Fosc CLK of calibration circuit is divided by a factor, k. So we need to multiply the frequency of the FOSC by k times.*/ if (cal_clk == RTC_CAL_RC_FAST) { - cal_val = cal_val >> CLK_LL_RC_FAST_TICK_DIV_BITS; + cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; } break; } @@ -173,15 +171,15 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { - soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); - /*The Fosc CLK of calibration circuit is divided by a factor, k. So we need to divide the calibrate cycles of the FOSC by k to avoid excessive calibration time.*/ if (cal_clk == RTC_CAL_RC_FAST) { - slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_TICK_DIV_BITS; + slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; } + assert(slowclk_cycles); + soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { return 0; @@ -195,6 +193,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) { + assert(period); /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. * TODO: fix overflow. */ diff --git a/components/esp_hw_support/port/esp32c6/rtc_time.c b/components/esp_hw_support/port/esp32c6/rtc_time.c index 8e31485e1d..89df6fae2d 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_time.c +++ b/components/esp_hw_support/port/esp32c6/rtc_time.c @@ -141,7 +141,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles)); expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX; if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { - expected_freq = expected_freq >> CLK_LL_RC_FAST_TICK_DIV_BITS; + expected_freq = expected_freq >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; } } else { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); @@ -166,7 +166,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc calibration. */ if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { if (cal_clk == RTC_CAL_RC_FAST) { - cal_val = cal_val >> CLK_LL_RC_FAST_TICK_DIV_BITS; + cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); } } @@ -227,7 +227,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) avoid excessive calibration time.*/ if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { if (cal_clk == RTC_CAL_RC_FAST) { - slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_TICK_DIV_BITS; + slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); } } diff --git a/components/esp_hw_support/port/esp32c61/CMakeLists.txt b/components/esp_hw_support/port/esp32c61/CMakeLists.txt index 7ce5ce6653..242fe18e81 100644 --- a/components/esp_hw_support/port/esp32c61/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c61/CMakeLists.txt @@ -21,11 +21,8 @@ endif() # TODO: [ESP32C61] IDF-9250 if(CONFIG_IDF_TARGET_ESP32C61) list(REMOVE_ITEM srcs - "pmu_param.c" - "pmu_init.c" "pmu_sleep.c" "sar_periph_ctrl.c" - "ocode_init.c" ) endif() diff --git a/components/esp_hw_support/port/esp32c61/Kconfig.rtc b/components/esp_hw_support/port/esp32c61/Kconfig.rtc index e58391029c..b02d6e6cc0 100644 --- a/components/esp_hw_support/port/esp32c61/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32c61/Kconfig.rtc @@ -5,22 +5,22 @@ choice RTC_CLK_SRC Choose which clock is used as RTC clock source. config RTC_CLK_SRC_INT_RC - bool "Internal 150 kHz RC oscillator" + bool "Internal 136 kHz RC oscillator" config RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" + bool "External 32 kHz crystal" select ESP_SYSTEM_RTC_EXT_XTAL config RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XP pin" + bool "External 32 kHz oscillator at 32K_XP pin" select ESP_SYSTEM_RTC_EXT_OSC config RTC_CLK_SRC_INT_RC32K - bool "Internal 32kHz RC oscillator" + bool "Internal 32 kHz RC oscillator" endchoice config RTC_CLK_CAL_CYCLES int "Number of cycles for RTC_SLOW_CLK calibration" default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K default 1024 if RTC_CLK_SRC_INT_RC - range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K + range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K range 0 32766 if RTC_CLK_SRC_INT_RC help When the startup code initializes RTC_SLOW_CLK, it can perform diff --git a/components/esp_hw_support/port/esp32c61/esp_clk_tree.c b/components/esp_hw_support/port/esp32c61/esp_clk_tree.c index e61fb88c37..2ddaca24af 100644 --- a/components/esp_hw_support/port/esp32c61/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c61/esp_clk_tree.c @@ -15,8 +15,6 @@ static const char *TAG = "esp_clk_tree"; -//TODO: [ESP32C61] IDF-9249 - esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision, uint32_t *freq_value) { @@ -26,14 +24,32 @@ uint32_t *freq_value) uint32_t clk_src_freq = 0; switch (clk_src) { + case SOC_MOD_CLK_CPU: + clk_src_freq = clk_hal_cpu_get_freq_hz(); + break; + case SOC_MOD_CLK_XTAL: + clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ; + break; case SOC_MOD_CLK_PLL_F80M: clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ; break; case SOC_MOD_CLK_PLL_F160M: clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ; break; - case SOC_MOD_CLK_PLL_F240M: - clk_src_freq = CLK_LL_PLL_240M_FREQ_MHZ * MHZ; + case SOC_MOD_CLK_SPLL: + clk_src_freq = CLK_LL_PLL_480M_FREQ_MHZ * MHZ; + break; + case SOC_MOD_CLK_RTC_SLOW: + clk_src_freq = esp_clk_tree_lp_slow_get_freq_hz(precision); + break; + case SOC_MOD_CLK_RTC_FAST: + clk_src_freq = esp_clk_tree_lp_fast_get_freq_hz(precision); + break; + case SOC_MOD_CLK_RC_FAST: + clk_src_freq = esp_clk_tree_rc_fast_get_freq_hz(precision); + break; + case SOC_MOD_CLK_XTAL32K: + clk_src_freq = esp_clk_tree_xtal32k_get_freq_hz(precision); break; default: break; diff --git a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h index cdf1e422b4..91cebda696 100644 --- a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h @@ -49,10 +49,6 @@ extern "C" { #define MHZ (1000000) -#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) -#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) -#define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value - #define OTHER_BLOCKS_POWERUP 1 #define OTHER_BLOCKS_WAIT 1 @@ -120,21 +116,19 @@ typedef struct rtc_cpu_freq_config_s { #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - /** * @brief Clock source to be calibrated using rtc_clk_cal function * - * @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL - * However, this is not true on ESP32C61. The conversion to register field values is explicitly done in - * rtc_clk_cal_internal + * @note On ESP32C61, the enum values somehow reflects the register field values of PCR_32K_SEL. */ typedef enum { - RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK - RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator - RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock - RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock - RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock - RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator + RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK + RTC_CAL_RC32K = 0, //!< Internal 32kHz RC oscillator, as one type of 32k clock + RTC_CAL_32K_XTAL = 1, //!< External 32kHz XTAL, as one type of 32k clock + RTC_CAL_32K_OSC_SLOW = 2, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock + RTC_CAL_RC_SLOW = 3, //!< Internal 150kHz RC oscillator + RTC_CAL_RC_FAST = 4, //!< Internal 20MHz RC oscillator + RTC_CAL_INVALID_CLK, //!< Clock not available to calibrate } rtc_cal_sel_t; /** @@ -177,23 +171,10 @@ void rtc_clk_init(rtc_clk_config_t cfg); /** * @brief Get main XTAL frequency * - * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to - * rtc_clk_init function - * * @return XTAL frequency, one of soc_xtal_freq_t */ soc_xtal_freq_t rtc_clk_xtal_freq_get(void); -/** - * @brief Update XTAL frequency - * - * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored - * after startup. - * - * @param xtal_freq New frequency value - */ -void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq); - /** * @brief Enable or disable 32 kHz XTAL oscillator * @param en true to enable, false to disable @@ -441,50 +422,6 @@ bool rtc_dig_8m_enabled(void); */ uint32_t rtc_clk_freq_cal(uint32_t cal_val); - -// -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- -// **WARNING**: The following are only for backwards compatibility. -// Please use the declarations in soc/clk_tree_defs.h instead. -/** - * @brief CPU clock source - */ -typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t; -#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL -#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M) -#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator - -/** - * @brief RTC SLOW_CLK frequency values - */ -typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t; -#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator -#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL - -/** - * @brief RTC FAST_CLK frequency values - */ -typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t; -#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2 -#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator - -/** - * @brief Possible main XTAL frequency values. - */ -typedef soc_xtal_freq_t rtc_xtal_freq_t; -#define RTC_XTAL_FREQ_40M SOC_XTAL_FREQ_40M //!< 40 MHz XTAL - -/* Alias of frequency related macros */ -#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX -#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX -#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX -#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX - -/* Alias of deprecated function names */ -#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq) -#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get() -#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq) -#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get() - #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/port/esp32c61/ocode_init.c b/components/esp_hw_support/port/esp32c61/ocode_init.c new file mode 100644 index 0000000000..bb25cce95c --- /dev/null +++ b/components/esp_hw_support/port/esp32c61/ocode_init.c @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "soc/soc.h" +#include "soc/rtc.h" +#include "soc/regi2c_dig_reg.h" +#include "soc/regi2c_lp_bias.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" +#include "regi2c_ctrl.h" +#include "esp_hw_log.h" + +// TODO: IDF-9303 + +static const char *TAG = "ocode_init"; + +// static void set_ocode_by_efuse(int ocode_scheme_ver) +// { + // assert(ocode_scheme_ver == 1); + // unsigned int ocode = efuse_ll_get_ocode(); + + // //set ext_ocode + // REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); + // REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); +// } + +static void calibrate_ocode(void) +{ + /* + Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration (must turn off PLL). + Method: + 1. read current cpu config, save in old_config; + 2. switch cpu to xtal because PLL will be closed when o-code calibration; + 3. begin o-code calibration; + 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; + 5. set cpu to old-config. + */ + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); + rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { + cal_clk = RTC_CAL_32K_OSC_SLOW; + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + cal_clk = RTC_CAL_32K_XTAL; + } + + uint64_t max_delay_time_us = 10000; + uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); + uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); + uint64_t cycle0 = rtc_time_get(); + uint64_t timeout_cycle = cycle0 + max_delay_cycle; + uint64_t cycle1 = 0; + + rtc_cpu_freq_config_t old_config; + rtc_clk_cpu_freq_get_config(&old_config); + rtc_clk_cpu_freq_set_xtal(); + + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); + bool odone_flag = 0; + bool bg_odone_flag = 0; + while (1) { + odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG); + bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG); + cycle1 = rtc_time_get(); + if (odone_flag && bg_odone_flag) { + break; + } + if (cycle1 >= timeout_cycle) { + ESP_HW_LOGW(TAG, "o_code calibration fail\n"); + break; + } + } + rtc_clk_cpu_freq_set_config(&old_config); +} + +void esp_ocode_calib_init(void) +{ + // if (efuse_hal_blk_version() >= 1) { + // set_ocode_by_efuse(1); + // } else { + calibrate_ocode(); + // } +} diff --git a/components/esp_hw_support/port/esp32c61/pmu_init.c b/components/esp_hw_support/port/esp32c61/pmu_init.c new file mode 100644 index 0000000000..1496d39190 --- /dev/null +++ b/components/esp_hw_support/port/esp32c61/pmu_init.c @@ -0,0 +1,219 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "sdkconfig.h" +#include "esp_attr.h" +#include "soc/soc.h" +#include "soc/pmu_struct.h" +#include "hal/pmu_hal.h" +#include "pmu_param.h" +#include "esp_private/esp_pmu.h" +#include "soc/regi2c_dig_reg.h" +#include "regi2c_ctrl.h" + +static __attribute__((unused)) const char *TAG = "pmu_init"; + +typedef struct { + const pmu_hp_system_power_param_t *power; + const pmu_hp_system_clock_param_t *clock; + const pmu_hp_system_digital_param_t *digital; + pmu_hp_system_analog_param_t *analog; //param determined at runtime + const pmu_hp_system_retention_param_t *retent; +} pmu_hp_system_param_t; + +typedef struct { + const pmu_lp_system_power_param_t *power; + pmu_lp_system_analog_param_t *analog; //param determined at runtime +} pmu_lp_system_param_t; + +pmu_context_t * __attribute__((weak)) IRAM_ATTR PMU_instance(void) +{ + /* It should be explicitly defined in the internal RAM, because this + * instance will be used in pmu_sleep.c */ + static DRAM_ATTR pmu_hal_context_t pmu_hal = { .dev = &PMU }; + static DRAM_ATTR pmu_sleep_machine_constant_t pmu_mc = PMU_SLEEP_MC_DEFAULT(); + static DRAM_ATTR pmu_context_t pmu_context = { .hal = &pmu_hal, .mc = (void *)&pmu_mc }; + return &pmu_context; +} + +void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, const pmu_hp_system_param_t *param) +{ + const pmu_hp_system_power_param_t *power = param->power; + const pmu_hp_system_clock_param_t *clock = param->clock; + const pmu_hp_system_digital_param_t *dig = param->digital; + const pmu_hp_system_analog_param_t *anlg = param->analog; + const pmu_hp_system_retention_param_t *ret = param->retent; + + assert(ctx->hal); + /* Default configuration of hp-system power in active, modem and sleep modes */ + pmu_ll_hp_set_dig_power(ctx->hal->dev, mode, power->dig_power.val); + pmu_ll_hp_set_clk_power(ctx->hal->dev, mode, power->clk_power.val); + pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, mode, power->xtal.xpd_xtal); + + /* Default configuration of hp-system clock in active, modem and sleep modes */ + pmu_ll_hp_set_icg_func (ctx->hal->dev, mode, clock->icg_func); + pmu_ll_hp_set_icg_apb (ctx->hal->dev, mode, clock->icg_apb); + pmu_ll_hp_set_icg_modem (ctx->hal->dev, mode, clock->icg_modem.code); + pmu_ll_hp_set_sysclk_nodiv (ctx->hal->dev, mode, clock->sysclk.dig_sysclk_nodiv); + pmu_ll_hp_set_icg_sysclk_enable (ctx->hal->dev, mode, clock->sysclk.icg_sysclk_en); + pmu_ll_hp_set_sysclk_slp_sel (ctx->hal->dev, mode, clock->sysclk.sysclk_slp_sel); + pmu_ll_hp_set_icg_sysclk_slp_sel(ctx->hal->dev, mode, clock->sysclk.icg_slp_sel); + pmu_ll_hp_set_dig_sysclk (ctx->hal->dev, mode, clock->sysclk.dig_sysclk_sel); + + /* Default configuration of hp-system digital sub-system in active, modem + * and sleep modes */ + pmu_ll_hp_set_uart_wakeup_enable(ctx->hal->dev, mode, dig->syscntl.uart_wakeup_en); + pmu_ll_hp_set_hold_all_lp_pad (ctx->hal->dev, mode, dig->syscntl.lp_pad_hold_all); + pmu_ll_hp_set_hold_all_hp_pad (ctx->hal->dev, mode, dig->syscntl.hp_pad_hold_all); + pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, mode, dig->syscntl.dig_pad_slp_sel); + pmu_ll_hp_set_pause_watchdog (ctx->hal->dev, mode, dig->syscntl.dig_pause_wdt); + pmu_ll_hp_set_cpu_stall (ctx->hal->dev, mode, dig->syscntl.dig_cpu_stall); + + /* Default configuration of hp-system analog sub-system in active, modem and + * sleep modes */ + pmu_ll_hp_set_bias_xpd (ctx->hal->dev, mode, anlg->bias.xpd_bias); + pmu_ll_hp_set_dbg_atten (ctx->hal->dev, mode, anlg->bias.dbg_atten); + pmu_ll_hp_set_current_power_off (ctx->hal->dev, mode, anlg->bias.pd_cur); + pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, mode, anlg->bias.bias_sleep); + pmu_ll_hp_set_regulator_sleep_memory_xpd (ctx->hal->dev, mode, anlg->regulator0.slp_mem_xpd); + pmu_ll_hp_set_regulator_sleep_logic_xpd (ctx->hal->dev, mode, anlg->regulator0.slp_logic_xpd); + pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, mode, anlg->regulator0.xpd); + pmu_ll_hp_set_regulator_sleep_memory_dbias(ctx->hal->dev, mode, anlg->regulator0.slp_mem_dbias); + pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, mode, anlg->regulator0.slp_logic_dbias); + pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, mode, anlg->regulator0.dbias); + pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, mode, anlg->regulator1.drv_b); + + /* Default configuration of hp-system retention sub-system in active, modem + * and sleep modes */ + pmu_ll_hp_set_retention_param(ctx->hal->dev, mode, ret->retention.val); + pmu_ll_hp_set_backup_icg_func(ctx->hal->dev, mode, ret->backup_clk); + + /* Some PMU initial parameter configuration */ + pmu_ll_imm_update_dig_icg_modem_code(ctx->hal->dev, true); + pmu_ll_imm_update_dig_icg_switch(ctx->hal->dev, true); + + pmu_ll_hp_set_sleep_protect_mode(ctx->hal->dev, PMU_SLEEP_PROTECT_HP_LP_SLEEP); +} + +void pmu_lp_system_init(pmu_context_t *ctx, pmu_lp_mode_t mode, const pmu_lp_system_param_t *param) +{ + const pmu_lp_system_power_param_t *power = param->power; + const pmu_lp_system_analog_param_t *anlg = param->analog; + + assert(ctx->hal); + /* Default configuration of lp-system power in active and sleep modes */ + pmu_ll_lp_set_dig_power(ctx->hal->dev, mode, power->dig_power.val); + pmu_ll_lp_set_clk_power(ctx->hal->dev, mode, power->clk_power.val); + pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, PMU_MODE_LP_SLEEP, power->xtal.xpd_xtal); + + /* Default configuration of lp-system analog sub-system in active and + * sleep modes */ + pmu_ll_lp_set_bias_xpd (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.xpd_bias); + pmu_ll_lp_set_dbg_atten (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.dbg_atten); + pmu_ll_lp_set_current_power_off (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.pd_cur); + pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.bias_sleep); + pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, mode, anlg->regulator0.slp_xpd); + pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, mode, anlg->regulator0.xpd); + pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, mode, anlg->regulator0.slp_dbias); + pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, mode, anlg->regulator0.dbias); + pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, mode, anlg->regulator1.drv_b); +} + +static inline void pmu_power_domain_force_default(pmu_context_t *ctx) +{ + assert(ctx); + // for bypass reserved power domain + const pmu_hp_power_domain_t pmu_hp_domains[] = { + PMU_HP_PD_TOP, + PMU_HP_PD_HP_AON, + PMU_HP_PD_CPU, + PMU_HP_PD_WIFI + }; + + for (uint8_t idx = 0; idx < (sizeof(pmu_hp_domains) / sizeof(pmu_hp_power_domain_t)); idx++) { + pmu_ll_hp_set_power_force_power_up (ctx->hal->dev, pmu_hp_domains[idx], false); + pmu_ll_hp_set_power_force_no_reset (ctx->hal->dev, pmu_hp_domains[idx], false); + pmu_ll_hp_set_power_force_no_isolate(ctx->hal->dev, pmu_hp_domains[idx], false); + pmu_ll_hp_set_power_force_power_down(ctx->hal->dev, pmu_hp_domains[idx], false); + pmu_ll_hp_set_power_force_isolate (ctx->hal->dev, pmu_hp_domains[idx], false); + pmu_ll_hp_set_power_force_reset (ctx->hal->dev, pmu_hp_domains[idx], false); + } + /* Isolate all memory banks while sleeping, avoid memory leakage current */ + pmu_ll_hp_set_memory_no_isolate (ctx->hal->dev, 0); + + pmu_ll_lp_set_power_force_power_up (ctx->hal->dev, false); + pmu_ll_lp_set_power_force_no_reset (ctx->hal->dev, false); + pmu_ll_lp_set_power_force_no_isolate(ctx->hal->dev, false); + pmu_ll_lp_set_power_force_power_down(ctx->hal->dev, false); + pmu_ll_lp_set_power_force_isolate (ctx->hal->dev, false); + pmu_ll_lp_set_power_force_reset (ctx->hal->dev, false); +} + +static inline void pmu_hp_system_param_default(pmu_hp_mode_t mode, pmu_hp_system_param_t *param) +{ + assert (param->analog); + + param->power = pmu_hp_system_power_param_default(mode); + param->clock = pmu_hp_system_clock_param_default(mode); + param->digital = pmu_hp_system_digital_param_default(mode); + *param->analog = *pmu_hp_system_analog_param_default(mode); //copy default value + param->retent = pmu_hp_system_retention_param_default(mode); + + if (mode == PMU_MODE_HP_ACTIVE || mode == PMU_MODE_HP_MODEM) { + param->analog->regulator0.dbias = get_act_hp_dbias(); + } +} + +static void pmu_hp_system_init_default(pmu_context_t *ctx) +{ + assert(ctx); + for (pmu_hp_mode_t mode = PMU_MODE_HP_ACTIVE; mode < PMU_MODE_HP_MAX; mode++) { + pmu_hp_system_analog_param_t analog = {}; + pmu_hp_system_param_t param = {.analog = &analog}; + + pmu_hp_system_param_default(mode, ¶m); + pmu_hp_system_init(ctx, mode, ¶m); + } +} + +static inline void pmu_lp_system_param_default(pmu_lp_mode_t mode, pmu_lp_system_param_t *param) +{ + assert (param->analog); + + param->power = pmu_lp_system_power_param_default(mode); + *param->analog = *pmu_lp_system_analog_param_default(mode); //copy default value + + if (mode == PMU_MODE_LP_ACTIVE) { + param->analog->regulator0.dbias = get_act_lp_dbias(); + } +} + +static void pmu_lp_system_init_default(pmu_context_t *ctx) +{ + assert(ctx); + for (pmu_lp_mode_t mode = PMU_MODE_LP_ACTIVE; mode < PMU_MODE_LP_MAX; mode++) { + pmu_lp_system_analog_param_t analog = {}; + pmu_lp_system_param_t param = {.analog = &analog}; + + pmu_lp_system_param_default(mode, ¶m); + pmu_lp_system_init(ctx, mode, ¶m); + } +} + +void pmu_init(void) +{ + /* Peripheral reg i2c power up */ + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); + SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); + + pmu_hp_system_init_default(PMU_instance()); + pmu_lp_system_init_default(PMU_instance()); + + pmu_power_domain_force_default(PMU_instance()); +} diff --git a/components/esp_hw_support/port/esp32c61/pmu_param.c b/components/esp_hw_support/port/esp32c61/pmu_param.c new file mode 100644 index 0000000000..19be87caa5 --- /dev/null +++ b/components/esp_hw_support/port/esp32c61/pmu_param.c @@ -0,0 +1,505 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "sdkconfig.h" +#include "soc/soc.h" +#include "pmu_param.h" +#include "soc/pmu_icg_mapping.h" +#include "esp_private/esp_pmu.h" + +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" +#include "esp_hw_log.h" + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#endif + +#define PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT() { \ + .dig_power = { \ + .vdd_spi_pd_en = 0, \ + .mem_dslp = 0, \ + .mem_pd_en = 0, \ + .wifi_pd_en = 0, \ + .cpu_pd_en = 0, \ + .aon_pd_en = 0, \ + .top_pd_en = 0 \ + }, \ + .clk_power = { \ + .i2c_iso_en = 0, \ + .i2c_retention = 0, \ + .xpd_bb_i2c = 1, \ + .xpd_bbpll_i2c = 1, \ + .xpd_bbpll = 1 \ + }, \ + .xtal = { \ + .xpd_xtal = 1 \ + } \ +} + +#define PMU_HP_MODEM_POWER_CONFIG_DEFAULT() { \ + .dig_power = { \ + .vdd_spi_pd_en = 0, \ + .mem_dslp = 0, \ + .mem_pd_en = 0, \ + .wifi_pd_en = 0, \ + .cpu_pd_en = 1, \ + .aon_pd_en = 0, \ + .top_pd_en = 0 \ + }, \ + .clk_power = { \ + .i2c_iso_en = 0, \ + .i2c_retention = 0, \ + .xpd_bb_i2c = 1, \ + .xpd_bbpll_i2c = 1, \ + .xpd_bbpll = 1 \ + }, \ + .xtal = { \ + .xpd_xtal = 1 \ + } \ +} + +#define PMU_HP_SLEEP_POWER_CONFIG_DEFAULT() { \ + .dig_power = { \ + .vdd_spi_pd_en = 1, \ + .mem_dslp = 0, \ + .mem_pd_en = 0, \ + .wifi_pd_en = 1, \ + .cpu_pd_en = 0, \ + .aon_pd_en = 0, \ + .top_pd_en = 0 \ + }, \ + .clk_power = { \ + .i2c_iso_en = 1, \ + .i2c_retention = 1, \ + .xpd_bb_i2c = 1, \ + .xpd_bbpll_i2c = 0, \ + .xpd_bbpll = 0, \ + }, \ + .xtal = { \ + .xpd_xtal = 0 \ + } \ +} + +const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mode_t mode) +{ + static const pmu_hp_system_power_param_t hp_power[] = { + PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT(), + PMU_HP_MODEM_POWER_CONFIG_DEFAULT(), + PMU_HP_SLEEP_POWER_CONFIG_DEFAULT() + }; + assert(mode < ARRAY_SIZE(hp_power)); + return &hp_power[mode]; +} + +#define PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT() { \ + .icg_func = 0xffffffff, \ + .icg_apb = 0xffffffff, \ + .icg_modem = { \ + .code = PMU_HP_ICG_MODEM_CODE_ACTIVE \ + }, \ + .sysclk = { \ + .dig_sysclk_nodiv = 0, \ + .icg_sysclk_en = 1, \ + .sysclk_slp_sel = 0, \ + .icg_slp_sel = 0, \ + .dig_sysclk_sel = PMU_HP_SYSCLK_XTAL \ + } \ +} + +#define PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT() { \ + .icg_func = 0, \ + .icg_apb = 0, \ + .icg_modem = { \ + .code = PMU_HP_ICG_MODEM_CODE_MODEM \ + }, \ + .sysclk = { \ + .dig_sysclk_nodiv = 0, \ + .icg_sysclk_en = 1, \ + .sysclk_slp_sel = 1, \ + .icg_slp_sel = 1, \ + .dig_sysclk_sel = PMU_HP_SYSCLK_PLL \ + } \ +} + +#define PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT() { \ + .icg_func = 0, \ + .icg_apb = 0, \ + .icg_modem = { \ + .code = PMU_HP_ICG_MODEM_CODE_SLEEP \ + }, \ + .sysclk = { \ + .dig_sysclk_nodiv = 0, \ + .icg_sysclk_en = 0, \ + .sysclk_slp_sel = 1, \ + .icg_slp_sel = 1, \ + .dig_sysclk_sel = PMU_HP_SYSCLK_XTAL \ + } \ +} + +const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mode_t mode) +{ + static const pmu_hp_system_clock_param_t hp_clock[] = { + PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT(), + PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT(), + PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT() + }; + assert(mode < ARRAY_SIZE(hp_clock)); + return &hp_clock[mode]; +} + +#define PMU_HP_ACTIVE_DIGITAL_CONFIG_DEFAULT() { \ + .syscntl = { \ + .uart_wakeup_en = 0, \ + .lp_pad_hold_all = 0, \ + .hp_pad_hold_all = 0, \ + .dig_pad_slp_sel = 0, \ + .dig_pause_wdt = 0, \ + .dig_cpu_stall = 0 \ + } \ +} + +#define PMU_HP_MODEM_DIGITAL_CONFIG_DEFAULT() { \ + .syscntl = { \ + .uart_wakeup_en = 1, \ + .lp_pad_hold_all = 0, \ + .hp_pad_hold_all = 0, \ + .dig_pad_slp_sel = 0, \ + .dig_pause_wdt = 1, \ + .dig_cpu_stall = 1 \ + } \ +} + +#define PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT() { \ + .syscntl = { \ + .uart_wakeup_en = 1, \ + .lp_pad_hold_all = 0, \ + .hp_pad_hold_all = 0, \ + .dig_pad_slp_sel = 1, \ + .dig_pause_wdt = 1, \ + .dig_cpu_stall = 1 \ + } \ +} + +const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp_mode_t mode) +{ + static const pmu_hp_system_digital_param_t hp_digital[] = { + PMU_HP_ACTIVE_DIGITAL_CONFIG_DEFAULT(), + PMU_HP_MODEM_DIGITAL_CONFIG_DEFAULT(), + PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT() + }; + assert(mode < ARRAY_SIZE(hp_digital)); + return &hp_digital[mode]; +} + +#define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \ + .bias = { \ + .xpd_bias = 1, \ + .dbg_atten = 0x0, \ + .pd_cur = 0, \ + .bias_sleep = 0 \ + }, \ + .regulator0 = { \ + .lp_dbias_vol = 0xd, \ + .hp_dbias_vol = 0x1c,\ + .dbias_sel = 1, \ + .dbias_init = 1, \ + .slp_mem_xpd = 0, \ + .slp_logic_xpd = 0, \ + .xpd = 1, \ + .slp_mem_dbias = 0, \ + .slp_logic_dbias = 0, \ + .dbias = HP_CALI_DBIAS_DEFAULT \ + }, \ + .regulator1 = { \ + .drv_b = 0x0 \ + } \ +} + +#define PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT() { \ + .bias = { \ + .xpd_bias = 0, \ + .dbg_atten = 0x0, \ + .pd_cur = 0, \ + .bias_sleep = 0 \ + }, \ + .regulator0 = { \ + .slp_mem_xpd = 0, \ + .slp_logic_xpd = 0, \ + .xpd = 1, \ + .slp_mem_dbias = 0, \ + .slp_logic_dbias = 0, \ + .dbias = HP_CALI_DBIAS_DEFAULT \ + }, \ + .regulator1 = { \ + .drv_b = 0x0 \ + } \ +} + +#define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \ + .bias = { \ + .xpd_bias = 0, \ + .dbg_atten = 0x0, \ + .pd_cur = 0, \ + .bias_sleep = 0 \ + }, \ + .regulator0 = { \ + .slp_mem_xpd = 0, \ + .slp_logic_xpd = 0, \ + .xpd = 1, \ + .slp_mem_dbias = 0, \ + .slp_logic_dbias = 0, \ + .dbias = 1 \ + }, \ + .regulator1 = { \ + .drv_b = 0x0 \ + } \ +} + +const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_mode_t mode) +{ + static const pmu_hp_system_analog_param_t hp_analog[] = { + PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT(), + PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT(), + PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() + }; + assert(mode < ARRAY_SIZE(hp_analog)); + return &hp_analog[mode]; +} + +#define PMU_HP_RETENTION_REGDMA_CONFIG(dir, entry) ((((dir)<<2) | (entry & 0x3)) & 0x7) + +#define PMU_HP_ACTIVE_RETENTION_CONFIG_DEFAULT() { \ + .retention = { \ + .hp_sleep2active_backup_modem_clk_code = 2, \ + .hp_modem2active_backup_modem_clk_code = 2, \ + .hp_active_retention_mode = 0, \ + .hp_sleep2active_retention_en = 0, \ + .hp_modem2active_retention_en = 0, \ + .hp_sleep2active_backup_clk_sel = 0, \ + .hp_modem2active_backup_clk_sel = 1, \ + .hp_sleep2active_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 0), \ + .hp_modem2active_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 2), \ + .hp_sleep2active_backup_en = 0, \ + .hp_modem2active_backup_en = 0, \ + }, \ + .backup_clk = ( \ + BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ + BIT(PMU_ICG_FUNC_ENA_TG0) | \ + BIT(PMU_ICG_FUNC_ENA_TG1) | \ + BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ + BIT(PMU_ICG_FUNC_ENA_MSPI) | \ + BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ + BIT(PMU_ICG_FUNC_ENA_SPI2) | \ + BIT(PMU_ICG_FUNC_ENA_UART0) | \ + BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ + ) \ +} + +#define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \ + .retention = { \ + .hp_sleep2modem_backup_modem_clk_code = 1, \ + .hp_modem_retention_mode = 0, \ + .hp_sleep2modem_retention_en = 0, \ + .hp_sleep2modem_backup_clk_sel = 0, \ + .hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \ + .hp_sleep2modem_backup_en = 0, \ + }, \ + .backup_clk = ( \ + BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ + BIT(PMU_ICG_FUNC_ENA_TG0) | \ + BIT(PMU_ICG_FUNC_ENA_TG1) | \ + BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ + BIT(PMU_ICG_FUNC_ENA_MSPI) | \ + BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ + BIT(PMU_ICG_FUNC_ENA_SPI2) | \ + BIT(PMU_ICG_FUNC_ENA_UART0) | \ + BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ + ) \ +} + +#define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \ + .retention = { \ + .hp_modem2sleep_backup_modem_clk_code = 0, \ + .hp_active2sleep_backup_modem_clk_code = 2, \ + .hp_sleep_retention_mode = 0, \ + .hp_modem2sleep_retention_en = 0, \ + .hp_active2sleep_retention_en = 0, \ + .hp_modem2sleep_backup_clk_sel = 0, \ + .hp_active2sleep_backup_clk_sel = 0, \ + .hp_modem2sleep_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(1, 1), \ + .hp_active2sleep_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(1, 0), \ + .hp_modem2sleep_backup_en = 0, \ + .hp_active2sleep_backup_en = 0, \ + }, \ + .backup_clk = ( \ + BIT(PMU_ICG_FUNC_ENA_REGDMA) | \ + BIT(PMU_ICG_FUNC_ENA_TG0) | \ + BIT(PMU_ICG_FUNC_ENA_TG1) | \ + BIT(PMU_ICG_FUNC_ENA_HPBUS) | \ + BIT(PMU_ICG_FUNC_ENA_MSPI) | \ + BIT(PMU_ICG_FUNC_ENA_IOMUX) | \ + BIT(PMU_ICG_FUNC_ENA_SPI2) | \ + BIT(PMU_ICG_FUNC_ENA_UART0) | \ + BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \ + ) \ +} + +const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode) +{ + static const pmu_hp_system_retention_param_t hp_retention[] = { + PMU_HP_ACTIVE_RETENTION_CONFIG_DEFAULT(), + PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT(), + PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() + }; + assert(mode < ARRAY_SIZE(hp_retention)); + return &hp_retention[mode]; +} + + +/** LP system default parameter */ + +#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL +# define PMU_SLOW_CLK_USE_EXT_XTAL (1) +#else +# define PMU_SLOW_CLK_USE_EXT_XTAL (0) +#endif + +#define PMU_LP_DEFAULT_XPD_RC32K (0) + +#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \ + .dig_power = { \ + .mem_dslp = 0, \ + .peri_pd_en = 0, \ + }, \ + .clk_power = { \ + .xpd_xtal32k = PMU_SLOW_CLK_USE_EXT_XTAL, \ + .xpd_rc32k = PMU_LP_DEFAULT_XPD_RC32K, \ + .xpd_fosc = 1, \ + .pd_osc = 0 \ + } \ +} + +#define PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() { \ + .dig_power = { \ + .mem_dslp = 1, \ + .peri_pd_en = 0, \ + }, \ + .clk_power = { \ + .xpd_xtal32k = 0, \ + .xpd_rc32k = 0, \ + .xpd_fosc = 0, \ + .pd_osc = 0 \ + }, \ + .xtal = { \ + .xpd_xtal = 0 \ + } \ +} + +const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mode_t mode) +{ + static const pmu_lp_system_power_param_t lp_power[] = { + PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT(), + PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() + }; + assert(mode < ARRAY_SIZE(lp_power)); + return &lp_power[mode]; +} + +#define PMU_LP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \ + .regulator0 = { \ + .slp_xpd = 0, \ + .xpd = 1, \ + .slp_dbias = 0, \ + .dbias = LP_CALI_DBIAS_DEFAULT \ + }, \ + .regulator1 = { \ + .drv_b = 0x0 \ + } \ +} + +#define PMU_LP_SLEEP_ANALOG_CONFIG_DEFAULT() { \ + .bias = { \ + .xpd_bias = 0, \ + .dbg_atten = 0, \ + .pd_cur = 1, \ + .bias_sleep = 1, \ + }, \ + .regulator0 = { \ + .slp_xpd = 0, \ + .xpd = 1, \ + .slp_dbias = 0, \ + .dbias = 12 \ + }, \ + .regulator1 = { \ + .drv_b = 0x0 \ + } \ +} + +const pmu_lp_system_analog_param_t * pmu_lp_system_analog_param_default(pmu_lp_mode_t mode) +{ + static const pmu_lp_system_analog_param_t lp_analog[] = { + PMU_LP_ACTIVE_ANALOG_CONFIG_DEFAULT(), + PMU_LP_SLEEP_ANALOG_CONFIG_DEFAULT() + }; + assert(mode < ARRAY_SIZE(lp_analog)); + return &lp_analog[mode]; +} + +uint32_t get_act_hp_dbias(void) +{ + // TODO: IDF-9274 + /* hp_cali_dbias is read from efuse to ensure that the hp_active_voltage is close to 1.15V + */ + uint32_t hp_cali_dbias = HP_CALI_DBIAS_DEFAULT; + // uint32_t blk_version = efuse_hal_blk_version(); + // if (blk_version >= 3) { + // hp_cali_dbias = efuse_ll_get_active_hp_dbias(); + // if (hp_cali_dbias != 0) { + // //efuse dbias need to add 2 to meet the CPU frequency switching + // if (hp_cali_dbias + 2 > 31) { + // hp_cali_dbias = 31; + // } else { + // hp_cali_dbias += 2; + // } + // } else { + // hp_cali_dbias = HP_CALI_DBIAS_DEFAULT; + // ESP_HW_LOGD(TAG, "hp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %" PRIu32 "\n", blk_version); + // } + // } + + return hp_cali_dbias; +} + +uint32_t get_act_lp_dbias(void) +{ + // TODO: IDF-9274 + /* lp_cali_dbias is read from efuse to ensure that the lp_active_voltage is close to 1.15V + */ + uint32_t lp_cali_dbias = LP_CALI_DBIAS_DEFAULT; + // uint32_t blk_version = efuse_hal_blk_version(); + // if (blk_version >= 3) { + // lp_cali_dbias = efuse_ll_get_active_lp_dbias(); + // if (lp_cali_dbias != 0) { + // //efuse dbias need to add 2 to meet the CPU frequency switching + // if (lp_cali_dbias + 2 > 31) { + // lp_cali_dbias = 31; + // } else { + // lp_cali_dbias += 2; + // } + // } else { + // lp_cali_dbias = LP_CALI_DBIAS_DEFAULT; + // ESP_HW_LOGD(TAG, "lp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %" PRIu32 "\n", blk_version); + // } + // } else { + // ESP_HW_LOGD(TAG, "blk_version is less than 3, act dbias not burnt in efuse\n"); + // } + + return lp_cali_dbias; +} diff --git a/components/esp_hw_support/port/esp32c61/private_include/pmu_bit_defs.h b/components/esp_hw_support/port/esp32c61/private_include/pmu_bit_defs.h new file mode 100644 index 0000000000..686855458a --- /dev/null +++ b/components/esp_hw_support/port/esp32c61/private_include/pmu_bit_defs.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-9247 + +#define PMU_EXT0_WAKEUP_EN BIT(0) +#define PMU_EXT1_WAKEUP_EN BIT(1) +#define PMU_GPIO_WAKEUP_EN BIT(2) +#define PMU_WIFI_BEACON_WAKEUP_EN BIT(3) +#define PMU_LP_TIMER_WAKEUP_EN BIT(4) +#define PMU_WIFI_SOC_WAKEUP_EN BIT(5) +#define PMU_UART0_WAKEUP_EN BIT(6) +#define PMU_UART1_WAKEUP_EN BIT(7) +#define PMU_BLE_SOC_WAKEUP_EN BIT(10) +// #define PMU_LP_CORE_WAKEUP_EN BIT(11) +#define PMU_USB_WAKEUP_EN BIT(14) + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h index bbed9cc4a9..ee5384e527 100644 --- a/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h @@ -18,8 +18,8 @@ extern "C" { //TODO: [ESP32C61] IDF-9250 -#define HP_CALI_DBIAS_DEFAULT 25 -#define LP_CALI_DBIAS_DEFAULT 26 +#define HP_CALI_DBIAS_DEFAULT 26 +#define LP_CALI_DBIAS_DEFAULT 25 // FOR XTAL FORCE PU IN SLEEP #define PMU_PD_CUR_SLEEP_ON 0 @@ -49,14 +49,9 @@ extern "C" { #define PMU_HP_XPD_DEEPSLEEP 0 #define PMU_LP_DRVB_DEEPSLEEP 0 -#define PMU_REGDMA_S2A_WORK_TIME_US 480 - #define PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT 12 #define PMU_LP_DBIAS_DEEPSLEEP_0V7_DEFAULT 23 -#define EFUSE_BURN_OFFSET_DSLP_DBG 8 -#define EFUSE_BURN_OFFSET_DSLP_LP_DBIAS 23 - uint32_t get_act_hp_dbias(void); uint32_t get_act_lp_dbias(void); @@ -221,6 +216,8 @@ typedef struct { uint8_t modify_icg_cntl_wait_cycle; uint8_t switch_icg_cntl_wait_cycle; uint8_t min_slp_slow_clk_cycle; + uint8_t isolate_wait_cycle; + uint8_t reset_wait_cycle; } pmu_hp_param_t; typedef struct { @@ -229,6 +226,8 @@ typedef struct { uint8_t analog_wait_target_cycle; uint8_t digital_power_down_wait_cycle; uint8_t digital_power_up_wait_cycle; + uint8_t isolate_wait_cycle; + uint8_t reset_wait_cycle; } pmu_lp_param_t; typedef struct { @@ -424,11 +423,12 @@ typedef struct pmu_sleep_machine_constant { uint16_t min_slp_time_us; /* Minimum sleep protection time (unit: microsecond) */ uint8_t wakeup_wait_cycle; /* Modem wakeup signal (WiFi MAC and BEACON wakeup) waits for the slow & fast clock domain synchronization and the wakeup signal triggers the PMU FSM switching wait cycle (unit: slow clock cycle) */ uint8_t reserved0; - uint16_t reserved1; uint16_t analog_wait_time_us; /* LP LDO power up wait time (unit: microsecond) */ uint16_t xtal_wait_stable_time_us; /* Main XTAL stabilization wait time (unit: microsecond) */ uint8_t clk_switch_cycle; /* Clock switch to FOSC (unit: slow clock cycle) */ uint8_t clk_power_on_wait_cycle; /* Clock power on wait cycle (unit: slow clock cycle) */ + uint8_t isolate_wait_time_us; /* Waiting for all isolate signals to be ready (unit: microsecond) */ + uint8_t reset_wait_time_us; /* Waiting for all reset signals to be ready (unit: microsecond) */ uint16_t power_supply_wait_time_us; /* (unit: microsecond) */ uint16_t power_up_wait_time_us; /* (unit: microsecond) */ } lp; @@ -437,6 +437,8 @@ typedef struct pmu_sleep_machine_constant { uint16_t clock_domain_sync_time_us; /* The Slow OSC clock domain synchronizes time with the Fast OSC domain, at least 4 slow clock cycles (unit: microsecond) */ uint16_t system_dfs_up_work_time_us; /* System DFS up scaling work time (unit: microsecond) */ uint16_t analog_wait_time_us; /* HP LDO power up wait time (unit: microsecond) */ + uint8_t isolate_wait_time_us; /* Waiting for all isolate signals to be ready (unit: microsecond) */ + uint8_t reset_wait_time_us; /* Waiting for all reset signals to be ready (unit: microsecond) */ uint16_t power_supply_wait_time_us; /* (unit: microsecond) */ uint16_t power_up_wait_time_us; /* (unit: microsecond) */ uint16_t regdma_s2m_work_time_us; /* Modem Subsystem (S2M switch) REGDMA restore time (unit: microsecond) */ @@ -458,6 +460,8 @@ typedef struct pmu_sleep_machine_constant { .xtal_wait_stable_time_us = 250, \ .clk_switch_cycle = 1, \ .clk_power_on_wait_cycle = 1, \ + .isolate_wait_time_us = 1, \ + .reset_wait_time_us = 1, \ .power_supply_wait_time_us = 2, \ .power_up_wait_time_us = 2 \ }, \ @@ -466,10 +470,12 @@ typedef struct pmu_sleep_machine_constant { .clock_domain_sync_time_us = 150, \ .system_dfs_up_work_time_us = 124, \ .analog_wait_time_us = 154, \ + .isolate_wait_time_us = 1, \ + .reset_wait_time_us = 1, \ .power_supply_wait_time_us = 2, \ .power_up_wait_time_us = 2, \ .regdma_s2m_work_time_us = 172, \ - .regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_US, \ + .regdma_s2a_work_time_us = 480, \ .regdma_m2a_work_time_us = 278, \ .regdma_a2s_work_time_us = 382, \ .regdma_rf_on_work_time_us = 70, \ diff --git a/components/esp_hw_support/port/esp32c61/rtc_clk.c b/components/esp_hw_support/port/esp32c61/rtc_clk.c index 1f652f17fe..c3cd694dd9 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c61/rtc_clk.c @@ -17,7 +17,7 @@ #include "esp_rom_sys.h" #include "hal/clk_tree_ll.h" #include "hal/regi2c_ctrl_ll.h" -#include "soc/io_mux_reg.h" +#include "hal/gpio_ll.h" #include "soc/lp_aon_reg.h" #include "esp_private/sleep_event.h" @@ -54,9 +54,9 @@ void rtc_clk_32k_enable(bool enable) void rtc_clk_32k_enable_external(void) { // EXT_OSC_SLOW_GPIO_NUM == GPIO_NUM_0 - // PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG); - // REG_SET_BIT(LP_AON_GPIO_HOLD0_REG, BIT(EXT_OSC_SLOW_GPIO_NUM)); - // clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL); + gpio_ll_input_enable(&GPIO, EXT_OSC_SLOW_GPIO_NUM); + REG_SET_BIT(LP_AON_GPIO_HOLD0_REG, BIT(EXT_OSC_SLOW_GPIO_NUM)); + clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL); } void rtc_clk_32k_bootstrap(uint32_t cycle) @@ -169,7 +169,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) clk_ll_bbpll_set_config(pll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); - esp_rom_delay_us(10); + esp_rom_delay_us(10); // wait for true stop /* BBPLL CALIBRATION STOP */ regi2c_ctrl_ll_bbpll_calibration_stop(); rtc_clk_enable_i2c_ana_master_clock(false); @@ -183,29 +183,40 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) */ static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div) { - clk_ll_ahb_set_ls_divider(div); - clk_ll_cpu_set_ls_divider(div); + // let f_cpu = f_ahb + clk_ll_cpu_set_divider(div); + clk_ll_ahb_set_divider(div); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); + clk_ll_bus_update(); esp_rom_set_cpu_ticks_per_us(cpu_freq); } static void rtc_clk_cpu_freq_to_8m(void) { - clk_ll_ahb_set_ls_divider(1); - clk_ll_cpu_set_ls_divider(1); + clk_ll_cpu_set_divider(1); + clk_ll_ahb_set_divider(1); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST); + clk_ll_bus_update(); esp_rom_set_cpu_ticks_per_us(20); } /** - * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL. + * Switch to PLL_F160M as cpu clock source. * PLL must already be enabled. * @param cpu_freq new CPU frequency */ -static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) +static void rtc_clk_cpu_freq_to_pll_160_mhz(int cpu_freq_mhz) { - clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz); - clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL); + // f_hp_root = 160MHz + uint32_t cpu_divider = CLK_LL_PLL_160M_FREQ_MHZ / cpu_freq_mhz; + clk_ll_cpu_set_divider(cpu_divider); + // Constraint: f_ahb <= 40MHz; f_cpu = N * f_ahb (N = 1, 2, 3...) + // let f_ahb = 40MHz + const uint32_t ahb_divider = 4; + assert((cpu_divider <= ahb_divider) && (ahb_divider % cpu_divider == 0)); + clk_ll_ahb_set_divider(ahb_divider); + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL_F160M); + clk_ll_bus_update(); esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); } @@ -229,19 +240,14 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou source = SOC_CPU_CLK_SRC_XTAL; } else if (freq_mhz == 80) { real_freq_mhz = freq_mhz; - source = SOC_CPU_CLK_SRC_PLL; - source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; - divider = 6; - } else if (freq_mhz == 120) { - real_freq_mhz = freq_mhz; - source = SOC_CPU_CLK_SRC_PLL; - source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; - divider = 4; + source = SOC_CPU_CLK_SRC_PLL_F160M; + source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; + divider = 2; } else if (freq_mhz == 160) { real_freq_mhz = freq_mhz; - source = SOC_CPU_CLK_SRC_PLL; - source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ; - divider = 3; + source = SOC_CPU_CLK_SRC_PLL_F160M; + source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; + divider = 1; } else { // unsupported frequency return false; @@ -264,21 +270,21 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src(); if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) { + if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) && !s_bbpll_digi_consumers_ref_count) { // We don't turn off the bbpll if some consumers depend on bbpll rtc_clk_bbpll_disable(); } - } else if (config->source == SOC_CPU_CLK_SRC_PLL) { - if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL) { + } else if (config->source == SOC_CPU_CLK_SRC_PLL_F160M) { + if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F160M) { rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_PLL_EN_START); rtc_clk_bbpll_enable(); - rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz); + rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_480M_FREQ_MHZ); } - rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); + rtc_clk_cpu_freq_to_pll_160_mhz(config->freq_mhz); rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_PLL_EN_STOP); } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { rtc_clk_cpu_freq_to_8m(); - if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) { + if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) && !s_bbpll_digi_consumers_ref_count) { // We don't turn off the bbpll if some consumers depend on bbpll rtc_clk_bbpll_disable(); } @@ -289,30 +295,24 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) { soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); uint32_t source_freq_mhz; - uint32_t div; // div = freq of SOC_ROOT_CLK / freq of CPU_CLK - uint32_t freq_mhz; switch (source) { case SOC_CPU_CLK_SRC_XTAL: { - div = clk_ll_cpu_get_ls_divider(); source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get(); - freq_mhz = source_freq_mhz / div; break; } - case SOC_CPU_CLK_SRC_PLL: { - div = clk_ll_cpu_get_hs_divider(); - source_freq_mhz = clk_ll_bbpll_get_freq_mhz(); - freq_mhz = source_freq_mhz / div; + case SOC_CPU_CLK_SRC_PLL_F160M: { + source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; break; } case SOC_CPU_CLK_SRC_RC_FAST: - div = clk_ll_cpu_get_ls_divider(); source_freq_mhz = 20; - freq_mhz = source_freq_mhz / div; break; default: ESP_HW_LOGE(TAG, "unsupported frequency configuration"); abort(); } + uint32_t div = clk_ll_cpu_get_divider(); + uint32_t freq_mhz = source_freq_mhz / div; // freq of CPU_CLK = freq of SOC_ROOT_CLK / cpu_div *out_config = (rtc_cpu_freq_config_t) { .source = source, .source_freq_mhz = source_freq_mhz, @@ -325,9 +325,9 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) { if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - } else if (config->source == SOC_CPU_CLK_SRC_PLL && - s_cur_pll_freq == config->source_freq_mhz) { - rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); + } else if (config->source == SOC_CPU_CLK_SRC_PLL_F160M && + s_cur_pll_freq == CLK_LL_PLL_480M_FREQ_MHZ) { + rtc_clk_cpu_freq_to_pll_160_mhz(config->freq_mhz); } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { rtc_clk_cpu_freq_to_8m(); } else { @@ -354,51 +354,38 @@ void rtc_clk_cpu_set_to_default_config(void) void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) { - rtc_clk_cpu_freq_to_pll_mhz(cpu_freq_mhz); + rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz); clk_ll_cpu_clk_src_lock_release(); } soc_xtal_freq_t rtc_clk_xtal_freq_get(void) { - uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz(); - if (xtal_freq_mhz == 0) { - ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz"); - return SOC_XTAL_FREQ_40M; - } + uint32_t xtal_freq_mhz = clk_ll_xtal_get_freq_mhz(); + assert(xtal_freq_mhz == SOC_XTAL_FREQ_40M); return (soc_xtal_freq_t)xtal_freq_mhz; } -void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq) -{ - clk_ll_xtal_store_freq_mhz(xtal_freq); -} - static uint32_t rtc_clk_ahb_freq_get(void) { soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); uint32_t soc_root_freq_mhz; - uint32_t divider; switch (source) { case SOC_CPU_CLK_SRC_XTAL: soc_root_freq_mhz = rtc_clk_xtal_freq_get(); - divider = clk_ll_ahb_get_ls_divider(); break; - case SOC_CPU_CLK_SRC_PLL: - soc_root_freq_mhz = clk_ll_bbpll_get_freq_mhz(); - divider = clk_ll_ahb_get_hs_divider(); + case SOC_CPU_CLK_SRC_PLL_F160M: + soc_root_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; break; case SOC_CPU_CLK_SRC_RC_FAST: soc_root_freq_mhz = 20; - divider = clk_ll_ahb_get_ls_divider(); break; default: // Unknown SOC_ROOT clock source soc_root_freq_mhz = 0; - divider = 1; ESP_HW_LOGE(TAG, "Invalid SOC_ROOT_CLK"); break; } - return soc_root_freq_mhz / divider; + return soc_root_freq_mhz / clk_ll_ahb_get_divider(); } uint32_t rtc_clk_apb_freq_get(void) @@ -422,8 +409,3 @@ bool rtc_dig_8m_enabled(void) { return clk_ll_rc_fast_digi_is_enabled(); } - -/* Name used in libphy.a:phy_chip_v7.o - * TODO: update the library to use rtc_clk_xtal_freq_get - */ -rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get"))); diff --git a/components/esp_hw_support/port/esp32c61/rtc_clk_init.c b/components/esp_hw_support/port/esp32c61/rtc_clk_init.c index 6d8ce23aac..8403fc90a4 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c61/rtc_clk_init.c @@ -65,7 +65,7 @@ void rtc_clk_init(rtc_clk_config_t cfg) { rtc_cpu_freq_config_t old_config, new_config; - rtc_clk_modem_clock_domain_active_state_icg_map_preinit(); + rtc_clk_modem_clock_domain_active_state_icg_map_preinit(); // TODO: comment? /* Set tuning parameters for RC_FAST, RC_SLOW, and RC32K clocks. * Note: this doesn't attempt to set the clocks to precise frequencies. @@ -89,16 +89,9 @@ void rtc_clk_init(rtc_clk_config_t cfg) SET_PERI_REG_BITS(PMU_HP_MODEM_HP_REGULATOR0_REG, PMU_HP_MODEM_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S); SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S); - clk_ll_rc_fast_tick_conf(); + // XTAL freq can be directly informed from register field PCR_CLK_XTAL_FREQ - soc_xtal_freq_t xtal_freq = cfg.xtal_freq; - esp_rom_output_tx_wait_idle(0); - rtc_clk_xtal_freq_update(xtal_freq); - - // On ESP32C61, MSPI source clock's default HS divider leads to 120MHz, which is unusable before calibration - // Therefore, before switching SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider to make it run at - // 80MHz after the switch. PLL = 480MHz, so divider is 6. - clk_ll_mspi_fast_set_hs_divider(6); + // No need to wait UART0 TX idle since its default clock source is XTAL, should not be affected by system clock configuration /* Set CPU frequency */ rtc_clk_cpu_freq_get_config(&old_config); diff --git a/components/esp_hw_support/port/esp32c61/rtc_time.c b/components/esp_hw_support/port/esp32c61/rtc_time.c index c3c6f35661..b1278dc5e9 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_time.c +++ b/components/esp_hw_support/port/esp32c61/rtc_time.c @@ -11,10 +11,9 @@ #include "hal/clk_tree_ll.h" #include "hal/timer_ll.h" #include "soc/timer_group_reg.h" +#include "soc/pcr_reg.h" #include "esp_rom_sys.h" #include "assert.h" -#include "hal/efuse_hal.h" -#include "soc/chip_revision.h" #include "esp_private/periph_ctrl.h" __attribute__((unused)) static const char *TAG = "rtc_time"; @@ -22,62 +21,31 @@ __attribute__((unused)) static const char *TAG = "rtc_time"; /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. * This feature counts the number of XTAL clock cycles within a given number of * RTC_SLOW_CLK cycles. - * - * Slow clock calibration feature has two modes of operation: one-off and cycling. - * In cycling mode (which is enabled by default on SoC reset), counting of XTAL - * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled - * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed - * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is - * enabled using TIMG_RTC_CALI_START bit. */ -/* On ESP32C61, TIMG_RTC_CALI_CLK_SEL can config to 0, 1, 2, 3 - * 0 or 3: calibrate RC_SLOW clock - * 1: calibrate RC_FAST clock - * 2: calibrate 32K clock, which 32k depends on reg_32k_sel: 0: Internal 32 kHz RC oscillator, 1: External 32 kHz XTAL, 2: External 32kHz clock input by lp_pad_gpio0 - */ -#define TIMG_RTC_CALI_CLK_SEL_RC_SLOW 0 -#define TIMG_RTC_CALI_CLK_SEL_RC_FAST 1 -#define TIMG_RTC_CALI_CLK_SEL_32K 2 +#define CLK_CAL_TIMEOUT_THRES(cal_clk, cycles) ((cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10)) -/** - * @brief Clock calibration function used by rtc_clk_cal - * - * Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. - * This feature counts the number of XTAL clock cycles within a given number of - * RTC_SLOW_CLK cycles. - * - * Slow clock calibration feature has two modes of operation: one-off and cycling. - * In cycling mode (which is enabled by default on SoC reset), counting of XTAL - * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled - * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed - * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is - * enabled using TIMG_RTC_CALI_START bit. - * - * @param cal_clk which clock to calibrate - * @param slowclk_cycles number of slow clock cycles to count - * @return number of XTAL clock cycles within the given number of slow clock cycles - */ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V); - uint32_t cali_clk_sel = 0; - soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); - soc_rtc_slow_clk_src_t old_32k_cal_clk_sel = clk_ll_32k_calibration_get_target(); if (cal_clk == RTC_CAL_RTC_MUX) { - cal_clk = (rtc_cal_sel_t)slow_clk_src; + soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); + if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) { + cal_clk = RTC_CAL_RC_SLOW; + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + cal_clk = RTC_CAL_32K_XTAL; + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { + cal_clk = RTC_CAL_RC32K; + } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { + cal_clk = RTC_CAL_32K_OSC_SLOW; + } } - if (cal_clk == RTC_CAL_RC_FAST) { - cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_FAST; - } else if (cal_clk == RTC_CAL_RC_SLOW) { - cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_SLOW; - } else { - cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_32K; - clk_ll_32k_calibration_set_target((soc_rtc_slow_clk_src_t)cal_clk); + if (cal_clk < 0 || cal_clk >= RTC_CAL_INVALID_CLK) { + ESP_EARLY_LOGE(TAG, "clock not supported to be calibrated"); + return 0; } - /* Enable requested clock (150k clock is always on) */ // All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock // Only enable if originally was disabled, and set back to the disable state after calibration is done @@ -123,21 +91,22 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc } /* Prepare calibration */ - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel); + REG_SET_FIELD(PCR_CTRL_32K_CONF_REG, PCR_32K_SEL, cal_clk); + if (cal_clk == RTC_CAL_RC_FAST) { + clk_ll_rc_fast_tick_conf(); + } CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); /* Figure out how long to wait for calibration to finish */ /* Set timeout reg and expect time delay*/ + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk, slowclk_cycles)); uint32_t expected_freq; - if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_32K) { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles)); + if (cal_clk == RTC_CAL_RC32K || cal_clk == RTC_CAL_32K_XTAL || cal_clk == RTC_CAL_32K_OSC_SLOW) { expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; - } else if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_RC_FAST) { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX; + } else if (cal_clk == RTC_CAL_RC_FAST) { + expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; } else { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; } uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); @@ -152,13 +121,10 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); - /*The Fosc CLK of calibration circuit is divided by 32 for ECO1. - So we need to multiply the frequency of the Fosc for ECO1 and above chips by 32 times. - And ensure that this modification will not affect ECO0.*/ - if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { - if (cal_clk == RTC_CAL_RC_FAST) { - cal_val = cal_val >> 5; - } + /*The Fosc CLK of calibration circuit is divided by a factor, k. + So we need to multiply the frequency of the FOSC by k times.*/ + if (cal_clk == RTC_CAL_RC_FAST) { + cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; } break; } @@ -192,11 +158,6 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc } } - // Always set back the calibration 32kHz clock selection - if (old_32k_cal_clk_sel != SOC_RTC_SLOW_CLK_SRC_INVALID) { - clk_ll_32k_calibration_set_target(old_32k_cal_clk_sel); - } - return cal_val; } @@ -209,18 +170,15 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { - assert(slowclk_cycles); - soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); - - /*The Fosc CLK of calibration circuit is divided by 32 for ECO1. - So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to + /*The Fosc CLK of calibration circuit is divided by a factor, k. + So we need to divide the calibrate cycles of the FOSC by k to avoid excessive calibration time.*/ - if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { - if (cal_clk == RTC_CAL_RC_FAST) { - slowclk_cycles = slowclk_cycles >> 5; - } + if (cal_clk == RTC_CAL_RC_FAST) { + slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; } + assert(slowclk_cycles); + soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) { @@ -250,7 +208,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period) uint64_t rtc_time_get(void) { // return lp_timer_hal_get_cycle_count(); - ESP_EARLY_LOGW(TAG, "rtc_timer has not been implemented yet"); + ESP_EARLY_LOGW(TAG, "rtc_timer has not been implemented yet"); // TODO: IDF-9244 return 0; } diff --git a/components/esp_hw_support/port/esp32h2/rtc_time.c b/components/esp_hw_support/port/esp32h2/rtc_time.c index 7db712d7a6..e5bc0616ab 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_time.c +++ b/components/esp_hw_support/port/esp32h2/rtc_time.c @@ -141,7 +141,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(slowclk_cycles)); expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX; if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) { - expected_freq = expected_freq >> CLK_LL_RC_FAST_TICK_DIV_BITS; + expected_freq = expected_freq >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; } } else { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); @@ -166,7 +166,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc calibration. */ if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) { if (cal_clk == RTC_CAL_RC_FAST) { - cal_val = cal_val >> CLK_LL_RC_FAST_TICK_DIV_BITS; + cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); } } @@ -227,7 +227,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) avoid excessive calibration time.*/ if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) { if (cal_clk == RTC_CAL_RC_FAST) { - slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_TICK_DIV_BITS; + slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS; SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); } } diff --git a/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h b/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h index a49f74d367..07c8a166bf 100644 --- a/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h +++ b/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h @@ -210,7 +210,7 @@ void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length); static inline void rtc_suppress_rom_log(void) { /* To disable logging in the ROM, only the least significant bit of the register is used, - * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG), + * but this register was also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG) on old targets, * you need to write to this register in the same format. * Namely, the upper 16 bits and lower should be the same. */ diff --git a/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h b/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h index fc3e04e161..c9c6663ba2 100644 --- a/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h +++ b/components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h @@ -211,7 +211,7 @@ void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length); static inline void rtc_suppress_rom_log(void) { /* To disable logging in the ROM, only the least significant bit of the register is used, - * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG), + * but this register was also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG) on old targets, * you need to write to this register in the same format. * Namely, the upper 16 bits and lower should be the same. */ diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c b/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c index b25b405fcc..4f75c8adff 100644 --- a/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c @@ -6,7 +6,6 @@ #include "esp_rom_sys.h" #include "esp_attr.h" #include "soc/i2c_ana_mst_reg.h" -#include "soc/pmu_reg.h" // TODO: IDF-9249 Can be removed #include "hal/regi2c_ctrl_ll.h" #define REGI2C_BIAS_MST_SEL (BIT(8)) @@ -77,8 +76,6 @@ static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) uint32_t i2c_sel = 0; regi2c_ctrl_ll_master_enable_clock(true); - REG_SET_BIT(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); // TODO: IDF-9249 Move to pmu_init() - REG_SET_BIT(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C); // TODO: IDF-9249 Move to pmu_init() /* Before config I2C register, enable corresponding slave. */ switch (block) { diff --git a/components/esp_system/port/soc/esp32c61/CMakeLists.txt b/components/esp_system/port/soc/esp32c61/CMakeLists.txt index 28d8f18863..23b1cb7466 100644 --- a/components/esp_system/port/soc/esp32c61/CMakeLists.txt +++ b/components/esp_system/port/soc/esp32c61/CMakeLists.txt @@ -1,5 +1,5 @@ # TODO: IDF-9526, refactor this -set(srcs +set(srcs "clk.c" "reset_reason.c" "system_internal.c" "cache_err_int.c") diff --git a/components/esp_system/port/soc/esp32c61/Kconfig.cpu b/components/esp_system/port/soc/esp32c61/Kconfig.cpu index 2b5a7e45b8..414e4377f3 100644 --- a/components/esp_system/port/soc/esp32c61/Kconfig.cpu +++ b/components/esp_system/port/soc/esp32c61/Kconfig.cpu @@ -10,8 +10,6 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ depends on IDF_ENV_FPGA config ESP_DEFAULT_CPU_FREQ_MHZ_80 bool "80 MHz" - config ESP_DEFAULT_CPU_FREQ_MHZ_120 - bool "120 MHz" config ESP_DEFAULT_CPU_FREQ_MHZ_160 bool "160 MHz" endchoice @@ -20,5 +18,4 @@ config ESP_DEFAULT_CPU_FREQ_MHZ int default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40 default 80 if ESP_DEFAULT_CPU_FREQ_MHZ_80 - default 120 if ESP_DEFAULT_CPU_FREQ_MHZ_120 default 160 if ESP_DEFAULT_CPU_FREQ_MHZ_160 diff --git a/components/esp_system/port/soc/esp32c61/clk.c b/components/esp_system/port/soc/esp32c61/clk.c index 9a82793f6f..eb6e6b8f2c 100644 --- a/components/esp_system/port/soc/esp32c61/clk.c +++ b/components/esp_system/port/soc/esp32c61/clk.c @@ -25,9 +25,6 @@ #include "esp_private/esp_pmu.h" #include "esp_rom_uart.h" #include "esp_rom_sys.h" -#include "ocode_init.h" - -// TODO: [ESP32C61] IDF-9249 /* Number of cycles to wait from the 32k XTAL oscillator to consider it running. * Larger values increase startup delay. Smaller values may cause false positive @@ -45,9 +42,6 @@ void esp_rtc_init(void) { #if !CONFIG_IDF_ENV_FPGA pmu_init(); - if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) { - esp_ocode_calib_init(); - } #endif } @@ -104,7 +98,9 @@ __attribute__((weak)) void esp_clk_init(void) // Wait for UART TX to finish, otherwise some UART output will be lost // when switching APB frequency - esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM); + if (CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM != -1) { + esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM); + } if (res) { rtc_clk_cpu_freq_set_config(&new_config); @@ -183,6 +179,7 @@ void rtc_clk_select_rtc_slow_clk(void) */ __attribute__((weak)) void esp_perip_clk_init(void) { +#if SOC_MODEM_CLOCK_SUPPORTED /* During system initialization, the low-power clock source of the modem * (WiFi, BLE or Coexist) follows the configuration of the slow clock source * of the system. If the WiFi, BLE or Coexist module needs a higher @@ -198,6 +195,7 @@ __attribute__((weak)) void esp_perip_clk_init(void) : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K : SOC_RTC_SLOW_CLK_SRC_RC_SLOW); modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0); +#endif ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); } diff --git a/components/esp_system/port/soc/esp32c61/system_internal.c b/components/esp_system/port/soc/esp32c61/system_internal.c index fa61e67022..a4f9e17b12 100644 --- a/components/esp_system/port/soc/esp32c61/system_internal.c +++ b/components/esp_system/port/soc/esp32c61/system_internal.c @@ -98,7 +98,7 @@ void IRAM_ATTR esp_restart_noos(void) // Disable cache Cache_Disable_Cache(); - //TODO: [ESP32C61] IDF-9249, inherit from verify code + //TODO: [ESP32C61] IDF-9553, inherit from verify code // Reset wifi/bluetooth/ethernet/sdio (bb/mac) // Moved to module internal // SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, diff --git a/components/esptool_py/Kconfig.projbuild b/components/esptool_py/Kconfig.projbuild index 5877ada398..fac3998ae1 100644 --- a/components/esptool_py/Kconfig.projbuild +++ b/components/esptool_py/Kconfig.projbuild @@ -4,7 +4,7 @@ menu "Serial flasher config" config ESPTOOLPY_NO_STUB bool "Disable download stub" default y if IDF_ENV_FPGA || IDF_ENV_BRINGUP - default y if IDF_TARGET_ESP32C5 # TODO: IDF-8631 to be removed + default y if IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61 # TODO: IDF-8631, IDF-9241 to be removed default n help diff --git a/components/hal/esp32c5/clk_tree_hal.c b/components/hal/esp32c5/clk_tree_hal.c index b7ac7939f2..c79d0d8276 100644 --- a/components/hal/esp32c5/clk_tree_hal.c +++ b/components/hal/esp32c5/clk_tree_hal.c @@ -10,7 +10,6 @@ #include "hal/clk_tree_ll.h" #include "hal/gpio_ll.h" #include "hal/log.h" -#include "sdkconfig.h" uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src) { diff --git a/components/hal/esp32c5/include/hal/clk_tree_ll.h b/components/hal/esp32c5/include/hal/clk_tree_ll.h index 08eaa2747e..094850e496 100644 --- a/components/hal/esp32c5/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c5/include/hal/clk_tree_ll.h @@ -41,7 +41,7 @@ extern "C" { } // Fix default division factor for the RC_FAST clock for calibration to be 32 -#define CLK_LL_RC_FAST_TICK_DIV_BITS 5 +#define CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS 5 /** * @brief XTAL32K_CLK enable modes @@ -274,7 +274,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(v } /** - * @brief Get PLL_CLK frequency + * @brief Get SPLL_CLK frequency * * @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid. */ @@ -407,6 +407,8 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr /** * @brief Set CPU_CLK's divider * + * SOC_ROOT_CLK ------> CPU_CLK + * * @param divider Divider. (PCR_CPU_DIV_NUM + 1) = divider. */ static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider) @@ -428,6 +430,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi /** * @brief Set AHB_CLK's divider * + * SOC_ROOT_CLK ------> AHB_CLK * Constraint: f_ahb <= 48 MHz, f_cpu = n * f_ahb * * @param divider Divider. (PCR_AHB_DIV_NUM + 1) = divider. @@ -576,7 +579,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uin /** * @brief Get RC_FAST_CLK divider * - * @return Divider. Divider = (CK8M_DIV_SEL + 1). + * @return Divider */ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { @@ -589,7 +592,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider */ static inline void clk_ll_rc_fast_tick_conf(void) { - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_TICK_DIV_BITS + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS } /** diff --git a/components/hal/esp32c6/include/hal/clk_tree_ll.h b/components/hal/esp32c6/include/hal/clk_tree_ll.h index 30aa05e1ad..90df2e69b3 100644 --- a/components/hal/esp32c6/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c6/include/hal/clk_tree_ll.h @@ -44,7 +44,7 @@ Set the frequency division factor of ref_tick The FOSC of rtc calibration uses the 32 frequency division clock for ECO1, So the frequency division factor of ref_tick must be greater than or equal to 32 */ -#define CLK_LL_RC_FAST_TICK_DIV_BITS 5 +#define CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS 5 #define REG_FOSC_TICK_NUM 255 /** @@ -719,7 +719,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uin /** * @brief Get RC_FAST_CLK divider * - * @return Divider. Divider = (CK8M_DIV_SEL + 1). + * @return Divider */ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { diff --git a/components/hal/esp32c61/clk_tree_hal.c b/components/hal/esp32c61/clk_tree_hal.c index 744b25f4b5..ad7f715260 100644 --- a/components/hal/esp32c61/clk_tree_hal.c +++ b/components/hal/esp32c61/clk_tree_hal.c @@ -9,15 +9,13 @@ #include "hal/assert.h" #include "hal/log.h" -static const char *CLK_HAL_TAG = "clk_hal"; - uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src) { switch (cpu_clk_src) { case SOC_CPU_CLK_SRC_XTAL: return clk_hal_xtal_get_freq_mhz(); - case SOC_CPU_CLK_SRC_PLL: - return clk_ll_bbpll_get_freq_mhz(); + case SOC_CPU_CLK_SRC_PLL_F160M: + return CLK_LL_PLL_160M_FREQ_MHZ; case SOC_CPU_CLK_SRC_RC_FAST: return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ; default: @@ -30,14 +28,14 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src) uint32_t clk_hal_cpu_get_freq_hz(void) { soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); - uint32_t divider = (source == SOC_CPU_CLK_SRC_PLL) ? clk_ll_cpu_get_hs_divider() : clk_ll_cpu_get_ls_divider(); + uint32_t divider = clk_ll_cpu_get_divider(); return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider; } static uint32_t clk_hal_ahb_get_freq_hz(void) { soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); - uint32_t divider = (source == SOC_CPU_CLK_SRC_PLL) ? clk_ll_ahb_get_hs_divider() : clk_ll_ahb_get_ls_divider(); + uint32_t divider = clk_ll_ahb_get_divider(); return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider; } @@ -66,10 +64,7 @@ uint32_t clk_hal_lp_slow_get_freq_hz(void) uint32_t clk_hal_xtal_get_freq_mhz(void) { - uint32_t freq = clk_ll_xtal_load_freq_mhz(); - if (freq == 0) { - HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz"); - return (uint32_t)SOC_XTAL_FREQ_40M; - } + uint32_t freq = clk_ll_xtal_get_freq_mhz(); + HAL_ASSERT(freq == SOC_XTAL_FREQ_40M); return freq; } diff --git a/components/hal/esp32c61/include/hal/clk_tree_ll.h b/components/hal/esp32c61/include/hal/clk_tree_ll.h index 8ed04659a1..8eadfa9fbe 100644 --- a/components/hal/esp32c61/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c61/include/hal/clk_tree_ll.h @@ -6,8 +6,6 @@ #pragma once -// TODO: [ESP32C61] IDF-9249, inherit from ESP32C6 - #include #include "soc/soc.h" #include "soc/clk_tree_defs.h" @@ -30,7 +28,6 @@ extern "C" { #define CLK_LL_PLL_80M_FREQ_MHZ (80) #define CLK_LL_PLL_120M_FREQ_MHZ (120) #define CLK_LL_PLL_160M_FREQ_MHZ (160) -#define CLK_LL_PLL_240M_FREQ_MHZ (240) #define CLK_LL_PLL_480M_FREQ_MHZ (480) @@ -41,12 +38,8 @@ extern "C" { .dbuf = 1, \ } -/* -Set the frequency division factor of ref_tick -The FOSC of rtc calibration uses the 32 frequency division clock for ECO1, -So the frequency division factor of ref_tick must be greater than or equal to 32 -*/ -#define REG_FOSC_TICK_NUM 255 +// Fix default division factor for the RC_FAST clock for calibration to be 32 +#define CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS 5 /** * @brief XTAL32K_CLK enable modes @@ -267,7 +260,17 @@ static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(v } /** - * @brief Get PLL_CLK frequency + * @brief Get XTAL_CLK frequency + * + * @return Main XTAL clock frequency, in MHz. + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(void) +{ + return PCR.sysclk_conf.clk_xtal_freq; +} + +/** + * @brief Get SPLL_CLK frequency * * @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid. */ @@ -278,7 +281,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz( } /** - * @brief Set BBPLL frequency from XTAL source (Digital part) + * @brief Set SPLL frequency from XTAL source (Digital part) * * @param pll_freq_mhz PLL frequency, in MHz */ @@ -289,8 +292,8 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ); } -/** - * @brief Set BBPLL frequency from XTAL source (Analog part) +/** TODO + * @brief Set SPLL frequency from XTAL source (Analog part) * * @param pll_freq_mhz PLL frequency, in MHz * @param xtal_freq_mhz XTAL frequency, in MHz @@ -300,11 +303,10 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ); uint8_t div_ref; uint8_t div7_0; - uint8_t dr1; - uint8_t dr3; - uint8_t dchgp; - uint8_t dcur; - uint8_t dbias; + uint8_t dchgp = 5; + uint8_t dbias = 3; + uint8_t href = 3; + uint8_t lref = 1; /* Configure 480M PLL */ switch (xtal_freq_mhz) { @@ -312,24 +314,26 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 default: div_ref = 0; div7_0 = 8; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 3; - dbias = 2; break; } uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref); uint8_t i2c_bbpll_div_7_0 = div7_0; - uint8_t i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref); REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, lref); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, href); REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); } +/** + * @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num + */ +static inline __attribute__((always_inline)) void clk_ll_bus_update(void) +{ + PCR.bus_clk_update.bus_clock_update = 1; + while (PCR.bus_clk_update.bus_clock_update); +} + /** * @brief Select the clock source for CPU_CLK (SOC Clock Root) * @@ -341,10 +345,10 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk case SOC_CPU_CLK_SRC_XTAL: PCR.sysclk_conf.soc_clk_sel = 0; break; - case SOC_CPU_CLK_SRC_PLL: + case SOC_CPU_CLK_SRC_RC_FAST: PCR.sysclk_conf.soc_clk_sel = 1; break; - case SOC_CPU_CLK_SRC_RC_FAST: + case SOC_CPU_CLK_SRC_PLL_F160M: PCR.sysclk_conf.soc_clk_sel = 2; break; default: @@ -365,9 +369,9 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr case 0: return SOC_CPU_CLK_SRC_XTAL; case 1: - return SOC_CPU_CLK_SRC_PLL; - case 2: return SOC_CPU_CLK_SRC_RC_FAST; + case 2: + return SOC_CPU_CLK_SRC_PLL_F160M; default: // Invalid SOC_CLK_SEL value return SOC_CPU_CLK_SRC_INVALID; @@ -375,125 +379,50 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr } /** - * @brief Set CPU_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL) + * @brief Set CPU_CLK's divider * - * @param divider Divider. (PCR_HS_DIV_NUM + 1) * (PCR_CPU_HS_DIV_NUM + 1) = divider. + * SOC_ROOT_CLK ------> CPU_CLK + * + * @param divider Divider. (PCR_CPU_DIV_NUM + 1) = divider. */ -static inline __attribute__((always_inline)) void clk_ll_cpu_set_hs_divider(uint32_t divider) +static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider) { - // SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> CPU_CLK - // (1) not configurable for the target (HRO register field: PCR_HS_DIV_NUM) - // Fixed at 3 for HS clock source - // Corresponding register field value is PCR_HS_DIV_NUM=2 - // (2) configurable - // HS divider option: 1, 2, 4 (PCR_CPU_HS_DIV_NUM=0, 1, 3) - - HAL_ASSERT(divider == 3 || divider == 4 || divider == 6 || divider == 12); - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, (divider / 3) - 1); - - // 120MHz CPU freq cannot be achieved through divider, need to set force_120m - // This field is only valid if PCR_CPU_HS_DIV_NUM=0 and PCR_SOC_CLK_SEL=SOC_CPU_CLK_SRC_PLL - // bool force_120m = (divider == 4) ? 1 : 0; - // PCR.cpu_freq_conf.cpu_hs_120m_force = force_120m; + HAL_ASSERT(divider >= 1); + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, (divider) - 1); } /** - * @brief Set CPU_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST) + * @brief Get CPU_CLK's divider * - * @param divider Divider. (PCR_LS_DIV_NUM + 1) * (PCR_CPU_LS_DIV_NUM + 1) = divider. + * @return Divider. Divider = (PCR_CPU_DIV_NUM + 1). */ -static inline __attribute__((always_inline)) void clk_ll_cpu_set_ls_divider(uint32_t divider) +static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(void) { - // SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> CPU_CLK - // (1) not configurable for the target (HRO register field: PCR_LS_DIV_NUM) - // Fixed at 1 for LS clock source - // Corresponding register field value is PCR_LS_DIV_NUM=0 - // (2) configurable - // LS divider option: 1, 2, 4, 8, 16, 32 (PCR_CPU_LS_DIV_NUM=0, 1, 3, 7, 15, 31) - HAL_ASSERT((divider > 0) && ((divider & (divider - 1)) == 0)); - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, divider - 1); + return HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num) + 1; } /** - * @brief Get CPU_CLK's high-speed divider + * @brief Set AHB_CLK's divider * - * @return Divider. Divider = (PCR_HS_DIV_NUM + 1) * (PCR_CPU_HS_DIV_NUM + 1). - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_hs_divider(void) -{ - uint32_t cpu_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num); - uint32_t hp_root_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, hs_div_num); - return (hp_root_hs_div + 1) * (cpu_hs_div + 1); -} - -/** - * @brief Get CPU_CLK's low-speed divider + * SOC_ROOT_CLK ------> AHB_CLK + * Constraint: f_ahb <= 40 MHz, f_cpu = n * f_ahb * - * @return Divider. Divider = (PCR_LS_DIV_NUM + 1) * (PCR_CPU_LS_DIV_NUM + 1). + * @param divider Divider. (PCR_AHB_DIV_NUM + 1) = divider. */ -static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_ls_divider(void) +static inline __attribute__((always_inline)) void clk_ll_ahb_set_divider(uint32_t divider) { - uint32_t cpu_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num); - uint32_t hp_root_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, ls_div_num); - return (hp_root_ls_div + 1) * (cpu_ls_div + 1); -} - -/** - * @brief Set AHB_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL) - * - * @param divider Divider. (PCR_HS_DIV_NUM + 1) * (PCR_AHB_HS_DIV_NUM + 1) = divider. - */ -static inline __attribute__((always_inline)) void clk_ll_ahb_set_hs_divider(uint32_t divider) -{ - // SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> AHB_CLK - // (1) not configurable for the target (HRO register field: PCR_HS_DIV_NUM) - // Fixed at 3 for HS clock source - // Corresponding register field value is PCR_HS_DIV_NUM=2 - // (2) configurable - // HS divider option: 4, 8, 16 (PCR_AHB_HS_DIV_NUM=3, 7, 15) - HAL_ASSERT(divider == 12 || divider == 24 || divider == 48); - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, (divider / 3) - 1); -} - -/** - * @brief Set AHB_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST) - * - * @param divider Divider. (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1) = divider. - */ -static inline __attribute__((always_inline)) void clk_ll_ahb_set_ls_divider(uint32_t divider) -{ - // SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> AHB_CLK - // (1) not configurable for the target (HRO register field: PCR_LS_DIV_NUM) - // Fixed at 1 for LS clock source - // Corresponding register field value is PCR_LS_DIV_NUM=0 - // (2) configurable - // LS divider option: 1, 2, 4, 8, 16, 32 (PCR_CPU_LS_DIV_NUM=0, 1, 3, 7, 15, 31) - HAL_ASSERT((divider > 0) && ((divider & (divider - 1)) == 0)); + HAL_ASSERT(divider >= 1); HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, divider - 1); } /** - * @brief Get AHB_CLK's high-speed divider + * @brief Get AHB_CLK's divider * - * @return Divider. Divider = (PCR_HS_DIV_NUM + 1) * (PCR_AHB_HS_DIV_NUM + 1). + * @return Divider. Divider = (PCR_AHB_DIV_NUM + 1). */ -static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_hs_divider(void) +static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_divider(void) { - uint32_t ahb_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num); - uint32_t hp_root_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, hs_div_num); - return (hp_root_hs_div + 1) * (ahb_hs_div + 1); -} - -/** - * @brief Get AHB_CLK's low-speed divider - * - * @return Divider. Divider = (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1). - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_ls_divider(void) -{ - uint32_t ahb_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num); - uint32_t hp_root_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, ls_div_num); - return (hp_root_ls_div + 1) * (ahb_ls_div + 1); + return HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num) + 1; } /** @@ -519,103 +448,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1; } -/** - * @brief Set MSPI_FAST_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL) - * - * @param divider Divider. - */ -static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_hs_divider(uint32_t divider) -{ - // SOC_ROOT_CLK ------> MSPI_FAST_CLK - // HS divider option: 4, 5, 6 (PCR_MSPI_FAST_HS_DIV_NUM=3, 4, 5) - uint32_t div_num = 0; - switch (divider) { - case 4: - div_num = 3; - break; - case 5: - div_num = 4; - break; - case 6: - div_num = 5; - break; - default: - // Unsupported HS MSPI_FAST divider - abort(); - } - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, div_num); -} - -/** - * @brief Set MSPI_FAST_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST) - * - * @param divider Divider. - */ -static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_ls_divider(uint32_t divider) -{ - // SOC_ROOT_CLK ------> MSPI_FAST_CLK - // LS divider option: 1, 2, 4 (PCR_MSPI_FAST_LS_DIV_NUM=0, 1, 2) - uint32_t div_num = 0; - switch (divider) { - case 1: - div_num = 0; - break; - case 2: - div_num = 1; - break; - case 4: - div_num = 2; - break; - default: - // Unsupported LS MSPI_FAST divider - abort(); - } - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, div_num); -} - -/** - * @brief Select the calibration 32kHz clock source for timergroup0 - * - * @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK) - */ -static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) -{ - switch (in_sel) { - case SOC_RTC_SLOW_CLK_SRC_RC32K: - PCR.ctrl_32k_conf.clk_32k_sel = 0; - break; - case SOC_RTC_SLOW_CLK_SRC_XTAL32K: - PCR.ctrl_32k_conf.clk_32k_sel = 1; - break; - case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: - PCR.ctrl_32k_conf.clk_32k_sel = 2; - break; - default: - // Unsupported 32K_SEL mux input - abort(); - } -} - -/** - * @brief Get the calibration 32kHz clock source for timergroup0 - * - * @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks) - */ -static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) -{ - uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel; - switch (clk_sel) { - case 0: - return SOC_RTC_SLOW_CLK_SRC_RC32K; - case 1: - return SOC_RTC_SLOW_CLK_SRC_XTAL32K; - case 2: - return SOC_RTC_SLOW_CLK_SRC_OSC_SLOW; - default: - return SOC_RTC_SLOW_CLK_SRC_INVALID; - } -} - /** * @brief Select the clock source for RTC_SLOW_CLK * @@ -678,6 +510,9 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rt case SOC_RTC_FAST_CLK_SRC_XTAL_D2: LP_CLKRST.lp_clk_conf.fast_clk_sel = 1; break; + case SOC_RTC_FAST_CLK_SRC_XTAL: + LP_CLKRST.lp_clk_conf.fast_clk_sel = 2; + break; default: // Unsupported RTC_FAST_CLK mux input sel abort(); @@ -697,6 +532,8 @@ static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_f return SOC_RTC_FAST_CLK_SRC_RC_FAST; case 1: return SOC_RTC_FAST_CLK_SRC_XTAL_D2; + case 2: + return SOC_RTC_FAST_CLK_SRC_XTAL; default: return SOC_RTC_FAST_CLK_SRC_INVALID; } @@ -716,7 +553,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uin /** * @brief Get RC_FAST_CLK divider * - * @return Divider. Divider = (CK8M_DIV_SEL + 1). + * @return Divider */ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { @@ -724,6 +561,14 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider return 1; } +/** + * @brief Set the frequency division factor of RC_FAST clock + */ +static inline void clk_ll_rc_fast_tick_conf(void) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS +} + /** * @brief Set RC_SLOW_CLK divider * @@ -736,47 +581,6 @@ static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uin } /************************** LP STORAGE REGISTER STORE/LOAD **************************/ -/** - * @brief Store XTAL_CLK frequency in RTC storage register - * - * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit - * halves. These are the routines to work with that representation. - * - * @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even, - * otherwise there will be a conflict with the low bit, which is used to disable logs - * in the ROM code. - */ -static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) -{ - // Read the status of whether disabling logging from ROM code - uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; - // If so, need to write back this setting - if (reg == RTC_DISABLE_ROM_LOG) { - xtal_freq_mhz |= 1; - } - WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16)); -} - -/** - * @brief Load XTAL_CLK frequency from RTC storage register - * - * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit - * halves. These are the routines to work with that representation. - * - * @return XTAL frequency, in MHz. Returns 0 if value in reg is invalid. - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(void) -{ - // Read from RTC storage register - uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG); - if ((xtal_freq_reg & 0xFFFF) == ((xtal_freq_reg >> 16) & 0xFFFF) && - xtal_freq_reg != 0 && xtal_freq_reg != UINT32_MAX) { - return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX; - } - // If the format in reg is invalid - return 0; -} - /** * @brief Store RTC_SLOW_CLK calibration value in RTC storage register * @@ -802,16 +606,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v return REG_READ(RTC_SLOW_CLK_CAL_REG); } - -/* -Set the frequency division factor of ref_tick -*/ -static inline void clk_ll_rc_fast_tick_conf(void) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, REG_FOSC_TICK_NUM); // divider = (REG_FOSC_TICK_NUM + 1) = 256 -} - - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c61/include/hal/pmu_ll.h b/components/hal/esp32c61/include/hal/pmu_ll.h index 85a8c0d3f9..b346121407 100644 --- a/components/hal/esp32c61/include/hal/pmu_ll.h +++ b/components/hal/esp32c61/include/hal/pmu_ll.h @@ -17,7 +17,8 @@ #include "hal/pmu_types.h" #include "hal/misc.h" -// TODO: [ESP32C61] IDF-9250, inherit from c6 +// TODO: [ESP32C61] IDF-9250 +#pragma message "pmu_ll.h has not been fully updated on ESP32C61 (IDF-9250). Use with care!" #ifdef __cplusplus extern "C" { @@ -589,6 +590,26 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t return hw->power.wait_timer1.powerdown_timer; } +FORCE_INLINE_ATTR void pmu_ll_lp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle) +{ + hw->power.wait_timer2.lp_iso_wait_timer = isolate_wait_cycle; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle) +{ + hw->power.wait_timer2.lp_rst_wait_timer = reset_wait_cycle; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle) +{ + hw->power.wait_timer2.hp_iso_wait_timer = isolate_wait_cycle; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle) +{ + hw->power.wait_timer2.hp_rst_wait_timer = reset_wait_cycle; +} + FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target, slow_clk_cycle); diff --git a/components/hal/esp32h2/include/hal/clk_tree_ll.h b/components/hal/esp32h2/include/hal/clk_tree_ll.h index f594607728..55ad67166c 100644 --- a/components/hal/esp32h2/include/hal/clk_tree_ll.h +++ b/components/hal/esp32h2/include/hal/clk_tree_ll.h @@ -43,7 +43,7 @@ Set the frequency division factor of ref_tick The FOSC of rtc calibration uses the 32 frequency division clock for ECO2, So the frequency division factor of ref_tick must be greater than or equal to 32 */ -#define CLK_LL_RC_FAST_TICK_DIV_BITS 5 +#define CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS 5 #define REG_FOSC_TICK_NUM 255 /** @@ -656,7 +656,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uin /** * @brief Get RC_FAST_CLK divider * - * @return Divider. Divider = (CK8M_DIV_SEL + 1). + * @return Divider */ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { diff --git a/components/hal/esp32p4/include/hal/clk_tree_ll.h b/components/hal/esp32p4/include/hal/clk_tree_ll.h index 1dd5efd021..c989681f77 100644 --- a/components/hal/esp32p4/include/hal/clk_tree_ll.h +++ b/components/hal/esp32p4/include/hal/clk_tree_ll.h @@ -765,7 +765,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uin /** * @brief Get RC_FAST_CLK divider * - * @return Divider. Divider = (CK8M_DIV_SEL + 1). + * @return Divider */ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) { diff --git a/components/soc/esp32c5/gpio_periph.c b/components/soc/esp32c5/gpio_periph.c index 1d1d496972..37c07f1cbc 100644 --- a/components/soc/esp32c5/gpio_periph.c +++ b/components/soc/esp32c5/gpio_periph.c @@ -6,8 +6,6 @@ #include "soc/gpio_periph.h" -_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); - const uint32_t GPIO_HOLD_MASK[] = { BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG BIT(1), //GPIO1 diff --git a/components/soc/esp32c61/gpio_periph.c b/components/soc/esp32c61/gpio_periph.c index e876a88b34..45ca3280d3 100644 --- a/components/soc/esp32c61/gpio_periph.c +++ b/components/soc/esp32c61/gpio_periph.c @@ -6,8 +6,6 @@ #include "soc/gpio_periph.h" -_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); - const uint32_t GPIO_HOLD_MASK[] = { BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG BIT(1), //GPIO1 diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 44fba65f96..bca2cc95ad 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -47,6 +47,14 @@ config SOC_FLASH_ENC_SUPPORTED bool default y +config SOC_PMU_SUPPORTED + bool + default y + +config SOC_CLK_TREE_SUPPORTED + bool + default y + config SOC_SPI_FLASH_SUPPORTED bool default y @@ -603,6 +611,10 @@ config SOC_PM_PAU_LINK_NUM int default 4 +config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION + bool + default y + config SOC_MODEM_CLOCK_IS_INDEPENDENT bool default y @@ -619,6 +631,10 @@ config SOC_CLK_RC32K_SUPPORTED bool default y +config SOC_CLK_LP_FAST_SUPPORT_XTAL + bool + default y + config SOC_RCC_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32c61/include/soc/clk_tree_defs.h b/components/soc/esp32c61/include/soc/clk_tree_defs.h index c3cc167dc9..4c1f135c94 100644 --- a/components/soc/esp32c61/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c61/include/soc/clk_tree_defs.h @@ -5,7 +5,6 @@ */ #pragma once -// TODO: [ESP32C61] IDF-9249, This file comes from verification code #ifdef __cplusplus extern "C" { #endif @@ -73,8 +72,8 @@ typedef enum { */ typedef enum { SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ - SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL_F160M = 2, /*!< Select PLL_F160M_CLK as CPU_CLK source (PLL_F160M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */ SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ } soc_cpu_clk_src_t; @@ -98,6 +97,7 @@ typedef enum { SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_XTAL = 2, /*!< Select XTAL_CLK as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ } soc_rtc_fast_clk_src_t; @@ -128,12 +128,10 @@ typedef enum { // For digital domain: peripherals, WIFI, BLE SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ - SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ + SOC_MOD_CLK_SPLL, /*!< SPLL is from the main XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */ SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ - // For LP peripherals - SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */ SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ } soc_module_clk_t; @@ -217,20 +215,6 @@ typedef enum { UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */ } soc_periph_uart_clk_src_legacy_t; -/** - * @brief Array initializer for all supported clock sources of LP_UART - */ -#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2} - -/** - * @brief Type of LP_UART clock source - */ -typedef enum { - LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */ - LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */ - LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */ -} soc_periph_lp_uart_clk_src_t; - ///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// /** @@ -264,22 +248,6 @@ typedef enum { I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */ } soc_periph_i2c_clk_src_t; -///////////////////////////////////////////////LP_I2C/////////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of LP_I2C - */ -#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2} - -/** - * @brief Type of LP_I2C clock source. - */ -typedef enum { - LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock is RTC_FAST */ - LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */ - LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */ -} soc_periph_lp_i2c_clk_src_t; - /////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32c61/include/soc/io_mux_reg.h b/components/soc/esp32c61/include/soc/io_mux_reg.h index e205853b2a..ea9dcaf0fc 100644 --- a/components/soc/esp32c61/include/soc/io_mux_reg.h +++ b/components/soc/esp32c61/include/soc/io_mux_reg.h @@ -124,9 +124,6 @@ extern "C" { #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) -#define U0RXD_GPIO_NUM 10 -#define U0TXD_GPIO_NUM 11 - #define SPI_HD_GPIO_NUM 19 #define SPI_WP_GPIO_NUM 17 #define SPI_CS0_GPIO_NUM 15 @@ -137,6 +134,8 @@ extern "C" { #define USB_INT_PHY0_DM_GPIO_NUM 12 #define USB_INT_PHY0_DP_GPIO_NUM 13 +#define EXT_OSC_SLOW_GPIO_NUM 0 + #define MAX_RTC_GPIO_NUM 7 #define MAX_PAD_GPIO_NUM 21 #define MAX_GPIO_NUM 28 diff --git a/components/soc/esp32c61/include/soc/pcr_reg.h b/components/soc/esp32c61/include/soc/pcr_reg.h index f7539adeba..feedd3ae52 100644 --- a/components/soc/esp32c61/include/soc/pcr_reg.h +++ b/components/soc/esp32c61/include/soc/pcr_reg.h @@ -314,7 +314,7 @@ extern "C" { #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x28) /** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed - * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a * low-speed clock-source such as XTAL/FOSC. */ #define PCR_MSPI_FAST_DIV_NUM 0x000000FFU @@ -1076,7 +1076,7 @@ extern "C" { #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of PVT MONITER.\\ + * Configures the clock source of PVT MONITOR.\\ * 0 (default): XTAL_CLK\\ * 1: PLL_F160M_CLK\\ */ @@ -1619,21 +1619,6 @@ extern "C" { * SYSCLK configuration register */ #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0xe8) -/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; - * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed - * clock-source such as XTAL/FOSC. - */ -#define PCR_LS_DIV_NUM 0x000000FFU -#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) -#define PCR_LS_DIV_NUM_V 0x000000FFU -#define PCR_LS_DIV_NUM_S 0 -/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; - * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. - */ -#define PCR_HS_DIV_NUM 0x000000FFU -#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) -#define PCR_HS_DIV_NUM_V 0x000000FFU -#define PCR_HS_DIV_NUM_S 8 /** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; * Configures to select the clock source of HP_ROOT_CLK.\\ * 0 (default): XTAL_CLK\\ @@ -1699,8 +1684,8 @@ extern "C" { */ #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf0) /** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is - * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. */ #define PCR_CPU_DIV_NUM 0x000000FFU @@ -1713,8 +1698,8 @@ extern "C" { */ #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf4) /** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is - * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_DIV_NUM. */ @@ -1741,7 +1726,7 @@ extern "C" { #define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU #define PCR_APB_DECREASE_DIV_NUM_S 0 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ #define PCR_APB_DIV_NUM 0x000000FFU @@ -1773,64 +1758,64 @@ extern "C" { */ #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x100) /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 160 MHz clock (div3 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_160M_CLK_EN (BIT(1)) #define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) #define PCR_PLL_160M_CLK_EN_V 0x00000001U #define PCR_PLL_160M_CLK_EN_S 1 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 120 MHz clock (div4 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_120M_CLK_EN (BIT(2)) #define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) #define PCR_PLL_120M_CLK_EN_V 0x00000001U #define PCR_PLL_120M_CLK_EN_S 2 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 80 MHz clock (div6 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_80M_CLK_EN (BIT(3)) #define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) #define PCR_PLL_80M_CLK_EN_V 0x00000001U #define PCR_PLL_80M_CLK_EN_S 3 /** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1; - * This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 60 MHz clock (div8 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_60M_CLK_EN (BIT(4)) #define PCR_PLL_60M_CLK_EN_M (PCR_PLL_60M_CLK_EN_V << PCR_PLL_60M_CLK_EN_S) #define PCR_PLL_60M_CLK_EN_V 0x00000001U #define PCR_PLL_60M_CLK_EN_S 4 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 48 MHz clock (div10 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_48M_CLK_EN (BIT(5)) #define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) #define PCR_PLL_48M_CLK_EN_V 0x00000001U #define PCR_PLL_48M_CLK_EN_S 5 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 40 MHz clock (div12 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_40M_CLK_EN (BIT(6)) #define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) #define PCR_PLL_40M_CLK_EN_V 0x00000001U #define PCR_PLL_40M_CLK_EN_S 6 /** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 20 MHz clock (div24 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_20M_CLK_EN (BIT(7)) #define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) #define PCR_PLL_20M_CLK_EN_V 0x00000001U #define PCR_PLL_20M_CLK_EN_S 7 /** PCR_PLL_12M_CLK_EN : HRO; bitpos: [8]; default: 1; - * This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 12 MHz clock (div40 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_12M_CLK_EN (BIT(8)) #define PCR_PLL_12M_CLK_EN_M (PCR_PLL_12M_CLK_EN_V << PCR_PLL_12M_CLK_EN_S) diff --git a/components/soc/esp32c61/include/soc/pcr_struct.h b/components/soc/esp32c61/include/soc/pcr_struct.h index 87776e7631..0591f845ef 100644 --- a/components/soc/esp32c61/include/soc/pcr_struct.h +++ b/components/soc/esp32c61/include/soc/pcr_struct.h @@ -266,7 +266,7 @@ typedef union { struct { /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0; * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed - * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * clock-source to drive clk_mspi_fast. Only available when the clck-source is a * low-speed clock-source such as XTAL/FOSC. */ uint32_t mspi_fast_div_num:8; @@ -916,7 +916,7 @@ typedef union { uint32_t pvt_monitor_func_clk_div_num:4; uint32_t reserved_4:16; /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of PVT MONITER.\\ + * Configures the clock source of PVT MONITOR.\\ * 0 (default): XTAL_CLK\\ * 1: PLL_F160M_CLK\\ */ @@ -1399,15 +1399,7 @@ typedef union { */ typedef union { struct { - /** ls_div_num : HRO; bitpos: [7:0]; default: 0; - * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed - * clock-source such as XTAL/FOSC. - */ - uint32_t ls_div_num:8; - /** hs_div_num : HRO; bitpos: [15:8]; default: 2; - * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. - */ - uint32_t hs_div_num:8; + uint32_t reserved_0:16; /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; * Configures to select the clock source of HP_ROOT_CLK.\\ * 0 (default): XTAL_CLK\\ @@ -1462,8 +1454,8 @@ typedef union { typedef union { struct { /** cpu_div_num : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is - * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. */ uint32_t cpu_div_num:8; @@ -1478,8 +1470,8 @@ typedef union { typedef union { struct { /** ahb_div_num : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is - * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_DIV_NUM. */ @@ -1505,7 +1497,7 @@ typedef union { */ uint32_t apb_decrease_div_num:8; /** apb_div_num : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ uint32_t apb_div_num:8; @@ -1521,43 +1513,43 @@ typedef union { struct { uint32_t reserved_0:1; /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 160 MHz clock (div3 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_160m_clk_en:1; /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 120 MHz clock (div4 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_120m_clk_en:1; /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 80 MHz clock (div6 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_80m_clk_en:1; /** pll_60m_clk_en : R/W; bitpos: [4]; default: 1; - * This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 60 MHz clock (div8 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_60m_clk_en:1; /** pll_48m_clk_en : R/W; bitpos: [5]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 48 MHz clock (div10 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_48m_clk_en:1; /** pll_40m_clk_en : R/W; bitpos: [6]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 40 MHz clock (div12 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_40m_clk_en:1; /** pll_20m_clk_en : R/W; bitpos: [7]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 20 MHz clock (div24 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_20m_clk_en:1; /** pll_12m_clk_en : HRO; bitpos: [8]; default: 1; - * This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close, - * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + * This field is used to open 12 MHz clock (div40 of SPLL) derived from SPLL. 0: close, + * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_12m_clk_en:1; uint32_t reserved_9:23; diff --git a/components/soc/esp32c61/include/soc/reg_base.h b/components/soc/esp32c61/include/soc/reg_base.h index 226a2517f9..097e03db2f 100644 --- a/components/soc/esp32c61/include/soc/reg_base.h +++ b/components/soc/esp32c61/include/soc/reg_base.h @@ -30,6 +30,7 @@ #define DR_REG_ECDSA_BASE 0x6008E000 #define DR_REG_IO_MUX_BASE 0x60090000 #define DR_REG_GPIO_BASE 0x60091000 +#define DR_REG_GPIO_EXT_BASE 0x60091E00 #define DR_REG_TCM_MEM_MONITOR_BASE 0x60092000 #define DR_REG_PAU_BASE 0x60093000 #define DR_REG_HP_SYSTEM_BASE 0x60095000 diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h index 0ae5500a91..c2317dec73 100644 --- a/components/soc/esp32c61/include/soc/soc.h +++ b/components/soc/esp32c61/include/soc/soc.h @@ -134,13 +134,10 @@ //}} //Periheral Clock {{ -#define APB_CLK_FREQ_ROM ( 40*1000000 ) -#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM #define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration #define APB_CLK_FREQ ( 40*1000000 ) #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) #define REF_CLK_FREQ ( 1000000 ) -#define XTAL_CLK_FREQ (40*1000000) #define GPIO_MATRIX_DELAY_NS 0 //}} diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 99fbb8f7b2..541ee325f3 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -51,11 +51,11 @@ // \#define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: [ESP32C61] IDF-9233 // \#define SOC_BOD_SUPPORTED 1 //TODO: [ESP32C61] IDF-9254 // \#define SOC_APM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9230 -// \#define SOC_PMU_SUPPORTED 1 //TODO: [ESP32C61] IDf-9250 +#define SOC_PMU_SUPPORTED 1 //TODO: [ESP32C61] IDF-9250 // \#define SOC_LP_TIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9244 // \#define SOC_LP_AON_SUPPORTED 1 // \#define SOC_LP_PERIPHERALS_SUPPORTED 1 -// \#define SOC_CLK_TREE_SUPPORTED 1 //TODO: [ESP32C61] IDF-9249 + #define SOC_CLK_TREE_SUPPORTED 1 // \#define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9270 // \#define SOC_WDT_SUPPORTED 1 //TODO: [ESP32C61] IDF-9257 #define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32C61] IDF-9314 @@ -480,12 +480,13 @@ #define SOC_PM_PAU_LINK_NUM (4) /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/ -// #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) //TODO: [ESP32C61] IDF-9249 +#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) #define SOC_MODEM_CLOCK_IS_INDEPENDENT (1) #define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */ #define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */ #define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */ +#define SOC_CLK_LP_FAST_SUPPORT_XTAL (1) /*!< Support XTAL clock as the LP_FAST clock source */ #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */ diff --git a/components/soc/esp32c61/include/soc/timer_group_reg.h b/components/soc/esp32c61/include/soc/timer_group_reg.h index 1710786842..3f96f9300c 100644 --- a/components/soc/esp32c61/include/soc/timer_group_reg.h +++ b/components/soc/esp32c61/include/soc/timer_group_reg.h @@ -420,13 +420,6 @@ extern "C" { #define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) #define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U #define TIMG_RTC_CALI_START_CYCLING_S 12 -/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0; - * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. - */ -#define TIMG_RTC_CALI_CLK_SEL 0x00000003U -#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) -#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U -#define TIMG_RTC_CALI_CLK_SEL_S 13 /** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; * Represents whether one-shot frequency calculation is done. * 0: Not done diff --git a/components/soc/esp32c61/include/soc/timer_group_struct.h b/components/soc/esp32c61/include/soc/timer_group_struct.h index 9f6fde66f8..f994c52fde 100644 --- a/components/soc/esp32c61/include/soc/timer_group_struct.h +++ b/components/soc/esp32c61/include/soc/timer_group_struct.h @@ -401,10 +401,7 @@ typedef union { * 1: periodic frequency calculation */ uint32_t rtc_cali_start_cycling:1; - /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; - * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. - */ - uint32_t rtc_cali_clk_sel:2; + uint32_t reserved_13: 2; /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; * Represents whether one-shot frequency calculation is done. * 0: Not done diff --git a/docs/docs_not_updated/esp32c61.txt b/docs/docs_not_updated/esp32c61.txt index d880659dc0..5a8b63cbde 100644 --- a/docs/docs_not_updated/esp32c61.txt +++ b/docs/docs_not_updated/esp32c61.txt @@ -103,7 +103,6 @@ api-reference/peripherals/ledc.rst api-reference/peripherals/temp_sensor.rst api-reference/peripherals/spi_features.rst api-reference/peripherals/sdio_slave.rst -api-reference/peripherals/clk_tree.rst api-reference/peripherals/spi_flash/spi_flash_concurrency.rst api-reference/peripherals/spi_flash/spi_flash_override_driver.rst api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst