mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
ethernet: support OpenCores ethernet MAC
OpenCores Ethernet MAC has a relatively simple interface, and is already supported in QEMU. This makes it a good candidate for enabling network support when running IDF apps in QEMU, compared to the relatively more complex task of writing a QEMU model of ESP32 EMAC. This driver is written with QEMU in mind: it does not implement or handle things that aren't implemented or handled in the QEMU model: error flags, error interrupts. The transmit part of the driver also assumes that the TX operation is done immediately when the TX descriptor is written (which is the case with QEMU), hence waiting for the TX operation to complete is not necessary. For simplicity, the driver assumes that the peripheral register occupy the same memory range as the ESP32 EMAC registers, and the same interrupt source number is used.
This commit is contained in:
Ivan Grokhotkov
parent
420ee45279
commit
31dac92e5f
@ -13,6 +13,10 @@ if(CONFIG_ETH_SPI_ETHERNET_DM9051)
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"src/esp_eth_phy_dm9051.c")
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endif()
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if(CONFIG_ETH_USE_OPENETH)
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list(APPEND esp_eth_srcs "src/esp_eth_mac_openeth.c")
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endif()
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idf_component_register(SRCS "${esp_eth_srcs}"
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INCLUDE_DIRS "include"
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LDFRAGMENTS "linker.lf"
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@ -153,4 +153,28 @@ menu "Ethernet"
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Set the GPIO number used by DM9051's Interrupt pin.
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endif
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endif
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menuconfig ETH_USE_OPENETH
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bool "Support OpenCores Ethernet MAC (for use with QEMU)"
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default n
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help
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OpenCores Ethernet MAC driver can be used when an ESP-IDF application
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is executed in QEMU. This driver is not supported when running on a
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real chip.
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if ETH_USE_OPENETH
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config ETH_OPENETH_DMA_RX_BUFFER_NUM
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int "Number of Ethernet DMA Rx buffers"
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range 1 64
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default 4
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help
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Number of DMA receive buffers, each buffer is 1600 bytes.
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config ETH_OPENETH_DMA_TX_BUFFER_NUM
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int "Number of Ethernet DMA Tx buffers"
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range 1 64
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default 1
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help
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Number of DMA transmit buffers, each buffer is 1600 bytes.
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endif
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endmenu
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@ -12,3 +12,7 @@ endif
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ifndef CONFIG_ETH_SPI_ETHERNET_DM9051
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COMPONENT_OBJEXCLUDE += src/esp_eth_mac_dm9051.o src/esp_eth_phy_dm9051.o
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endif
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ifndef CONFIG_ETH_USE_OPENETH
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COMPONENT_OBJEXCLUDE += src/esp_eth_mac_openeth.o
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endif
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@ -307,6 +307,12 @@ typedef struct {
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*/
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esp_eth_mac_t *esp_eth_mac_new_dm9051(const eth_dm9051_config_t *dm9051_config, const eth_mac_config_t *mac_config);
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#endif
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#if CONFIG_ETH_USE_OPENETH
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esp_eth_mac_t *esp_eth_mac_new_openeth(const eth_mac_config_t *config);
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#endif // CONFIG_ETH_USE_OPENETH
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#ifdef __cplusplus
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}
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#endif
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410
components/esp_eth/src/esp_eth_mac_openeth.c
Normal file
410
components/esp_eth/src/esp_eth_mac_openeth.c
Normal file
@ -0,0 +1,410 @@
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// This is a driver for OpenCores Ethernet MAC (https://opencores.org/projects/ethmac).
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// Espressif chips do not use this MAC, but it is supported in QEMU
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// (see hw/net/opencores_eth.c). Since the interface of this MAC is a relatively
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// simple one, it is used for the purpose of running IDF apps in QEMU.
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// The QEMU driver also emulates the DP83848C PHY, which is supported in IDF.
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// Note that this driver is written with QEMU in mind. For example, it doesn't
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// handle errors which QEMU will not report, and doesn't wait for TX to be
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// finished, since QEMU does this instantly.
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#include <string.h>
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#include <stdlib.h>
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include "esp_log.h"
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#include "esp_eth.h"
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#include "esp_intr_alloc.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "openeth.h"
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static const char *TAG = "emac_opencores";
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#define MAC_CHECK(a, str, goto_tag, ret_value, ...) \
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do \
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{ \
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if (!(a)) \
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{ \
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ESP_LOGE(TAG, "%s(%d): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
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ret = ret_value; \
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goto goto_tag; \
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} \
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} while (0)
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// Driver state structure
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typedef struct {
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esp_eth_mac_t parent;
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esp_eth_mediator_t *eth;
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intr_handle_t intr_hdl;
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TaskHandle_t rx_task_hdl;
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int cur_rx_desc;
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int cur_tx_desc;
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uint8_t addr[6];
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uint8_t *rx_buf[RX_BUF_COUNT];
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uint8_t *tx_buf[TX_BUF_COUNT];
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} emac_opencores_t;
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// Interrupt handler and the receive task
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static esp_err_t emac_opencores_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32_t *length);
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static IRAM_ATTR void emac_opencores_isr_handler(void *args)
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{
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emac_opencores_t *emac = (emac_opencores_t*) args;
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BaseType_t high_task_wakeup;
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uint32_t status = REG_READ(OPENETH_INT_SOURCE_REG);
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if (status & OPENETH_INT_RXB) {
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// Notify receive task
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vTaskNotifyGiveFromISR(emac->rx_task_hdl, &high_task_wakeup);
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if (high_task_wakeup) {
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portYIELD_FROM_ISR();
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}
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}
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if (status & OPENETH_INT_BUSY) {
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ESP_EARLY_LOGW(TAG, "%s: RX frame dropped (0x%x)", __func__, status);
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}
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// Clear interrupt
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REG_WRITE(OPENETH_INT_SOURCE_REG, status);
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}
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static void emac_opencores_rx_task(void *arg)
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{
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emac_opencores_t *emac = (emac_opencores_t *)arg;
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uint8_t *buffer = NULL;
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uint32_t length = 0;
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while (1) {
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if (ulTaskNotifyTake(pdFALSE, portMAX_DELAY)) {
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while(true) {
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buffer = (uint8_t *)malloc(ETH_MAX_PACKET_SIZE);
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length = ETH_MAX_PACKET_SIZE;
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if (emac_opencores_receive(&emac->parent, buffer, &length) == ESP_OK) {
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// pass the buffer to the upper layer
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if (length) {
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emac->eth->stack_input(emac->eth, buffer, length);
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} else {
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free(buffer);
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}
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} else {
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free(buffer);
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break;
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}
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}
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}
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}
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vTaskDelete(NULL);
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}
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// Below functions implement the driver interface
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static esp_err_t emac_opencores_set_mediator(esp_eth_mac_t *mac, esp_eth_mediator_t *eth)
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{
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esp_err_t ret = ESP_OK;
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MAC_CHECK(eth, "can't set mac's mediator to null", err, ESP_ERR_INVALID_ARG);
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emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent);
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emac->eth = eth;
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_opencores_write_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr, uint32_t phy_reg, uint32_t reg_value)
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{
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ESP_LOGV(TAG, "%s: addr=%d reg=0x%x val=0x%04x", __func__, phy_addr, phy_reg, reg_value);
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REG_SET_FIELD(OPENETH_MIIADDRESS_REG, OPENETH_FIAD, phy_addr);
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REG_SET_FIELD(OPENETH_MIIADDRESS_REG, OPENETH_RGAD, phy_reg);
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REG_WRITE(OPENETH_MIITX_DATA_REG, reg_value & OPENETH_MII_DATA_MASK);
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REG_SET_BIT(OPENETH_MIICOMMAND_REG, OPENETH_WCTRLDATA);
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return ESP_OK;
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}
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static esp_err_t emac_opencores_read_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr, uint32_t phy_reg, uint32_t *reg_value)
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{
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esp_err_t ret = ESP_OK;
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MAC_CHECK(reg_value, "can't set reg_value to null", err, ESP_ERR_INVALID_ARG);
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REG_SET_FIELD(OPENETH_MIIADDRESS_REG, OPENETH_FIAD, phy_addr);
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REG_SET_FIELD(OPENETH_MIIADDRESS_REG, OPENETH_RGAD, phy_reg);
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REG_SET_BIT(OPENETH_MIICOMMAND_REG, OPENETH_RSTAT);
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*reg_value = (REG_READ(OPENETH_MIIRX_DATA_REG) & OPENETH_MII_DATA_MASK);
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ESP_LOGV(TAG, "%s: addr=%d reg=0x%x val=0x%04x", __func__, phy_addr, phy_reg, *reg_value);
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_opencores_set_addr(esp_eth_mac_t *mac, uint8_t *addr)
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{
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ESP_LOGV(TAG, "%s: " MACSTR, __func__, MAC2STR(addr));
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esp_err_t ret = ESP_OK;
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MAC_CHECK(addr, "can't set mac addr to null", err, ESP_ERR_INVALID_ARG);
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emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent);
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memcpy(emac->addr, addr, 6);
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const uint8_t mac0[4] = {addr[5], addr[4], addr[3], addr[2]};
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const uint8_t mac1[4] = {addr[1], addr[0]};
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uint32_t mac0_u32, mac1_u32;
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memcpy(&mac0_u32, &mac0, 4);
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memcpy(&mac1_u32, &mac1, 4);
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REG_WRITE(OPENETH_MAC_ADDR0_REG, mac0_u32);
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REG_WRITE(OPENETH_MAC_ADDR1_REG, mac1_u32);
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_opencores_get_addr(esp_eth_mac_t *mac, uint8_t *addr)
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{
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ESP_LOGV(TAG, "%s: " MACSTR, __func__, MAC2STR(addr));
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esp_err_t ret = ESP_OK;
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MAC_CHECK(addr, "can't set mac addr to null", err, ESP_ERR_INVALID_ARG);
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emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent);
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memcpy(addr, emac->addr, 6);
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_opencores_set_link(esp_eth_mac_t *mac, eth_link_t link)
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{
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ESP_LOGV(TAG, "%s: %s", __func__, link == ETH_LINK_UP ? "up" : "down");
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esp_err_t ret = ESP_OK;
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emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent);
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switch (link) {
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case ETH_LINK_UP:
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MAC_CHECK(esp_intr_enable(emac->intr_hdl) == ESP_OK, "enable interrupt failed", err, ESP_FAIL);
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openeth_enable();
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break;
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case ETH_LINK_DOWN:
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MAC_CHECK(esp_intr_disable(emac->intr_hdl) == ESP_OK, "disable interrupt failed", err, ESP_FAIL);
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openeth_disable();
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break;
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default:
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MAC_CHECK(false, "unknown link status", err, ESP_ERR_INVALID_ARG);
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break;
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}
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_opencores_set_speed(esp_eth_mac_t *mac, eth_speed_t speed)
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{
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/* QEMU doesn't emulate PHY speed, so accept any value */
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return ESP_OK;
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}
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static esp_err_t emac_opencores_set_duplex(esp_eth_mac_t *mac, eth_duplex_t duplex)
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{
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/* QEMU doesn't emulate full/half duplex, so accept any value */
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return ESP_OK;
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}
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static esp_err_t emac_opencores_set_promiscuous(esp_eth_mac_t *mac, bool enable)
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{
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if (enable) {
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REG_SET_BIT(OPENETH_MODER_REG, OPENETH_PRO);
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} else {
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REG_CLR_BIT(OPENETH_MODER_REG, OPENETH_PRO);
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}
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return ESP_OK;
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}
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static esp_err_t emac_opencores_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint32_t length)
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{
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esp_err_t ret = ESP_OK;
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emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent);
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MAC_CHECK(buf, "can't set buf to null", err, ESP_ERR_INVALID_ARG);
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MAC_CHECK(length, "buf length can't be zero", err, ESP_ERR_INVALID_ARG);
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MAC_CHECK(length < DMA_BUF_SIZE * TX_BUF_COUNT, "insufficient TX buffer size", err, ESP_ERR_INVALID_SIZE);
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uint32_t bytes_remaining = length;
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// In QEMU, there never is a TX operation in progress, so start with descriptor 0.
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ESP_LOGV(TAG, "%s: len=%d", __func__, length);
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while (bytes_remaining > 0) {
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uint32_t will_write = MIN(bytes_remaining, DMA_BUF_SIZE);
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memcpy(emac->tx_buf[emac->cur_tx_desc], buf, will_write);
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openeth_tx_desc_t* desc_ptr = openeth_tx_desc(emac->cur_tx_desc);
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openeth_tx_desc_t desc_val = *desc_ptr;
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desc_val.wr = (emac->cur_tx_desc == TX_BUF_COUNT - 1);
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desc_val.len = will_write;
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desc_val.rd = 1;
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// TXEN is already set, and this triggers a TX operation for the descriptor
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ESP_LOGV(TAG, "%s: desc %d (%p) len=%d wr=%d", __func__, emac->cur_tx_desc, desc_ptr, will_write, desc_val.wr);
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*desc_ptr = desc_val;
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bytes_remaining -= will_write;
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buf += will_write;
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emac->cur_tx_desc = (emac->cur_tx_desc + 1) % TX_BUF_COUNT;
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}
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_opencores_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32_t *length)
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{
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esp_err_t ret = ESP_OK;
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emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent);
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MAC_CHECK(buf && length, "can't set buf and length to null", err, ESP_ERR_INVALID_ARG);
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openeth_rx_desc_t *desc_ptr = openeth_rx_desc(emac->cur_rx_desc);
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openeth_rx_desc_t desc_val = *desc_ptr;
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ESP_LOGV(TAG, "%s: desc %d (%p) e=%d len=%d wr=%d", __func__, emac->cur_rx_desc, desc_ptr, desc_val.e, desc_val.len, desc_val.wr);
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if (desc_val.e) {
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ret = ESP_ERR_INVALID_STATE;
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goto err;
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}
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size_t rx_length = desc_val.len;
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MAC_CHECK(*length >= rx_length, "RX length too large", err, ESP_ERR_INVALID_SIZE);
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*length = rx_length;
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memcpy(buf, desc_val.rxpnt, *length);
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desc_val.e = 1;
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*desc_ptr = desc_val;
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emac->cur_rx_desc = (emac->cur_rx_desc + 1) % RX_BUF_COUNT;
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_opencores_init(esp_eth_mac_t *mac)
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{
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esp_err_t ret = ESP_OK;
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emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent);
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esp_eth_mediator_t *eth = emac->eth;
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MAC_CHECK(eth->on_state_changed(eth, ETH_STATE_LLINIT, NULL) == ESP_OK, "lowlevel init failed", err, ESP_FAIL);
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MAC_CHECK(esp_read_mac(emac->addr, ESP_MAC_ETH) == ESP_OK, "fetch ethernet mac address failed", err, ESP_FAIL);
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// Sanity check
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if (REG_READ(OPENETH_MODER_REG) != OPENETH_MODER_DEFAULT) {
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ESP_LOGE(TAG, "CONFIG_ETH_USE_OPENETH should only be used when running in QEMU.");
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ESP_LOGE(TAG, "When running the app on the ESP32, use CONFIG_ETH_USE_ESP32_EMAC instead.");
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abort();
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}
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// Initialize the MAC
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openeth_reset();
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openeth_set_tx_desc_cnt(TX_BUF_COUNT);
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emac_opencores_set_addr(mac, emac->addr);
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return ESP_OK;
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err:
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eth->on_state_changed(eth, ETH_STATE_DEINIT, NULL);
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return ret;
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}
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static esp_err_t emac_opencores_deinit(esp_eth_mac_t *mac)
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{
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emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent);
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esp_eth_mediator_t *eth = emac->eth;
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eth->on_state_changed(eth, ETH_STATE_DEINIT, NULL);
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return ESP_OK;
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}
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static esp_err_t emac_opencores_del(esp_eth_mac_t *mac)
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{
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emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent);
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esp_intr_free(emac->intr_hdl);
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vTaskDelete(emac->rx_task_hdl);
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for (int i = 0; i < RX_BUF_COUNT; i++) {
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free(emac->rx_buf[i]);
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}
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for (int i = 0; i < TX_BUF_COUNT; i++) {
|
||||
free(emac->tx_buf[i]);
|
||||
}
|
||||
free(emac);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_eth_mac_t *esp_eth_mac_new_openeth(const eth_mac_config_t *config)
|
||||
{
|
||||
esp_eth_mac_t *ret = NULL;
|
||||
emac_opencores_t *emac = NULL;
|
||||
MAC_CHECK(config, "can't set mac config to null", out, NULL);
|
||||
emac = calloc(1, sizeof(emac_opencores_t));
|
||||
MAC_CHECK(emac, "calloc emac failed", out, NULL);
|
||||
|
||||
// Allocate DMA buffers
|
||||
for (int i = 0; i < RX_BUF_COUNT; i++) {
|
||||
emac->rx_buf[i] = heap_caps_calloc(1, DMA_BUF_SIZE, MALLOC_CAP_DMA);
|
||||
if (!(emac->rx_buf[i])) {
|
||||
goto out;
|
||||
}
|
||||
openeth_init_rx_desc(openeth_rx_desc(i), emac->rx_buf[i]);
|
||||
}
|
||||
openeth_rx_desc(RX_BUF_COUNT - 1)->wr = 1;
|
||||
emac->cur_rx_desc = 0;
|
||||
|
||||
for (int i = 0; i < TX_BUF_COUNT; i++) {
|
||||
emac->tx_buf[i] = heap_caps_calloc(1, DMA_BUF_SIZE, MALLOC_CAP_DMA);
|
||||
if (!(emac->tx_buf[i])) {
|
||||
goto out;
|
||||
}
|
||||
openeth_init_tx_desc(openeth_tx_desc(i), emac->tx_buf[i]);
|
||||
}
|
||||
openeth_tx_desc(TX_BUF_COUNT - 1)->wr = 1;
|
||||
emac->cur_tx_desc = 0;
|
||||
|
||||
emac->parent.set_mediator = emac_opencores_set_mediator;
|
||||
emac->parent.init = emac_opencores_init;
|
||||
emac->parent.deinit = emac_opencores_deinit;
|
||||
emac->parent.del = emac_opencores_del;
|
||||
emac->parent.write_phy_reg = emac_opencores_write_phy_reg;
|
||||
emac->parent.read_phy_reg = emac_opencores_read_phy_reg;
|
||||
emac->parent.set_addr = emac_opencores_set_addr;
|
||||
emac->parent.get_addr = emac_opencores_get_addr;
|
||||
emac->parent.set_speed = emac_opencores_set_speed;
|
||||
emac->parent.set_duplex = emac_opencores_set_duplex;
|
||||
emac->parent.set_link = emac_opencores_set_link;
|
||||
emac->parent.set_promiscuous = emac_opencores_set_promiscuous;
|
||||
emac->parent.transmit = emac_opencores_transmit;
|
||||
emac->parent.receive = emac_opencores_receive;
|
||||
|
||||
// Initialize the interrupt
|
||||
MAC_CHECK(esp_intr_alloc(OPENETH_INTR_SOURCE, ESP_INTR_FLAG_IRAM, emac_opencores_isr_handler,
|
||||
emac, &(emac->intr_hdl)) == ESP_OK,
|
||||
"alloc emac interrupt failed", out, NULL);
|
||||
|
||||
// Create the RX task
|
||||
BaseType_t xReturned = xTaskCreate(emac_opencores_rx_task, "emac_rx", config->rx_task_stack_size, emac,
|
||||
config->rx_task_prio, &emac->rx_task_hdl);
|
||||
MAC_CHECK(xReturned == pdPASS, "create emac_rx task failed", out, NULL);
|
||||
return &(emac->parent);
|
||||
|
||||
out:
|
||||
if (emac) {
|
||||
if (emac->rx_task_hdl) {
|
||||
vTaskDelete(emac->rx_task_hdl);
|
||||
}
|
||||
if (emac->intr_hdl) {
|
||||
esp_intr_free(emac->intr_hdl);
|
||||
}
|
||||
for (int i = 0; i < TX_BUF_COUNT; i++) {
|
||||
free(emac->tx_buf[i]);
|
||||
}
|
||||
for (int i = 0; i < RX_BUF_COUNT; i++) {
|
||||
free(emac->rx_buf[i]);
|
||||
}
|
||||
free(emac);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
216
components/esp_eth/src/openeth.h
Normal file
216
components/esp_eth/src/openeth.h
Normal file
@ -0,0 +1,216 @@
|
||||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <assert.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// These are the register definitions for the OpenCores Ethernet MAC.
|
||||
// See comments in esp_eth_mac_openeth.c for more details about this driver.
|
||||
|
||||
// DMA buffers configuration
|
||||
#define DMA_BUF_SIZE 1600
|
||||
#define RX_BUF_COUNT CONFIG_ETH_OPENETH_DMA_RX_BUFFER_NUM
|
||||
#define TX_BUF_COUNT CONFIG_ETH_OPENETH_DMA_TX_BUFFER_NUM
|
||||
|
||||
// This driver uses the interrupt source number of the internal EMAC of the ESP32 chip,
|
||||
// and uses the same register address base. This of course only works in QEMU, where
|
||||
// the OpenCores MAC is mapped to the same register base and to the same interrupt
|
||||
// source. This driver does a sanity check that it is not running on the real ESP32
|
||||
// chip, using the EMAC date register.
|
||||
#define OPENETH_INTR_SOURCE ETS_ETH_MAC_INTR_SOURCE
|
||||
#define OPENETH_BASE DR_REG_EMAC_BASE
|
||||
|
||||
// OpenCores ethmac registers
|
||||
#define OPENETH_MODER_REG (OPENETH_BASE + 0x00)
|
||||
#define OPENETH_MODER_DEFAULT 0xa000
|
||||
// OPENETH_RST: reset the MAC
|
||||
#define OPENETH_RST BIT(11)
|
||||
// OPENETH_PRO: enable promiscuous mode
|
||||
#define OPENETH_PRO BIT(5)
|
||||
// OPENETH_TXEN: enable transmit
|
||||
#define OPENETH_TXEN BIT(1)
|
||||
// OPENETH_RXEN: enable receive
|
||||
#define OPENETH_RXEN BIT(0)
|
||||
|
||||
#define OPENETH_INT_SOURCE_REG (OPENETH_BASE + 0x04)
|
||||
#define OPENETH_INT_MASK_REG (OPENETH_BASE + 0x08)
|
||||
// These bits apply to INT_SOURCE and INT_MASK registers:
|
||||
// OPENETH_INT_BUSY: Buffer was received and discarded due to lack of buffers
|
||||
#define OPENETH_INT_BUSY BIT(4)
|
||||
// OPENETH_INT_RXB: Frame received
|
||||
#define OPENETH_INT_RXB BIT(2)
|
||||
// OPENETH_INT_TXB: Frame transmitted
|
||||
#define OPENETH_INT_TXB BIT(0)
|
||||
|
||||
// IPGT, IPGR1, IPGR2 registers are not implemented in QEMU, hence not used here
|
||||
#define OPENETH_PACKETLEN_REG (OPENETH_BASE + 0x18)
|
||||
// OPENETH_MINFL: minimum frame length
|
||||
#define OPENETH_MINFL_S 16
|
||||
#define OPENETH_MINFL_V 0xffff
|
||||
#define OPENETH_MINFL_M (OPENETH_MINFL_V << OPENETH_MINFL_S)
|
||||
// OPENETH_MAXFL: maximum frame length
|
||||
#define OPENETH_MAXFL_S 0
|
||||
#define OPENETH_MAXFL_V 0xffff
|
||||
#define OPENETH_MAXFL_M (OPENETH_MAXFL_V << OPENETH_MAXFL_S)
|
||||
|
||||
// COLLCONF is not implemented in QEMU
|
||||
#define OPENETH_TX_BD_NUM_REG (OPENETH_BASE + 0x20)
|
||||
// CTRLMODER, MIIMODER are not implemented in QEMU
|
||||
#define OPENETH_MIICOMMAND_REG (OPENETH_BASE + 0x2c)
|
||||
// OPENETH_WCTRLDATA: write control data
|
||||
#define OPENETH_WCTRLDATA BIT(2)
|
||||
// OPENETH_RSTAT: read status
|
||||
#define OPENETH_RSTAT BIT(1)
|
||||
// OPENETH_SCANSTAT: scan status
|
||||
#define OPENETH_SCANSTAT BIT(0)
|
||||
|
||||
#define OPENETH_MIIADDRESS_REG (OPENETH_BASE + 0x30)
|
||||
// OPENETH_RGAD: register address
|
||||
#define OPENETH_RGAD_S 8
|
||||
#define OPENETH_RGAD_V 0x1f
|
||||
#define OPENETH_RGAD_M (OPENETH_RGAD_V << OPENETH_RGAD_S)
|
||||
// OPENETH_FIAD: PHY address
|
||||
#define OPENETH_FIAD_S 0
|
||||
#define OPENETH_FIAD_V 0x1f
|
||||
#define OPENETH_FIAD_N (OPENETH_FIAD_V << OPENETH_FIAD_S)
|
||||
|
||||
#define OPENETH_MIITX_DATA_REG (OPENETH_BASE + 0x34)
|
||||
#define OPENETH_MIIRX_DATA_REG (OPENETH_BASE + 0x38)
|
||||
#define OPENETH_MII_DATA_MASK 0xffff
|
||||
|
||||
#define OPENETH_MIISTATUS_REG (OPENETH_BASE + 0x3c)
|
||||
// OPENETH_LINKFAIL: link is down
|
||||
#define OPENETH_LINKFAIL BIT(0)
|
||||
|
||||
// OPENETH_MAC_ADDR0_REG: bytes 2-5 of the MAC address (byte 5 in LSB)
|
||||
#define OPENETH_MAC_ADDR0_REG (OPENETH_BASE + 0x40)
|
||||
// OPENETH_MAC_ADDR1_REG: bytes 0-1 of the MAC address (byte 1 in LSB)
|
||||
#define OPENETH_MAC_ADDR1_REG (OPENETH_BASE + 0x44)
|
||||
|
||||
#define OPENETH_HASH0_ADR_REG (OPENETH_BASE + 0x48)
|
||||
#define OPENETH_HASH1_ADR_REG (OPENETH_BASE + 0x4c)
|
||||
|
||||
// Location of the DMA descriptors
|
||||
#define OPENETH_DESC_BASE (OPENETH_BASE + 0x400)
|
||||
// Total number of (TX + RX) DMA descriptors
|
||||
#define OPENETH_DESC_CNT 128
|
||||
|
||||
|
||||
// Structures describing TX and RX descriptors.
|
||||
// The field names are same as in the OpenCores ethmac documentation.
|
||||
typedef struct {
|
||||
uint16_t cs: 1; //!< Carrier sense lost (flag set by HW)
|
||||
uint16_t df: 1; //!< Defer indication (flag set by HW)
|
||||
uint16_t lc: 1; //!< Late collision occured (flag set by HW)
|
||||
uint16_t rl: 1; //!< TX failed due to retransmission limit (flag set by HW)
|
||||
uint16_t rtry: 4; //!< Number of retries before the frame was sent (set by HW)
|
||||
uint16_t ur: 1; //!< Underrun status (flag set by HW)
|
||||
uint16_t rsv: 2; //!< Reserved
|
||||
uint16_t crc: 1; //!< Add CRC at the end of the packet
|
||||
uint16_t pad: 1; //!< Add padding to the end of short packets
|
||||
uint16_t wr: 1; //!< Wrap-around. 0: not the last descriptor in the table, 1: last descriptor.
|
||||
uint16_t irq: 1; //!< Generate interrupt after this descriptor is transmitted
|
||||
uint16_t rd: 1; //!< Descriptor ready. 0: descriptor owned by SW, 1: descriptor owned by HW. Cleared by HW.
|
||||
|
||||
uint16_t len; //!< Number of bytes to be transmitted
|
||||
void* txpnt; //!< Pointer to the data to transmit
|
||||
} openeth_tx_desc_t;
|
||||
|
||||
_Static_assert(sizeof(openeth_tx_desc_t) == 8, "incorrect size of openeth_tx_desc_t");
|
||||
|
||||
typedef struct {
|
||||
uint16_t lc: 1; //!< Late collision flag
|
||||
uint16_t crc: 1; //!< RX CRC error flag
|
||||
uint16_t sf: 1; //!< Frame shorter than set in PACKETLEN register
|
||||
uint16_t tl: 1; //!< Frame longer than set in PACKETLEN register
|
||||
uint16_t dn: 1; //!< Dribble nibble (frame length not divisible by 8 bits) flag
|
||||
uint16_t is: 1; //!< Invalid symbol flag
|
||||
uint16_t or: 1; //!< Overrun flag
|
||||
uint16_t m: 1; //!< Frame received because of the promiscuous mode
|
||||
uint16_t rsv: 5; //!< Reserved
|
||||
uint16_t wr: 1; //!< Wrap-around. 0: not the last descriptor in the table, 1: last descriptor.
|
||||
uint16_t irq: 1; //!< Generate interrupt after this descriptor is transmitted
|
||||
uint16_t e: 1; //!< The buffer is empty. 0: descriptor owned by SW, 1: descriptor owned by HW.
|
||||
|
||||
uint16_t len; //!< Number of bytes received (filled by HW)
|
||||
void* rxpnt; //!< Pointer to the receive buffer
|
||||
} openeth_rx_desc_t;
|
||||
|
||||
_Static_assert(sizeof(openeth_rx_desc_t) == 8, "incorrect size of openeth_rx_desc_t");
|
||||
|
||||
|
||||
static inline openeth_tx_desc_t* openeth_tx_desc(int idx)
|
||||
{
|
||||
assert(idx < TX_BUF_COUNT);
|
||||
return &((openeth_tx_desc_t*)OPENETH_DESC_BASE)[idx];
|
||||
}
|
||||
|
||||
static inline openeth_rx_desc_t* openeth_rx_desc(int idx)
|
||||
{
|
||||
assert(idx < OPENETH_DESC_CNT - TX_BUF_COUNT);
|
||||
return &((openeth_rx_desc_t*)OPENETH_DESC_BASE)[idx + TX_BUF_COUNT];
|
||||
}
|
||||
|
||||
static inline void openeth_enable(void)
|
||||
{
|
||||
REG_SET_BIT(OPENETH_MODER_REG, OPENETH_TXEN | OPENETH_RXEN | OPENETH_PRO);
|
||||
REG_SET_BIT(OPENETH_INT_MASK_REG, OPENETH_INT_RXB);
|
||||
}
|
||||
|
||||
static inline void openeth_disable(void)
|
||||
{
|
||||
REG_CLR_BIT(OPENETH_INT_MASK_REG, OPENETH_INT_RXB);
|
||||
REG_CLR_BIT(OPENETH_MODER_REG, OPENETH_TXEN | OPENETH_RXEN | OPENETH_PRO);
|
||||
}
|
||||
|
||||
static inline void openeth_reset(void)
|
||||
{
|
||||
REG_SET_BIT(OPENETH_MODER_REG, OPENETH_RST);
|
||||
REG_CLR_BIT(OPENETH_MODER_REG, OPENETH_RST);
|
||||
}
|
||||
|
||||
static inline void openeth_init_tx_desc(openeth_tx_desc_t* desc, void* buf)
|
||||
{
|
||||
*desc = (openeth_tx_desc_t) {
|
||||
.rd = 0,
|
||||
.txpnt = buf
|
||||
};
|
||||
}
|
||||
|
||||
static inline void openeth_init_rx_desc(openeth_rx_desc_t* desc, void* buf)
|
||||
{
|
||||
*desc = (openeth_rx_desc_t) {
|
||||
.e = 1,
|
||||
.irq = 1,
|
||||
.rxpnt = buf
|
||||
};
|
||||
}
|
||||
|
||||
static inline void openeth_set_tx_desc_cnt(int tx_desc_cnt)
|
||||
{
|
||||
assert(tx_desc_cnt <= OPENETH_DESC_CNT);
|
||||
REG_WRITE(OPENETH_TX_BD_NUM_REG, tx_desc_cnt);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -49,6 +49,17 @@ menu "Example Connection Configuration"
|
||||
select ETH_USE_SPI_ETHERNET
|
||||
help
|
||||
Select external SPI-Ethernet module.
|
||||
|
||||
config EXAMPLE_USE_OPENETH
|
||||
bool "OpenCores Ethernet MAC (EXPERIMENTAL)"
|
||||
select ETH_USE_OPENETH
|
||||
help
|
||||
When this option is enabled, the example is built with support for
|
||||
OpenCores Ethernet MAC, which allows testing the example in QEMU.
|
||||
Note that this option is used for internal testing purposes, and
|
||||
not officially supported. Examples built with this option enabled
|
||||
will not run on a real ESP32 chip.
|
||||
|
||||
endchoice
|
||||
|
||||
if EXAMPLE_USE_INTERNAL_ETHERNET
|
||||
|
||||
@ -232,7 +232,12 @@ static void start(void)
|
||||
eth_dm9051_config_t dm9051_config = ETH_DM9051_DEFAULT_CONFIG(spi_handle);
|
||||
s_mac = esp_eth_mac_new_dm9051(&dm9051_config, &mac_config);
|
||||
s_phy = esp_eth_phy_new_dm9051(&phy_config);
|
||||
#elif CONFIG_EXAMPLE_USE_OPENETH
|
||||
phy_config.autonego_timeout_ms = 100;
|
||||
s_mac = esp_eth_mac_new_openeth(&mac_config);
|
||||
s_phy = esp_eth_phy_new_dp83848(&phy_config);
|
||||
#endif
|
||||
|
||||
esp_eth_config_t config = ETH_DEFAULT_CONFIG(s_mac, s_phy);
|
||||
ESP_ERROR_CHECK(esp_eth_driver_install(&config, &s_eth_handle));
|
||||
s_connection_name = "Ethernet";
|
||||
|
||||
Loading…
Reference in New Issue
Block a user