mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
Merge branch 'feature/esp32c3_soc_changes' into 'master'
soc: Apply esp32c3 updates See merge request espressif/esp-idf!11712
This commit is contained in:
Angus Gratton
commit
30a96d22e1
@ -5,7 +5,6 @@ set(srcs "cpu_util_esp32c3.c"
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"rtc_pm.c"
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"rtc_sleep.c"
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"rtc_time.c"
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"soc_memory_layout.c"
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)
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add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
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@ -7,6 +7,7 @@ set(srcs
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"ledc_periph.c"
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"rmt_periph.c"
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"sigmadelta_periph.c"
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"soc_memory_layout.c"
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"i2s_periph.c"
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"i2c_periph.c"
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"uart_periph.c"
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37
components/soc/esp32c3/include/soc/bb_reg.h
Normal file
37
components/soc/esp32c3/include/soc/bb_reg.h
Normal file
@ -0,0 +1,37 @@
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// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
|
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
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#pragma once
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/* Some of the baseband control registers.
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* PU/PD fields defined here are used in sleep related functions.
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*/
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#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
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#define BB_FFT_FORCE_PU (BIT(3))
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#define BB_FFT_FORCE_PU_M (BIT(3))
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#define BB_FFT_FORCE_PU_V 1
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#define BB_FFT_FORCE_PU_S 3
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#define BB_FFT_FORCE_PD (BIT(2))
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#define BB_FFT_FORCE_PD_M (BIT(2))
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#define BB_FFT_FORCE_PD_V 1
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#define BB_FFT_FORCE_PD_S 2
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#define BB_DC_EST_FORCE_PU (BIT(1))
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#define BB_DC_EST_FORCE_PU_M (BIT(1))
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#define BB_DC_EST_FORCE_PU_V 1
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#define BB_DC_EST_FORCE_PU_S 1
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#define BB_DC_EST_FORCE_PD (BIT(0))
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#define BB_DC_EST_FORCE_PD_M (BIT(0))
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#define BB_DC_EST_FORCE_PD_V 1
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#define BB_DC_EST_FORCE_PD_S 0
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41
components/soc/esp32c3/include/soc/fe_reg.h
Normal file
41
components/soc/esp32c3/include/soc/fe_reg.h
Normal file
@ -0,0 +1,41 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
|
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "soc/soc.h"
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/* Some of the RF frontend control registers.
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* PU/PD fields defined here are used in sleep related functions.
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*/
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#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
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#define FE_IQ_EST_FORCE_PU (BIT(5))
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#define FE_IQ_EST_FORCE_PU_M (BIT(5))
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#define FE_IQ_EST_FORCE_PU_V 1
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#define FE_IQ_EST_FORCE_PU_S 5
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#define FE_IQ_EST_FORCE_PD (BIT(4))
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#define FE_IQ_EST_FORCE_PD_M (BIT(4))
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#define FE_IQ_EST_FORCE_PD_V 1
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#define FE_IQ_EST_FORCE_PD_S 4
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#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
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#define FE2_TX_INF_FORCE_PU (BIT(10))
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#define FE2_TX_INF_FORCE_PU_M (BIT(10))
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#define FE2_TX_INF_FORCE_PU_V 1
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#define FE2_TX_INF_FORCE_PU_S 10
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#define FE2_TX_INF_FORCE_PD (BIT(9))
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#define FE2_TX_INF_FORCE_PD_M (BIT(9))
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#define FE2_TX_INF_FORCE_PD_V 1
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#define FE2_TX_INF_FORCE_PD_S 9
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@ -14,12 +14,9 @@
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#pragma once
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#define APLL_MIN_FREQ (250000000)
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#define APLL_MAX_FREQ (500000000)
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#define APLL_I2S_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
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#define SOC_I2S_APLL_MIN_FREQ (250000000)
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#define SOC_I2S_APLL_MAX_FREQ (500000000)
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#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
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#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
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// ESP32-S3 have 1 I2S
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#define SOC_I2S_NUM (1)
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#define SOC_I2S_SUPPORT_PDM (0) // ESP32-S3 do not support PDM
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@ -328,7 +328,7 @@ typedef volatile struct {
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uint32_t val;
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} date;
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} i2s_dev_t;
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extern i2s_dev_t I2S1;
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extern i2s_dev_t I2S0;
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#ifdef __cplusplus
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}
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#endif
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26
components/soc/esp32c3/include/soc/int_caps.h
Normal file
26
components/soc/esp32c3/include/soc/int_caps.h
Normal file
@ -0,0 +1,26 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
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||||
|
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// http://www.apache.org/licenses/LICENSE-2.0
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//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SOC_INTERRUPT_LEVEL_CAN_SET (1)
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#define SOC_INTERRUPT_TYPE_CAN_SET (1)
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#ifdef __cplusplus
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}
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#endif
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@ -73,6 +73,18 @@
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#define MCU_SEL_V 0x7
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#define MCU_SEL_S 12
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#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
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#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
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#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
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#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
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#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
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#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
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#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
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#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
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#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
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#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
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#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
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#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
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#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
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@ -32,7 +32,7 @@ extern "C" {
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#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
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#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
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#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
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#define SOC_MMU_VADDR1_START_ADDR SOC_IRAM_LOW
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#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
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#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
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#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
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#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW
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55
components/soc/esp32c3/include/soc/nrx_reg.h
Normal file
55
components/soc/esp32c3/include/soc/nrx_reg.h
Normal file
@ -0,0 +1,55 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
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//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
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|
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#include "soc/soc.h"
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/* Some of the WiFi RX control registers.
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* PU/PD fields defined here are used in sleep related functions.
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*/
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#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
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#define NRX_CHAN_EST_FORCE_PU (BIT(7))
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#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
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#define NRX_CHAN_EST_FORCE_PU_V 1
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#define NRX_CHAN_EST_FORCE_PU_S 7
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#define NRX_CHAN_EST_FORCE_PD (BIT(6))
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#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
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#define NRX_CHAN_EST_FORCE_PD_V 1
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#define NRX_CHAN_EST_FORCE_PD_S 6
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#define NRX_RX_ROT_FORCE_PU (BIT(5))
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#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
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#define NRX_RX_ROT_FORCE_PU_V 1
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#define NRX_RX_ROT_FORCE_PU_S 5
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#define NRX_RX_ROT_FORCE_PD (BIT(4))
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#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
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#define NRX_RX_ROT_FORCE_PD_V 1
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#define NRX_RX_ROT_FORCE_PD_S 4
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#define NRX_VIT_FORCE_PU (BIT(3))
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#define NRX_VIT_FORCE_PU_M (BIT(3))
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#define NRX_VIT_FORCE_PU_V 1
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#define NRX_VIT_FORCE_PU_S 3
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#define NRX_VIT_FORCE_PD (BIT(2))
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#define NRX_VIT_FORCE_PD_M (BIT(2))
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#define NRX_VIT_FORCE_PD_V 1
|
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#define NRX_VIT_FORCE_PD_S 2
|
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#define NRX_DEMAP_FORCE_PU (BIT(1))
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#define NRX_DEMAP_FORCE_PU_M (BIT(1))
|
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#define NRX_DEMAP_FORCE_PU_V 1
|
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#define NRX_DEMAP_FORCE_PU_S 1
|
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#define NRX_DEMAP_FORCE_PD (BIT(0))
|
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#define NRX_DEMAP_FORCE_PD_M (BIT(0))
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#define NRX_DEMAP_FORCE_PD_V 1
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#define NRX_DEMAP_FORCE_PD_S 0
|
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@ -68,11 +68,16 @@ extern "C" {
|
||||
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
|
||||
* Valid if RTC_CNTL_DBG_ATTEN is 0.
|
||||
*/
|
||||
#define RTC_CNTL_DBIAS_1V00 0
|
||||
#define RTC_CNTL_DBIAS_1V05 4
|
||||
#define RTC_CNTL_DBIAS_1V10 5
|
||||
#define RTC_CNTL_DBIAS_1V15 6
|
||||
#define RTC_CNTL_DBIAS_1V20 7
|
||||
#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias
|
||||
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
|
||||
#define RTC_CNTL_DBIAS_0V95 16
|
||||
#define RTC_CNTL_DBIAS_1V00 18
|
||||
#define RTC_CNTL_DBIAS_1V05 20
|
||||
#define RTC_CNTL_DBIAS_1V10 23
|
||||
#define RTC_CNTL_DBIAS_1V15 25
|
||||
#define RTC_CNTL_DBIAS_1V20 28
|
||||
#define RTC_CNTL_DBIAS_1V25 30
|
||||
#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
|
||||
|
||||
#define DELAY_FAST_CLK_SWITCH 3
|
||||
#define DELAY_SLOW_CLK_SWITCH 300
|
||||
@ -83,30 +88,29 @@ extern "C" {
|
||||
*/
|
||||
#define XTAL_FREQ_EST_CYCLES 10
|
||||
|
||||
/* Core voltage needs to be increased in two cases:
|
||||
* 1. running at 240 MHz
|
||||
* 2. running with 80MHz Flash frequency
|
||||
*/
|
||||
#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
|
||||
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25
|
||||
#else
|
||||
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
|
||||
#endif
|
||||
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
|
||||
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
|
||||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 1
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (1000)
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (2)
|
||||
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
|
||||
|
||||
/*
|
||||
set sleep_init default param
|
||||
*/
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
|
||||
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
|
||||
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
|
||||
@ -114,19 +118,13 @@ set sleep_init default param
|
||||
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
|
||||
|
||||
#define APLL_SDM_STOP_VAL_1 0x09
|
||||
#define APLL_SDM_STOP_VAL_2_REV0 0x69
|
||||
#define APLL_SDM_STOP_VAL_2_REV1 0x49
|
||||
#define APLL_CAL_DELAY_1 0x0f
|
||||
#define APLL_CAL_DELAY_2 0x3f
|
||||
#define APLL_CAL_DELAY_3 0x1f
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
* Enum values should be equal to frequency in MHz.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_32M = 32,
|
||||
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
@ -243,23 +241,27 @@ typedef struct {
|
||||
typedef struct {
|
||||
uint16_t wifi_powerup_cycles : 7;
|
||||
uint16_t wifi_wait_cycles : 9;
|
||||
uint16_t rtc_powerup_cycles : 7;
|
||||
uint16_t rtc_wait_cycles : 9;
|
||||
uint16_t bt_powerup_cycles : 7;
|
||||
uint16_t bt_wait_cycles : 9;
|
||||
uint16_t cpu_top_powerup_cycles : 7;
|
||||
uint16_t cpu_top_wait_cycles : 9;
|
||||
uint16_t dg_wrap_powerup_cycles : 7;
|
||||
uint16_t dg_wrap_wait_cycles : 9;
|
||||
uint16_t rtc_mem_powerup_cycles : 7;
|
||||
uint16_t rtc_mem_wait_cycles : 9;
|
||||
uint16_t dg_peri_powerup_cycles : 7;
|
||||
uint16_t dg_peri_wait_cycles : 9;
|
||||
} rtc_init_config_t;
|
||||
|
||||
#define RTC_INIT_CONFIG_DEFAULT() { \
|
||||
.wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.wifi_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.rtc_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.rtc_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.bt_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.rtc_mem_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.rtc_mem_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
}
|
||||
|
||||
void rtc_clk_divider_set(uint32_t div);
|
||||
@ -589,19 +591,21 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val);
|
||||
* @brief Power down flags for rtc_sleep_pd function
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t dig_fpu : 1; //!< Set to 1 to power down digital part in sleep
|
||||
uint32_t rtc_fpu : 1; //!< Set to 1 to power down RTC memories in sleep
|
||||
uint32_t cpu_fpu : 1; //!< Set to 1 to power down digital memories and CPU in sleep
|
||||
uint32_t i2s_fpu : 1; //!< Set to 1 to power down I2S in sleep
|
||||
uint32_t bb_fpu : 1; //!< Set to 1 to power down WiFi in sleep
|
||||
uint32_t nrx_fpu : 1; //!< Set to 1 to power down WiFi in sleep
|
||||
uint32_t fe_fpu : 1; //!< Set to 1 to power down WiFi in sleep
|
||||
} rtc_sleep_pd_config_t;
|
||||
uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep
|
||||
uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep
|
||||
uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep
|
||||
uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep
|
||||
uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
|
||||
uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
|
||||
uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
|
||||
uint32_t sram_fpu : 1; //!< Set to 1 to power UP SRAM in sleep
|
||||
uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep
|
||||
} rtc_sleep_pu_config_t;
|
||||
|
||||
/**
|
||||
* Initializer for rtc_sleep_pd_config_t which sets all flags to the same value
|
||||
* Initializer for rtc_sleep_pu_config_t which sets all flags to the same value
|
||||
*/
|
||||
#define RTC_SLEEP_PD_CONFIG_ALL(val) {\
|
||||
#define RTC_SLEEP_PU_CONFIG_ALL(val) {\
|
||||
.dig_fpu = (val), \
|
||||
.rtc_fpu = (val), \
|
||||
.cpu_fpu = (val), \
|
||||
@ -609,26 +613,31 @@ typedef struct {
|
||||
.bb_fpu = (val), \
|
||||
.nrx_fpu = (val), \
|
||||
.fe_fpu = (val), \
|
||||
.sram_fpu = (val), \
|
||||
.rom_ram_fpu = (val), \
|
||||
}
|
||||
|
||||
void rtc_sleep_pd(rtc_sleep_pd_config_t cfg);
|
||||
void rtc_sleep_pu(rtc_sleep_pu_config_t cfg);
|
||||
|
||||
/**
|
||||
* @brief sleep configuration for rtc_sleep_init function
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
|
||||
uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if touch is used)
|
||||
uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
|
||||
uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory
|
||||
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
|
||||
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
|
||||
uint32_t wifi_pd_en : 1; //!< power down WiFi
|
||||
uint32_t bt_pd_en : 1; //!< power down BT
|
||||
uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
|
||||
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
|
||||
uint32_t deep_slp : 1; //!< power down digital domain
|
||||
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
|
||||
uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode
|
||||
uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode
|
||||
uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode
|
||||
uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode
|
||||
uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode
|
||||
uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode
|
||||
uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
|
||||
uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
|
||||
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
|
||||
uint32_t deep_slp_reject : 1;
|
||||
uint32_t light_slp_reject : 1;
|
||||
@ -649,12 +658,15 @@ typedef struct {
|
||||
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
|
||||
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
|
||||
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
|
||||
.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
|
||||
.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
|
||||
.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
|
||||
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
|
||||
.wdt_flashboot_mod_en = 0, \
|
||||
.dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \
|
||||
.dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \
|
||||
.dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
|
||||
.dig_dbias_slp = RTC_CNTL_DBIAS_SLP, \
|
||||
.rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
|
||||
.rtc_dbias_slp = RTC_CNTL_DBIAS_1V00, \
|
||||
.rtc_dbias_slp = RTC_CNTL_DBIAS_SLP, \
|
||||
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
|
||||
.deep_slp_reject = 1, \
|
||||
.light_slp_reject = 1 \
|
||||
@ -666,7 +678,10 @@ typedef struct {
|
||||
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory
|
||||
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
|
||||
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
|
||||
#define RTC_SLEEP_PD_WIFI BIT(6)
|
||||
#define RTC_SLEEP_PD_WIFI BIT(6) //!< Power down WIFI
|
||||
#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT
|
||||
#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
|
||||
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
|
||||
|
||||
/**
|
||||
* @brief Prepare the chip to enter sleep mode
|
||||
@ -683,6 +698,17 @@ typedef struct {
|
||||
*/
|
||||
void rtc_sleep_init(rtc_sleep_config_t cfg);
|
||||
|
||||
/**
|
||||
* @brief Low level initialize for rtc state machine waiting cycles after waking up
|
||||
*
|
||||
* This function configures the cycles chip need to wait for internal 8MHz
|
||||
* oscillator and external 40MHz crystal. As we configure fixed time for waiting
|
||||
* crystal, we need to pass period to calculate cycles. Now this function only
|
||||
* used in lightsleep mode.
|
||||
*
|
||||
* @param slowclk_period re-calibrated slow clock period
|
||||
*/
|
||||
void rtc_sleep_low_init(uint32_t slowclk_period);
|
||||
|
||||
/**
|
||||
* @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
|
||||
@ -700,7 +726,6 @@ void rtc_sleep_set_wakeup_time(uint64_t t);
|
||||
#define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only)
|
||||
#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only)
|
||||
#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only)
|
||||
#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup
|
||||
#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only)
|
||||
#define RTC_COCPU_TRIG_EN BIT(11)
|
||||
#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12)
|
||||
@ -747,6 +772,7 @@ typedef struct {
|
||||
uint32_t xtal_fpu : 1;
|
||||
uint32_t bbpll_fpu : 1;
|
||||
uint32_t cpu_waiti_clk_gate : 1;
|
||||
uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise.
|
||||
} rtc_config_t;
|
||||
|
||||
/**
|
||||
@ -764,7 +790,8 @@ typedef struct {
|
||||
.rtc_dboost_fpd = 1, \
|
||||
.xtal_fpu = 0, \
|
||||
.bbpll_fpu = 0, \
|
||||
.cpu_waiti_clk_gate = 1\
|
||||
.cpu_waiti_clk_gate = 1, \
|
||||
.cali_ocode = 0\
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -389,6 +389,7 @@ extern "C" {
|
||||
#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
|
||||
#define RTC_CNTL_MIN_SLP_VAL_V 0xFF
|
||||
#define RTC_CNTL_MIN_SLP_VAL_S 8
|
||||
#define RTC_CNTL_MIN_SLP_VAL_MIN 2
|
||||
|
||||
#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030)
|
||||
/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */
|
||||
@ -1035,7 +1036,6 @@ extern "C" {
|
||||
#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
|
||||
#define RTC_CNTL_CK8M_DFREQ_V 0xFF
|
||||
#define RTC_CNTL_CK8M_DFREQ_S 17
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 //TODO, may change in chip7.2.4
|
||||
/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
|
||||
/*description: CK8M force no gating during sleep*/
|
||||
#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16))
|
||||
@ -1327,25 +1327,6 @@ extern "C" {
|
||||
#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28))
|
||||
#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1
|
||||
#define RTC_CNTL_DBOOST_FORCE_PD_S 28
|
||||
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
|
||||
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
|
||||
* Valid if RTC_CNTL_DBG_ATTEN is 0.
|
||||
*/
|
||||
#define RTC_CNTL_DIG_DBIAS_0V85 0
|
||||
#define RTC_CNTL_DIG_DBIAS_0V90 1
|
||||
#define RTC_CNTL_DIG_DBIAS_0V95 2
|
||||
#define RTC_CNTL_DIG_DBIAS_1V00 3
|
||||
#define RTC_CNTL_DIG_DBIAS_1V05 4
|
||||
#define RTC_CNTL_DIG_DBIAS_1V10 5
|
||||
#define RTC_CNTL_DIG_DBIAS_1V15 6
|
||||
#define RTC_CNTL_DIG_DBIAS_1V20 7
|
||||
|
||||
/* The value of 1V00 can be adjusted between 0~3*/
|
||||
#define RTC_CNTL_DBIAS_1V00 0
|
||||
#define RTC_CNTL_DBIAS_1V05 4
|
||||
#define RTC_CNTL_DBIAS_1V10 5
|
||||
#define RTC_CNTL_DBIAS_1V15 6
|
||||
#define RTC_CNTL_DBIAS_1V20 7
|
||||
|
||||
/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */
|
||||
/*description: SCK_DCAP*/
|
||||
|
||||
@ -42,6 +42,8 @@
|
||||
#define DR_REG_SPI1_BASE 0x60002000
|
||||
#define DR_REG_SPI0_BASE 0x60003000
|
||||
#define DR_REG_GPIO_BASE 0x60004000
|
||||
#define DR_REG_FE2_BASE 0x60005000
|
||||
#define DR_REG_FE_BASE 0x60006000
|
||||
#define DR_REG_RTCCNTL_BASE 0x60008000
|
||||
#define DR_REG_IO_MUX_BASE 0x60009000
|
||||
#define DR_REG_RTC_I2C_BASE 0x6000e000
|
||||
@ -51,6 +53,8 @@
|
||||
#define DR_REG_RMT_BASE 0x60016000
|
||||
#define DR_REG_LEDC_BASE 0x60019000
|
||||
#define DR_REG_EFUSE_BASE 0x60008800
|
||||
#define DR_REG_NRX_BASE 0x6001CC00
|
||||
#define DR_REG_BB_BASE 0x6001D000
|
||||
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
|
||||
#define DR_REG_TIMERGROUP1_BASE 0x60020000
|
||||
#define DR_REG_SYS_TIMER_BASE 0x60023000
|
||||
@ -312,6 +316,9 @@
|
||||
#define ETS_CACHEERR_INUM 25
|
||||
#define ETS_DPORT_INUM 28
|
||||
|
||||
//CPU0 Max valid interrupt number
|
||||
#define ETS_MAX_INUM 31
|
||||
|
||||
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
|
||||
#define ETS_SLC_INUM 1
|
||||
#define ETS_UART0_INUM 5
|
||||
@ -324,3 +331,6 @@
|
||||
|
||||
//Invalid interrupt for number interrupt matrix
|
||||
#define ETS_INVALID_INUM 0
|
||||
|
||||
//Interrupt medium level, used for INT WDT for example
|
||||
#define SOC_INTERRUPT_LEVEL_MEDIUM 4
|
||||
|
||||
@ -44,10 +44,26 @@
|
||||
#include "sha_caps.h"
|
||||
#include "spi_caps.h"
|
||||
#include "uart_caps.h"
|
||||
#include "int_caps.h"
|
||||
|
||||
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
|
||||
#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */
|
||||
|
||||
/*-------------------------- ADC CAPS -------------------------------*/
|
||||
#define SOC_ADC_PERIPH_NUM (2)
|
||||
#define SOC_ADC_PATT_LEN_MAX (16)
|
||||
|
||||
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
|
||||
#define SOC_ADC_MAX_CHANNEL_NUM (10)
|
||||
|
||||
/**
|
||||
* Check if adc support digital controller (DMA) mode.
|
||||
* @value
|
||||
* - 1 : support;
|
||||
* - 0 : not support;
|
||||
*/
|
||||
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1
|
||||
|
||||
/*-------------------------- AES CAPS -----------------------------------------*/
|
||||
#define SOC_AES_SUPPORT_DMA (1)
|
||||
|
||||
|
||||
0
components/soc/esp32c3/include/soc/soc_ulp.h
Normal file
0
components/soc/esp32c3/include/soc/soc_ulp.h
Normal file
@ -168,24 +168,23 @@ extern "C" {
|
||||
#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
|
||||
/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
|
||||
/*description: */
|
||||
#define SYSTEM_WIFI_CLK_EN 0xFFFFFFFF
|
||||
#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF
|
||||
#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S))
|
||||
#define SYSTEM_WIFI_CLK_EN_V 0xFFFFFFFF
|
||||
#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF
|
||||
#define SYSTEM_WIFI_CLK_EN_S 0
|
||||
|
||||
/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21
|
||||
Bit15 not included here because of the bit now can't be cleared */
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN 0x003807cf
|
||||
/* Mask for all Wifi clock bits, 6 */
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN 0x0
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x7cf
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN_S 0
|
||||
/* Mask for all Bluetooth clock bits - 11, 16, 17 */
|
||||
#define SYSTEM_WIFI_CLK_BT_EN 0x61
|
||||
/* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */
|
||||
#define SYSTEM_WIFI_CLK_BT_EN 0x0
|
||||
#define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
|
||||
#define SYSTEM_WIFI_CLK_BT_EN_V 0x61
|
||||
#define SYSTEM_WIFI_CLK_BT_EN_S 11
|
||||
/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
|
||||
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
|
||||
#define SYSTEM_WIFI_CLK_BT_EN_V 0x0
|
||||
#define SYSTEM_WIFI_CLK_BT_EN_S 0
|
||||
/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
|
||||
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
|
||||
|
||||
/* Digital team to check */
|
||||
//bluetooth baseband bit11
|
||||
@ -204,15 +203,19 @@ extern "C" {
|
||||
#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
|
||||
/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define SYSTEM_RW_BTLP_RST (BIT(10))
|
||||
#define SYSTEM_RW_BTMAC_RST (BIT(9))
|
||||
#define SYSTEM_MACPWR_RST (BIT(8))
|
||||
#define SYSTEM_SDIO_RST (BIT(5))
|
||||
#define SYSTEM_BTMAC_RST (BIT(4))
|
||||
#define SYSTEM_BT_RST (BIT(3))
|
||||
#define SYSTEM_MAC_RST (BIT(2))
|
||||
#define SYSTEM_FE_RST (BIT(1))
|
||||
#define SYSTEM_BB_RST (BIT(0))
|
||||
#define SYSTEM_BB_RST BIT(0)
|
||||
#define SYSTEM_FE_RST BIT(1)
|
||||
#define SYSTEM_MAC_RST BIT(2)
|
||||
#define SYSTEM_BT_RST BIT(3)
|
||||
#define SYSTEM_BTMAC_RST BIT(4)
|
||||
#define SYSTEM_SDIO_RST BIT(5)
|
||||
#define SYSTEM_EMAC_RST BIT(7)
|
||||
#define SYSTEM_MACPWR_RST BIT(8)
|
||||
#define SYSTEM_RW_BTMAC_RST BIT(9)
|
||||
#define SYSTEM_RW_BTLP_RST BIT(10)
|
||||
#define BLE_REG_REST_BIT BIT(11)
|
||||
#define BLE_PWR_REG_REST_BIT BIT(12)
|
||||
#define BLE_BB_REG_REST_BIT BIT(13)
|
||||
|
||||
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C)
|
||||
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
|
||||
@ -65,7 +65,7 @@ const soc_memory_region_t soc_memory_regions[] = {
|
||||
{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 5, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x3FCC0000, 0x20000, 1, 0x403C0000}, //Block 9, can be used as trace memory
|
||||
#ifdef CONFIG_ESP32C3_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ 0x50000000, 0x2000, 5, 0}, //Fast RTC memory
|
||||
{ 0x50000000, 0x2000, 4, 0}, //Fast RTC memory
|
||||
#endif
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user