diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild
index ac4d1d14b9..1a091a49f4 100644
--- a/components/bootloader/Kconfig.projbuild
+++ b/components/bootloader/Kconfig.projbuild
@@ -28,8 +28,17 @@ config LOG_BOOTLOADER_LEVEL
     default 4 if LOG_BOOTLOADER_LEVEL_DEBUG
     default 5 if LOG_BOOTLOADER_LEVEL_VERBOSE
 
-endmenu
+config BOOTLOADER_VDDSDIO_BOOST
+    bool "Increase VDDSDIO LDO voltage to 1.9V"
+    default y
+    help
+        If this option is enabled, and VDDSDIO LDO is set to 1.8V (using EFUSE
+        or MTDI bootstrapping pin), bootloader will change LDO settings to
+        output 1.9V instead. This helps prevent flash chip from browning out
+        during flash programming operations.
+        For 3.3V flash, this option has no effect.
 
+endmenu  # Bootloader
 
 
 menu "Security features"
diff --git a/components/bootloader/src/main/bootloader_start.c b/components/bootloader/src/main/bootloader_start.c
index fd062a5f91..4274fe8402 100644
--- a/components/bootloader/src/main/bootloader_start.c
+++ b/components/bootloader/src/main/bootloader_start.c
@@ -72,6 +72,8 @@ static void set_cache_and_start_app(uint32_t drom_addr,
     uint32_t irom_size,
     uint32_t entry_addr);
 static void update_flash_config(const esp_image_header_t* pfhdr);
+static void vddsdio_configure();
+static void flash_gpio_configure();
 static void clock_configure(void);
 static void uart_console_configure(void);
 static void wdt_reset_check(void);
@@ -237,6 +239,8 @@ static bool ota_select_valid(const esp_ota_select_entry_t *s)
 
 void bootloader_main()
 {
+    vddsdio_configure();
+    flash_gpio_configure();
     clock_configure();
     uart_console_configure();
     wdt_reset_check();
@@ -697,6 +701,104 @@ void print_flash_info(const esp_image_header_t* phdr)
 #endif
 }
 
+static void vddsdio_configure()
+{
+#if CONFIG_BOOTLOADER_VDDSDIO_BOOST
+    rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
+    if (cfg.tieh == 0) {    // 1.8V is used
+        cfg.drefh = 3;
+        cfg.drefm = 3;
+        cfg.drefl = 3;
+        cfg.force = 1;
+        cfg.enable = 1;
+        rtc_vddsdio_set_config(cfg);
+        ets_delay_us(10); // wait for regulator to become stable
+    }
+#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
+}
+
+
+#define FLASH_CLK_IO      6
+#define FLASH_CS_IO       11
+#define FLASH_SPIQ_IO     7
+#define FLASH_SPID_IO     8
+#define FLASH_SPIWP_IO    10
+#define FLASH_SPIHD_IO    9
+#define FLASH_IO_MATRIX_DUMMY_40M   1
+#define FLASH_IO_MATRIX_DUMMY_80M   2
+static void IRAM_ATTR flash_gpio_configure()
+{
+    int spi_cache_dummy = 0;
+    int drv = 2;
+#if CONFIG_FLASHMODE_QIO
+    spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;   //qio 3
+#elif CONFIG_FLASHMODE_QOUT
+    spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;  //qout 7
+#elif CONFIG_FLASHMODE_DIO
+    spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;   //dio 3
+#elif CONFIG_FLASHMODE_DOUT
+    spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;  //dout 7
+#endif
+    /* dummy_len_plus values defined in ROM for SPI flash configuration */
+    extern uint8_t g_rom_spiflash_dummy_len_plus[];
+#if CONFIG_ESPTOOLPY_FLASHFREQ_40M
+    g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M;
+    g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M;
+    SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M, SPI_USR_DUMMY_CYCLELEN_S);  //DUMMY
+#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
+    g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M;
+    g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M;
+    SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S);  //DUMMY
+    drv = 3;
+#endif
+
+    uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
+    uint32_t pkg_ver = chip_ver & 0x7;
+
+    if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
+        // For ESP32D2WD the SPI pins are already configured
+        ESP_LOGI(TAG, "Detected ESP32D2WD");
+        //flash clock signal should come from IO MUX.
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+    } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
+        // For ESP32PICOD2 the SPI pins are already configured
+        ESP_LOGI(TAG, "Detected ESP32PICOD2");
+        //flash clock signal should come from IO MUX.
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+    } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
+        // For ESP32PICOD4 the SPI pins are already configured
+        ESP_LOGI(TAG, "Detected ESP32PICOD4");
+        //flash clock signal should come from IO MUX.
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+    } else {
+        ESP_LOGI(TAG, "Detected ESP32");
+        const uint32_t spiconfig = ets_efuse_get_spiconfig();
+        if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
+            gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
+            gpio_matrix_out(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
+            gpio_matrix_in(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
+            gpio_matrix_out(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
+            gpio_matrix_in(FLASH_SPID_IO, SPID_IN_IDX, 0);
+            gpio_matrix_out(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
+            gpio_matrix_in(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
+            gpio_matrix_out(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
+            gpio_matrix_in(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
+            //select pin function gpio
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
+            // flash clock signal should come from IO MUX.
+            // set drive ability for clock
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+            SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+        }
+    }
+}
 
 static void clock_configure(void)
 {
diff --git a/components/bootloader/src/main/flash_qio_mode.c b/components/bootloader/src/main/flash_qio_mode.c
index cd288290cb..4e4bb5d2cf 100644
--- a/components/bootloader/src/main/flash_qio_mode.c
+++ b/components/bootloader/src/main/flash_qio_mode.c
@@ -163,7 +163,7 @@ static void enable_qio_mode(read_status_fn_t read_status_fn,
         // spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP.
         //
         // For now, in this situation we only support Quad I/O mode for ESP32-D2WD where WP pin is known.
-        uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_RESERVE);
+        uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
         uint32_t pkg_ver = chip_ver & 0x7;
         const uint32_t PKG_VER_ESP32_D2WD = 2; // TODO: use chip detection API once available
         if (pkg_ver != PKG_VER_ESP32_D2WD) {
diff --git a/components/esp32/system_api.c b/components/esp32/system_api.c
index c79761fd7d..b3c54b12bf 100644
--- a/components/esp32/system_api.c
+++ b/components/esp32/system_api.c
@@ -291,6 +291,14 @@ void IRAM_ATTR esp_restart_noos()
     uart_tx_wait_idle(0);
     uart_tx_wait_idle(1);
     uart_tx_wait_idle(2);
+    // 2nd stage bootloader reconfigures SPI flash signals.
+    // Reset them to the defaults expected by ROM.
+    WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
+    WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
+    WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
+    WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
+    WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
+    WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
 
     // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
     DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 
@@ -364,8 +372,10 @@ static void get_chip_info_esp32(esp_chip_info_t* out_info)
     if ((reg & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
         out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
     }
-    if (((reg & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S) ==
-            EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
+    int package = (reg & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S;
+    if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
+        package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
+        package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
         out_info->features |= CHIP_FEATURE_EMB_FLASH;
     }
 }
diff --git a/components/soc/esp32/include/soc/efuse_reg.h b/components/soc/esp32/include/soc/efuse_reg.h
index b9ad20ee64..5b16114d00 100644
--- a/components/soc/esp32/include/soc/efuse_reg.h
+++ b/components/soc/esp32/include/soc/efuse_reg.h
@@ -100,6 +100,9 @@
 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6  0
 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5  1
 #define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5  2
+#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2  4
+#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4  5
+
 /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */
 /*description: read for SPI_pad_config_hd*/
 #define EFUSE_RD_SPI_PAD_CONFIG_HD  0x0000001F
diff --git a/components/soc/esp32/include/soc/gpio_reg.h b/components/soc/esp32/include/soc/gpio_reg.h
index 1f4b08d43d..8168f4ba12 100644
--- a/components/soc/esp32/include/soc/gpio_reg.h
+++ b/components/soc/esp32/include/soc/gpio_reg.h
@@ -129,8 +129,7 @@
 
 #define GPIO_STRAP_REG          (DR_REG_GPIO_BASE + 0x0038)
 /* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default:  ; */
-/*description: GPIO strapping results: {2'd0  boot_sel_dig[7:1]  vsdio_boot_sel
-  boot_sel_chip[5:0]}.   Boot_sel_dig[7:1]: {U0RXD  SD_CLK  SD_CMD  SD_DATA0  SD_DATA1  SD_DATA2  SD_DATA3}.  vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0  U0TXD  GPIO2  GPIO4  MTDO  GPIO5}*/
+/*description: {10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5} */
 #define GPIO_STRAPPING  0x0000FFFF
 #define GPIO_STRAPPING_M  ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
 #define GPIO_STRAPPING_V  0xFFFF
diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h
index a85265fdc1..2a59269945 100644
--- a/components/soc/esp32/include/soc/rtc.h
+++ b/components/soc/esp32/include/soc/rtc.h
@@ -524,6 +524,36 @@ typedef struct {
  */
 void rtc_init(rtc_config_t cfg);
 
+/**
+ * Structure describing vddsdio configuration
+ */
+typedef struct {
+    uint32_t force : 1;     //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
+    uint32_t enable : 1;    //!< Enable VDDSDIO regulator
+    uint32_t tieh  : 1;     //!< Select VDDSDIO voltage: 1 — 1.8V, 0 — 3.3V
+    uint32_t drefh : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefm : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefl : 2;     //!< Tuning parameter for VDDSDIO regulator
+} rtc_vddsdio_config_t;
+
+/**
+ * Get current VDDSDIO configuration
+ * If VDDSDIO configuration is overridden by RTC, get values from RTC
+ * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
+ * Otherwise, use default values and the level of MTDI bootstrapping pin.
+ * @return currently used VDDSDIO configuration
+ */
+rtc_vddsdio_config_t rtc_vddsdio_get_config();
+
+/**
+ * Set new VDDSDIO configuration using RTC registers.
+ * If config.force == 1, this overrides configuration done using bootstrapping
+ * pins and EFUSE.
+ *
+ * @param config new VDDSDIO configuration
+ */
+void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
+
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32/rtc_init.c b/components/soc/esp32/rtc_init.c
index ff7b6b73cc..44786fbcc5 100644
--- a/components/soc/esp32/rtc_init.c
+++ b/components/soc/esp32/rtc_init.c
@@ -18,6 +18,8 @@
 #include "soc/rtc.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/dport_reg.h"
+#include "soc/efuse_reg.h"
+#include "soc/gpio_reg.h"
 
 
 void rtc_init(rtc_config_t cfg)
@@ -94,3 +96,51 @@ void rtc_init(rtc_config_t cfg)
         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
     }
 }
+
+rtc_vddsdio_config_t rtc_vddsdio_get_config()
+{
+    rtc_vddsdio_config_t result;
+    uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);
+    result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S;
+    result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S;
+    result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S;
+    if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) {
+        // Get configuration from RTC
+        result.force = 1;
+        result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
+        result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
+        return result;
+    }
+    uint32_t efuse_reg = REG_READ(EFUSE_BLK0_RDATA4_REG);
+    if (efuse_reg & EFUSE_RD_SDIO_FORCE) {
+        // Get configuration from EFUSE
+        result.force = 0;
+        result.enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) >> EFUSE_RD_XPD_SDIO_REG_S;
+        result.tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) >> EFUSE_RD_SDIO_TIEH_S;
+        // in this case, DREFH/M/L are also set from EFUSE
+        result.drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) >> EFUSE_RD_SDIO_DREFH_S;
+        result.drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M) >> EFUSE_RD_SDIO_DREFM_S;
+        result.drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M) >> EFUSE_RD_SDIO_DREFL_S;
+        return result;
+    }
+
+    // Otherwise, VDD_SDIO is controlled by bootstrapping pin
+    uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
+    result.force = 0;
+    result.tieh = (strap_reg & BIT(5)) ? 0 : 1;
+    result.enable = result.tieh == 0; // only power on the regulator if VDD=1.8
+    return result;
+}
+
+void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
+{
+    uint32_t val = 0;
+    val |= (config.force << RTC_CNTL_SDIO_FORCE_S);
+    val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S);
+    val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S);
+    val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S);
+    val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S);
+    val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S);
+    val |= RTC_CNTL_SDIO_PD_EN;
+    REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
+}