alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Make sure cache is disabled/enabled when *both* CPUs are running inside the iram guard code

Browse Source
This commit is contained in:
Jeroen Domburg 2017-09-04 20:11:15 +08:00 committed by zhangyanjiao
parent ca9993eca3
commit 2fa801dec4
1 changed files with 17 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
components/spi_flash/cache_utils.c
View File

@ -59,6 +59,12 @@ void spi_flash_op_unlock()
{ {
xSemaphoreGive(s_flash_op_mutex); xSemaphoreGive(s_flash_op_mutex);
} }
/*
If you're going to modify this, keep in mind that while the flash caches of the pro and app
cpu are separate, the psram cache is *not*. If one of the CPUs returns from a flash routine
with its cache enabled but the other CPUs cache is not enabled yet, you will have problems
when accessing psram from the former CPU.
*/
void IRAM_ATTR spi_flash_op_block_func(void* arg) void IRAM_ATTR spi_flash_op_block_func(void* arg)
{ {
@ -67,8 +73,6 @@ void IRAM_ATTR spi_flash_op_block_func(void* arg)
// Restore interrupts that aren't located in IRAM // Restore interrupts that aren't located in IRAM
esp_intr_noniram_disable(); esp_intr_noniram_disable();
uint32_t cpuid = (uint32_t) arg; uint32_t cpuid = (uint32_t) arg;
// Disable cache so that flash operation can start
spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);
// s_flash_op_complete flag is cleared on *this* CPU, otherwise the other // s_flash_op_complete flag is cleared on *this* CPU, otherwise the other
// CPU may reset the flag back to false before IPC task has a chance to check it // CPU may reset the flag back to false before IPC task has a chance to check it
// (if it is preempted by an ISR taking non-trivial amount of time) // (if it is preempted by an ISR taking non-trivial amount of time)
@ -122,8 +126,12 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
} }
// Kill interrupts that aren't located in IRAM // Kill interrupts that aren't located in IRAM
esp_intr_noniram_disable(); esp_intr_noniram_disable();
// Disable cache on this CPU as well // This CPU executes this routine, with non-IRAM interrupts and the scheduler
// disabled. The other CPU is spinning in the spi_flash_op_block_func task, also
// with non-iram interrupts and the scheduler disabled. None of these CPUs will
// touch external RAM or flash this way, so we can safely disable caches.
spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]); spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);
spi_flash_disable_cache(other_cpuid, &s_flash_op_cache_state[other_cpuid]);
} }
void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu() void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
@ -133,22 +141,20 @@ void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
#ifndef NDEBUG #ifndef NDEBUG
// Sanity check: flash operation ends on the same CPU as it has started // Sanity check: flash operation ends on the same CPU as it has started
assert(cpuid == s_flash_op_cpu); assert(cpuid == s_flash_op_cpu);
// More sanity check: if scheduler isn't started, only CPU0 can call this.
assert(!(xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED && cpuid != 0));
s_flash_op_cpu = -1; s_flash_op_cpu = -1;
#endif #endif
// Re-enable cache on this CPU // Re-enable cache on both CPUs. After this, cache (flash and external RAM) should work again.
spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]); spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) {
// Scheduler is not running yet — this means we are running on PRO CPU.
// other_cpuid is APP CPU, and it is either in reset or is spinning in
// user_start_cpu1, which is in IRAM. So we can simply reenable cache.
assert(other_cpuid == 1);
spi_flash_restore_cache(other_cpuid, s_flash_op_cache_state[other_cpuid]); spi_flash_restore_cache(other_cpuid, s_flash_op_cache_state[other_cpuid]);
} else {
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
// Signal to spi_flash_op_block_task that flash operation is complete // Signal to spi_flash_op_block_task that flash operation is complete
s_flash_op_complete = true; s_flash_op_complete = true;
} }
// Re-enable non-iram interrupts // Re-enable non-iram interrupts
esp_intr_noniram_enable(); esp_intr_noniram_enable();