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https://github.com/espressif/esp-idf.git
synced 2024-09-20 00:36:01 -04:00
ld scripts: fix overlap between bootloader and application IRAM ranges
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abecab7525
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2fa00ebd90
@ -51,7 +51,7 @@ extern void Cache_Flush(int);
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void bootloader_main();
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void unpack_load_app(const esp_partition_pos_t *app_node);
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void print_flash_info(const esp_image_header_t* pfhdr);
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void IRAM_ATTR set_cache_and_start_app(uint32_t drom_addr,
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void set_cache_and_start_app(uint32_t drom_addr,
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uint32_t drom_load_addr,
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uint32_t drom_size,
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uint32_t irom_addr,
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@ -445,7 +445,7 @@ void unpack_load_app(const esp_partition_pos_t* partition)
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image_header.entry_addr);
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}
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void IRAM_ATTR set_cache_and_start_app(
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void set_cache_and_start_app(
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uint32_t drom_addr,
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uint32_t drom_load_addr,
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uint32_t drom_size,
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@ -456,9 +456,7 @@ void IRAM_ATTR set_cache_and_start_app(
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{
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ESP_LOGD(TAG, "configure drom and irom and start");
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Cache_Read_Disable( 0 );
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Cache_Read_Disable( 1 );
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Cache_Flush( 0 );
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Cache_Flush( 1 );
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uint32_t drom_page_count = (drom_size + 64*1024 - 1) / (64*1024); // round up to 64k
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ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d", drom_addr & 0xffff0000, drom_load_addr & 0xffff0000, drom_size, drom_page_count );
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int rc = cache_flash_mmu_set( 0, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count );
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@ -474,7 +472,8 @@ void IRAM_ATTR set_cache_and_start_app(
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REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
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REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
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Cache_Read_Enable( 0 );
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Cache_Read_Enable( 1 );
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// Application will need to do Cache_Flush(1) and Cache_Read_Enable(1)
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ESP_LOGD(TAG, "start: 0x%08x", entry_addr);
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typedef void (*entry_t)(void);
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@ -15,7 +15,7 @@ MEMORY
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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dport0_seg (RW) : org = 0x3FF00000, len = 0x10 /* IO */
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iram_seg (RWX) : org = 0x40098000, len = 0x1000
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iram_seg (RWX) : org = 0x40080000, len = 0x400 /* 1k of IRAM used by bootloader functions which need to flush/enable APP CPU cache */
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iram_pool_1_seg (RWX) : org = 0x40078000, len = 0x8000 /* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, until we enable APP CPU cache */
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dram_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/
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}
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@ -20,6 +20,7 @@
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#include "rom/ets_sys.h"
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#include "rom/uart.h"
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#include "rom/rtc.h"
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#include "rom/cache.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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@ -110,7 +111,9 @@ void IRAM_ATTR call_start_cpu0()
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#if !CONFIG_FREERTOS_UNICORE
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ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
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//Flush and enable icache for APP CPU
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Cache_Flush(1);
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Cache_Read_Enable(1);
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//Un-stall the app cpu; the panic handler may have stalled it.
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CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C1_M);
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C0_M);
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