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feat(gdma): distinguish abnormal and normal eof in the gdma event data
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@ -535,7 +535,7 @@ esp_err_t gdma_register_rx_event_callbacks(gdma_channel_handle_t dma_chan, gdma_
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// enable/disable GDMA interrupt events for RX channel
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portENTER_CRITICAL(&pair->spinlock);
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gdma_hal_enable_intr(hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, GDMA_LL_EVENT_RX_SUC_EOF, cbs->on_recv_eof != NULL);
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gdma_hal_enable_intr(hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, GDMA_LL_EVENT_RX_SUC_EOF | GDMA_LL_EVENT_RX_ERR_EOF, cbs->on_recv_eof != NULL);
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gdma_hal_enable_intr(hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, GDMA_LL_EVENT_RX_DESC_ERROR, cbs->on_descr_err != NULL);
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gdma_hal_enable_intr(hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, GDMA_LL_EVENT_RX_DONE, cbs->on_recv_done != NULL);
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portEXIT_CRITICAL(&pair->spinlock);
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@ -799,39 +799,43 @@ void gdma_default_rx_isr(void *args)
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gdma_hal_context_t *hal = &group->hal;
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int pair_id = pair->pair_id;
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bool need_yield = false;
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// clear pending interrupt event
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bool abnormal_eof = false;
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bool normal_eof = false;
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// clear pending interrupt event first
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uint32_t intr_status = gdma_hal_read_intr_status(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX);
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gdma_hal_clear_intr(hal, pair_id, GDMA_CHANNEL_DIRECTION_RX, intr_status);
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/* Call on_recv_done before eof callbacks to ensure a correct sequence */
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if ((intr_status & GDMA_LL_EVENT_RX_DONE) && rx_chan->cbs.on_recv_done) {
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/* Here we don't return an event data in this callback.
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* Because we can't get a determinant descriptor address
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* that just finished processing by DMA controller.
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* When the `rx_done` interrupt triggers, the finished descriptor should ideally
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* stored in `in_desc_bf1` register, however, as it takes a while to
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* get the `in_desc_bf1` in software, `in_desc_bf1` might have already refreshed,
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* Therefore, instead of returning an unreliable descriptor, we choose to return nothing.
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*/
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need_yield |= rx_chan->cbs.on_recv_done(&rx_chan->base, NULL, rx_chan->user_data);
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// prepare data for different events
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uint32_t eof_addr = 0;
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if (intr_status & GDMA_LL_EVENT_RX_SUC_EOF) {
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eof_addr = gdma_hal_get_eof_desc_addr(&group->hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, true);
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normal_eof = true;
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}
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if (intr_status & GDMA_LL_EVENT_RX_ERR_EOF) {
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eof_addr = gdma_hal_get_eof_desc_addr(&group->hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, false);
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abnormal_eof = true;
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}
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gdma_event_data_t edata = {
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.rx_eof_desc_addr = eof_addr,
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.flags = {
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.abnormal_eof = abnormal_eof,
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.normal_eof = normal_eof,
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}
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};
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if ((intr_status & GDMA_LL_EVENT_RX_DESC_ERROR) && rx_chan->cbs.on_descr_err) {
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// in the future, we may add more information about the error descriptor into the event data,
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// but for now, we just pass NULL
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need_yield |= rx_chan->cbs.on_descr_err(&rx_chan->base, NULL, rx_chan->user_data);
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}
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if ((intr_status & GDMA_LL_EVENT_RX_SUC_EOF) && rx_chan->cbs.on_recv_eof) {
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uint32_t eof_addr = gdma_hal_get_eof_desc_addr(&group->hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, true);
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gdma_event_data_t suc_eof_data = {
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.rx_eof_desc_addr = eof_addr,
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};
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need_yield |= rx_chan->cbs.on_recv_eof(&rx_chan->base, &suc_eof_data, rx_chan->user_data);
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// we expect the caller will do data process in the recv_done callback first, and handle the EOF event later
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if ((intr_status & GDMA_LL_EVENT_RX_DONE) && rx_chan->cbs.on_recv_done) {
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need_yield |= rx_chan->cbs.on_recv_done(&rx_chan->base, &edata, rx_chan->user_data);
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}
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if ((intr_status & GDMA_LL_EVENT_RX_ERR_EOF) && rx_chan->cbs.on_recv_eof) {
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uint32_t eof_addr = gdma_hal_get_eof_desc_addr(&group->hal, pair->pair_id, GDMA_CHANNEL_DIRECTION_RX, false);
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gdma_event_data_t err_eof_data = {
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.rx_eof_desc_addr = eof_addr,
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.flags.abnormal_eof = true,
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};
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need_yield |= rx_chan->cbs.on_recv_eof(&rx_chan->base, &err_eof_data, rx_chan->user_data);
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if ((intr_status & (GDMA_LL_EVENT_RX_SUC_EOF | GDMA_LL_EVENT_RX_ERR_EOF)) && rx_chan->cbs.on_recv_eof) {
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need_yield |= rx_chan->cbs.on_recv_eof(&rx_chan->base, &edata, rx_chan->user_data);
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}
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if (need_yield) {
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@ -855,6 +859,7 @@ void gdma_default_tx_isr(void *args)
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uint32_t eof_addr = gdma_hal_get_eof_desc_addr(hal, pair_id, GDMA_CHANNEL_DIRECTION_TX, true);
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gdma_event_data_t edata = {
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.tx_eof_desc_addr = eof_addr,
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.flags.normal_eof = true,
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};
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need_yield |= tx_chan->cbs.on_trans_eof(&tx_chan->base, &edata, tx_chan->user_data);
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}
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@ -55,16 +55,13 @@ typedef struct {
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*/
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typedef struct {
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union {
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intptr_t rx_eof_desc_addr; /*!< EOF descriptor address of RX channel */
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intptr_t tx_eof_desc_addr; /*!< EOF descriptor address of TX channel */
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intptr_t rx_eof_desc_addr; /*!< EOF descriptor address of RX channel (only valid for EOF event) */
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intptr_t tx_eof_desc_addr; /*!< EOF descriptor address of TX channel (only valid for EOF event) */
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};
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struct {
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uint32_t abnormal_eof: 1; /*!< 0: normal/success EOF;
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* 1: abnormal/error EOF,
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* it doesn't mean GDMA goes into an error condition,
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* but the other peripheral goes into an abnormal state.
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* For GDMA, it's still a valid EOF
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*/
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uint32_t abnormal_eof: 1; /*!< If set, means the current DMA block has an abnormal/error EOF flag being set.
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It doesn't mean GDMA goes into an error condition, but indicates peripheral (e.g. UHCI) goes into an abnormal state */
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uint32_t normal_eof: 1; /*!< If set, means the current DMA block has a normal/successful EOF flag being set */
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} flags;
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} gdma_event_data_t;
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