diff --git a/Kconfig b/Kconfig
index 4b6ec216f7..eb1ddb8216 100644
--- a/Kconfig
+++ b/Kconfig
@@ -31,11 +31,13 @@ mainmenu "Espressif IoT Development Framework Configuration"
 
     config IDF_TARGET_ESP32
         bool
-        default y if IDF_TARGET="esp32"
+        default "y" if IDF_TARGET="esp32"
+        default "n"
 
     config IDF_TARGET_ESP32S2BETA
         bool
-        default y if IDF_TARGET="esp32s2beta"
+        default "y" if IDF_TARGET="esp32s2beta"
+        default "n"
 
     menu "SDK tool configuration"
         config SDK_TOOLPREFIX
diff --git a/components/esp32/intr_alloc.c b/components/esp32/intr_alloc.c
index b74c4f9293..d40caebe6e 100644
--- a/components/esp32/intr_alloc.c
+++ b/components/esp32/intr_alloc.c
@@ -340,7 +340,7 @@ static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force
         ALCHLOG("....Unusable: reserved at runtime.");
         return false;
     }
-    
+
     //Ints can't be both shared and non-shared.
     assert(!((vd->flags&VECDESC_FL_SHARED)&&(vd->flags&VECDESC_FL_NONSHARED)));
     //check if interrupt already is in use by a non-shared interrupt
@@ -368,7 +368,7 @@ static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force
         ALCHLOG("....Unusable: already allocated");
         return false;
     }
-        
+
     return true;
 }
 
@@ -385,7 +385,7 @@ static int get_available_int(int flags, int cpu, int force, int source)
     vector_desc_t empty_vect_desc;
     memset(&empty_vect_desc, 0, sizeof(vector_desc_t));
 
-    
+
     //Level defaults to any low/med interrupt
     if (!(flags&ESP_INTR_FLAG_LEVELMASK)) flags|=ESP_INTR_FLAG_LOWMED;
 
@@ -410,13 +410,13 @@ static int get_available_int(int flags, int cpu, int force, int source)
         if (vd == NULL ) {
             //if existing vd not found, just check the default state for the intr.
             empty_vect_desc.intno = force;
-            vd = &empty_vect_desc; 
+            vd = &empty_vect_desc;
         }
         if ( is_vect_desc_usable(vd, flags, cpu, force) ) {
             best = vd->intno;
         } else {
             ALCHLOG("get_avalible_int: forced vd invalid.");
-        } 
+        }
         return best;
     }
 
@@ -433,12 +433,12 @@ static int get_available_int(int flags, int cpu, int force, int source)
         ALCHLOG("Int %d reserved %d level %d %s hasIsr %d",
             x, int_desc[x].cpuflags[cpu]==INTDESC_RESVD, int_desc[x].level,
             int_desc[x].type==INTTP_LEVEL?"LEVEL":"EDGE", int_has_handler(x, cpu));
-        
+
         if ( !is_vect_desc_usable(vd, flags, cpu, force) ) continue;
 
         if (flags&ESP_INTR_FLAG_SHARED) {
             //We're allocating a shared int.
-            
+
             //See if int already is used as a shared interrupt.
             if (vd->flags&VECDESC_FL_SHARED) {
                 //We can use this already-marked-as-shared interrupt. Count the already attached isrs in order to see
@@ -548,9 +548,12 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
     //Statusreg should have a mask
     if (intrstatusreg && !intrstatusmask) return ESP_ERR_INVALID_ARG;
     //If the ISR is marked to be IRAM-resident, the handler must not be in the cached region
+    //ToDo: if we are to allow placing interrupt handlers into the 0x400c0000—0x400c2000 region,
+    //we need to make sure the interrupt is connected to the CPU0.
+    //CPU1 does not have access to the RTC fast memory through this region.
     if ((flags&ESP_INTR_FLAG_IRAM) &&
-            (ptrdiff_t) handler >= 0x400C0000 &&
-            (ptrdiff_t) handler < 0x50000000 ) {
+            (ptrdiff_t) handler >= SOC_RTC_IRAM_HIGH &&
+            (ptrdiff_t) handler < SOC_RTC_DATA_LOW ) {
         return ESP_ERR_INVALID_ARG;
     }
 
diff --git a/components/esp32/test/test_spiram_cache_flush.c b/components/esp32/test/test_spiram_cache_flush.c
index 6e984be6ce..d0797a2871 100644
--- a/components/esp32/test/test_spiram_cache_flush.c
+++ b/components/esp32/test/test_spiram_cache_flush.c
@@ -61,8 +61,8 @@ TEST_CASE("Spiram cache flush on mmap", "[spiram]")
     mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
     mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
 #else
-    mem[0]=(void*)0x3f800000;
-    mem[1]=(void*)0x3f800000+TSTSZ;
+    mem[0]=(void*)SOC_EXTRAM_DATA_LOW;
+    mem[1]=(void*)SOC_EXTRAM_DATA_LOW+TSTSZ;
 #endif
     assert(mem[0]);
     assert(mem[1]);
@@ -105,8 +105,8 @@ TEST_CASE("Spiram cache flush on write/read", "[spiram]")
     mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
     mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
 #else
-    mem[0]=(void*)0x3f800000;
-    mem[1]=(void*)0x3f800000+TSTSZ;
+    mem[0]=(void*)SOC_EXTRAM_DATA_LOW;
+    mem[1]=(void*)SOC_EXTRAM_DATA_LOW+TSTSZ;
 #endif
     assert(mem[0]);
     assert(mem[1]);
@@ -148,7 +148,7 @@ IRAM_ATTR TEST_CASE("Spiram memcmp weirdness at 80MHz", "[spiram]") {
 #if USE_CAPS_ALLOC
     char *mem2=heap_caps_malloc(0x10000, MALLOC_CAP_SPIRAM);
 #else
-    char *mem2=(void*)0x3f800000;
+    char *mem2=(void*)SOC_EXTRAM_DATA_LOW;
 #endif
 
 #if !CONFIG_SPIRAM_SPEED_80M
diff --git a/components/esp_common/include/esp_system.h b/components/esp_common/include/esp_system.h
index c57502c211..bf3fcd9034 100644
--- a/components/esp_common/include/esp_system.h
+++ b/components/esp_common/include/esp_system.h
@@ -323,7 +323,8 @@ const char* esp_get_idf_version(void);
  * @brief Chip models
  */
 typedef enum {
-    CHIP_ESP32 = 1, //!< ESP32
+    CHIP_ESP32  = 1, //!< ESP32
+    CHIP_ESP32S2BETA = 2, //!< ESP32S2BETA
 } esp_chip_model_t;
 
 /* Chip feature flags, used in esp_chip_info_t */