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Merge branch 'refactor/add_namespace_intr_cpu_id' into 'master'

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refactor(intr): add namespace for intr_cpu_id_t

See merge request espressif/esp-idf!25725
This commit is contained in:
morris 2023-09-06 16:41:57 +08:00
commit 2e6015b39f
12 changed files with 69 additions and 48 deletions
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6
components/driver/spi/gpspi/spi_master.c
View File

@ -232,13 +232,13 @@ static esp_err_t spi_master_init_driver(spi_host_device_t host_id)
// interrupts are not allowed on SPI1 bus
if (host_id != SPI1_HOST) {
#if (SOC_CPU_CORES_NUM > 1) && (!CONFIG_FREERTOS_UNICORE)
if(bus_attr->bus_cfg.isr_cpu_id > INTR_CPU_ID_AUTO) {
SPI_CHECK(bus_attr->bus_cfg.isr_cpu_id <= INTR_CPU_ID_1, "invalid core id", ESP_ERR_INVALID_ARG);
if (bus_attr->bus_cfg.isr_cpu_id > ESP_INTR_CPU_AFFINITY_AUTO) {
SPI_CHECK(bus_attr->bus_cfg.isr_cpu_id <= ESP_INTR_CPU_AFFINITY_1, "invalid core id", ESP_ERR_INVALID_ARG);
spi_ipc_param_t ipc_arg = {
.spi_host = host,
.err = &err,
};
esp_ipc_call_blocking(INTR_CPU_CONVERT_ID(bus_attr->bus_cfg.isr_cpu_id), ipc_isr_reg_to_core, (void *) &ipc_arg);
esp_ipc_call_blocking(ESP_INTR_CPU_AFFINITY_TO_CORE_ID(bus_attr->bus_cfg.isr_cpu_id), ipc_isr_reg_to_core, (void *) &ipc_arg);
} else
#endif
{

8
components/driver/spi/gpspi/spi_slave.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -222,14 +222,14 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
}
#if (SOC_CPU_CORES_NUM > 1) && (!CONFIG_FREERTOS_UNICORE)
if(bus_config->isr_cpu_id > INTR_CPU_ID_AUTO) {
if (bus_config->isr_cpu_id > ESP_INTR_CPU_AFFINITY_AUTO) {
spihost[host]->intr_flags = bus_config->intr_flags;
SPI_CHECK(bus_config->isr_cpu_id <= INTR_CPU_ID_1, "invalid core id", ESP_ERR_INVALID_ARG);
SPI_CHECK(bus_config->isr_cpu_id <= ESP_INTR_CPU_AFFINITY_1, "invalid core id", ESP_ERR_INVALID_ARG);
spi_ipc_param_t ipc_args = {
.host = spihost[host],
.err = &err,
};
esp_ipc_call_blocking(INTR_CPU_CONVERT_ID(bus_config->isr_cpu_id), ipc_isr_reg_to_core, (void *)&ipc_args);
esp_ipc_call_blocking(ESP_INTR_CPU_AFFINITY_TO_CORE_ID(bus_config->isr_cpu_id), ipc_isr_reg_to_core, (void *)&ipc_args);
} else
#endif
{

4
components/driver/spi/include/driver/spi_common.h
View File

@ -11,7 +11,7 @@
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_ipc.h"
#include "intr_types.h"
#include "esp_intr_types.h"
#include "hal/spi_types.h"
#ifdef __cplusplus
@ -117,7 +117,7 @@ typedef struct {
int data7_io_num; ///< GPIO pin for spi data7 signal in octal mode, or -1 if not used.
int max_transfer_sz; ///< Maximum transfer size, in bytes. Defaults to 4092 if 0 when DMA enabled, or to `SOC_SPI_MAXIMUM_BUFFER_SIZE` if DMA is disabled.
uint32_t flags; ///< Abilities of bus to be checked by the driver. Or-ed value of ``SPICOMMON_BUSFLAG_*`` flags.
intr_cpu_id_t isr_cpu_id; ///< Select cpu core to register SPI ISR.
esp_intr_cpu_affinity_t isr_cpu_id; ///< Select cpu core to register SPI ISR.
int intr_flags; /**< Interrupt flag for the bus to set the priority, and IRAM attribute, see
* ``esp_intr_alloc.h``. Note that the EDGE, INTRDISABLED attribute are ignored
* by the driver. Note that if ESP_INTR_FLAG_IRAM is set, ALL the callbacks of

2
components/driver/test_apps/spi/master/main/test_spi_master.c
View File

@ -1644,7 +1644,7 @@ TEST_CASE("test_master_isr_pin_to_core","[spi]")
//-------------------------------------CPU1---------------------------------------
buscfg.isr_cpu_id = INTR_CPU_ID_1;
buscfg.isr_cpu_id = ESP_INTR_CPU_AFFINITY_1;
master_expect = 0;
for (int i = 0; i < TEST_ISR_CNT; i++) {

16
components/driver/test_apps/spi/slave/main/test_spi_slave.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -21,7 +21,6 @@
#include "esp_log.h"
#include "esp_rom_gpio.h"
#if (TEST_SPI_PERIPH_NUM >= 2)
//These will only be enabled on chips with 2 or more SPI peripherals
@ -267,7 +266,6 @@ TEST_CASE("test slave send unaligned", "[spi]")
#endif // #if (TEST_SPI_PERIPH_NUM >= 2)
#if (TEST_SPI_PERIPH_NUM == 1)
//These tests are for chips which only have 1 SPI controller
/********************************************************************************
@ -391,7 +389,6 @@ static void unaligned_test_slave(void)
TEST_CASE_MULTIPLE_DEVICES("SPI_Slave_Unaligned_Test", "[spi_ms][timeout=120]", unaligned_test_master, unaligned_test_slave);
#endif //#if (TEST_SPI_PERIPH_NUM == 1)
#if CONFIG_SPI_SLAVE_ISR_IN_IRAM
#define TEST_IRAM_TRANS_NUM 8
#define TEST_TRANS_LEN 120
@ -528,7 +525,6 @@ static IRAM_ATTR void test_slave_isr_iram(void)
TEST_CASE_MULTIPLE_DEVICES("SPI_Slave: Test_ISR_IRAM_disable_cache", "[spi_ms]", test_slave_iram_master_normal, test_slave_isr_iram);
static uint32_t isr_trans_cnt, isr_trans_test_fail;
static IRAM_ATTR void test_trans_in_isr_post_trans_cbk(spi_slave_transaction_t *curr_trans)
{
@ -600,7 +596,6 @@ static IRAM_ATTR void spi_slave_trans_in_isr(void)
}
TEST_CASE_MULTIPLE_DEVICES("SPI_Slave: Test_Queue_Trans_in_ISR", "[spi_ms]", test_slave_iram_master_normal, spi_slave_trans_in_isr);
uint32_t dummy_data[2] = {0x38383838, 0x5b5b5b5b};
spi_slave_transaction_t dummy_trans[2];
static uint32_t queue_reset_isr_trans_cnt, test_queue_reset_isr_fail;
@ -694,15 +689,15 @@ static IRAM_ATTR void spi_queue_reset_in_isr(void)
TEST_CASE_MULTIPLE_DEVICES("SPI_Slave: Test_Queue_Reset_in_ISR", "[spi_ms]", test_slave_iram_master_normal, spi_queue_reset_in_isr);
#endif // CONFIG_SPI_SLAVE_ISR_IN_IRAM
#if (SOC_CPU_CORES_NUM > 1) && (!CONFIG_FREERTOS_UNICORE)
#define TEST_ISR_CNT 100
static void test_slave_isr_core_setup_cbk(spi_slave_transaction_t *curr_trans){
static void test_slave_isr_core_setup_cbk(spi_slave_transaction_t *curr_trans)
{
*((int *)curr_trans->user) += esp_cpu_get_core_id();
}
TEST_CASE("test_slave_isr_pin_to_core","[spi]")
TEST_CASE("test_slave_isr_pin_to_core", "[spi]")
{
uint32_t slave_send;
uint32_t slave_recive;
@ -729,9 +724,8 @@ TEST_CASE("test_slave_isr_pin_to_core","[spi]")
// by default the esp_intr_alloc is called on ESP_MAIN_TASK_AFFINITY_CPU0 now
TEST_ASSERT_EQUAL_UINT32(0, slave_expect);
//-------------------------------------CPU1---------------------------------------
buscfg.isr_cpu_id = INTR_CPU_ID_1;
buscfg.isr_cpu_id = ESP_INTR_CPU_AFFINITY_1;
slave_expect = 0;
for (int i = 0; i < TEST_ISR_CNT; i++) {

12
components/esp_hw_support/include/esp_intr_alloc.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,6 +10,7 @@
#include <stdbool.h>
#include <stdio.h>
#include "esp_err.h"
#include "esp_intr_types.h"
#ifdef __cplusplus
extern "C" {
@ -79,15 +80,6 @@ extern "C" {
/** Disable interrupt by interrupt number */
#define ESP_INTR_DISABLE(inum) esp_intr_disable_source(inum)
/** Function prototype for interrupt handler function */
typedef void (*intr_handler_t)(void *arg);
/** Interrupt handler associated data structure */
typedef struct intr_handle_data_t intr_handle_data_t;
/** Handle to an interrupt handler */
typedef intr_handle_data_t *intr_handle_t ;
/**
* @brief Mark an interrupt as a shared interrupt
*

34
components/esp_hw_support/include/esp_intr_types.h Normal file
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@ -0,0 +1,34 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/** Function prototype for interrupt handler function */
typedef void (*intr_handler_t)(void *arg);
/** Handle to an interrupt handler */
typedef struct intr_handle_data_t *intr_handle_t;
/**
* @brief Interrupt CPU core affinity
*
* This type specify the CPU core that the peripheral interrupt is connected to.
*/
typedef enum {
ESP_INTR_CPU_AFFINITY_AUTO, ///< Install the peripheral interrupt to ANY CPU core, decided by on which CPU the interrupt allocator is running
ESP_INTR_CPU_AFFINITY_0, ///< Install the peripheral interrupt to CPU core 0
ESP_INTR_CPU_AFFINITY_1, ///< Install the peripheral interrupt to CPU core 1
} esp_intr_cpu_affinity_t;
/// Convert esp_intr_cpu_affinity_t to CPU core ID
#define ESP_INTR_CPU_AFFINITY_TO_CORE_ID(cpu_affinity) ((cpu_affinity) - 1)
#ifdef __cplusplus
}
#endif

22
components/esp_hw_support/include/intr_types.h
View File

@ -5,22 +5,20 @@
*/
#pragma once
#warning "This header is deprecated. Please use esp_intr_types.h instead"
#include "esp_intr_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Interrupt core ID type
*
* This type represents on which core your ISR is registered
*/
typedef enum {
INTR_CPU_ID_AUTO, ///< Register intr ISR to core automatically, this means the core on which you call `esp_intr_alloc`
INTR_CPU_ID_0, ///< Register intr ISR to core 0.
INTR_CPU_ID_1, ///< Register intr ISR to core 1.
} intr_cpu_id_t;
#define INTR_CPU_CONVERT_ID(cpu_id) ((cpu_id) - 1)
/// @brief legacy type compatibility
typedef esp_intr_cpu_affinity_t intr_cpu_id_t;
#define INTR_CPU_CONVERT_ID ESP_INTR_CPU_AFFINITY_TO_CORE_ID
#define INTR_CPU_ID_AUTO ESP_INTR_CPU_AFFINITY_AUTO
#define INTR_CPU_ID_0 ESP_INTR_CPU_AFFINITY_0
#define INTR_CPU_ID_1 ESP_INTR_CPU_AFFINITY_1
#ifdef __cplusplus
}

5
components/esp_hw_support/intr_alloc.c
View File

@ -83,10 +83,11 @@ struct vector_desc_t {
vector_desc_t *next;
};
struct intr_handle_data_t {
/** Interrupt handler associated data structure */
typedef struct intr_handle_data_t {
vector_desc_t *vector_desc;
shared_vector_desc_t *shared_vector_desc;
};
} intr_handle_data_t;
typedef struct non_shared_isr_arg_t non_shared_isr_arg_t;

1
docs/doxygen/Doxyfile
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@ -148,6 +148,7 @@ INPUT = \
$(PROJECT_PATH)/components/esp_hw_support/include/esp_ds.h \
$(PROJECT_PATH)/components/esp_hw_support/include/esp_hmac.h \
$(PROJECT_PATH)/components/esp_hw_support/include/esp_intr_alloc.h \
$(PROJECT_PATH)/components/esp_hw_support/include/esp_intr_types.h \
$(PROJECT_PATH)/components/esp_hw_support/include/esp_mac.h \
$(PROJECT_PATH)/components/esp_hw_support/include/esp_random.h \
$(PROJECT_PATH)/components/esp_hw_support/include/esp_sleep.h \

5
docs/en/api-reference/system/intr_alloc.rst
View File

@ -95,7 +95,7 @@ Several handlers can be assigned to a same source, given that all handlers are a
Sources attached to non-shared interrupt do not support this feature.
.. only:: not SOC_CPU_HAS_FLEXIBLE_INTC
By default, when ``ESP_INTR_FLAG_SHARED`` flag is specified, the interrupt allocator will allocate only Level 1 interrupts. Use ``ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED`` to also allow allocating shared interrupts at Level 2 and Level 3.
Though the framework supports this feature, you have to use it **very carefully**. There usually exist two ways to stop an interrupt from being triggered: **disable the source** or **mask peripheral interrupt status**. ESP-IDF only handles enabling and disabling of the source itself, leaving status and mask bits to be handled by users.
@ -103,7 +103,7 @@ Though the framework supports this feature, you have to use it **very carefully*
**Status bits shall either be masked before the handler responsible for it is disabled, either be masked and then properly handled in another enabled interrupt**.
.. note::
Leaving some status bits unhandled without masking them, while disabling the handlers for them, will cause the interrupt(s) to be triggered indefinitely, resulting therefore in a system crash.
Troubleshooting Interrupt Allocation
@ -150,4 +150,5 @@ If you have confirmed that the application is indeed running out of interrupts,
API Reference
-------------
.. include-build-file:: inc/esp_intr_types.inc
.. include-build-file:: inc/esp_intr_alloc.inc

2
examples/openthread/ot_rcp/main/esp_ot_config.h
View File

@ -60,7 +60,7 @@
.sclk_io_num = 0, \
.quadhd_io_num = -1, \
.quadwp_io_num = -1, \
.isr_cpu_id = INTR_CPU_ID_0, \
.isr_cpu_id = ESP_INTR_CPU_AFFINITY_AUTO, \
}, \
.slave_config = { \
.mode = 0, \