From 874a720286b78e866684129ce18a6c948c8fa7fe Mon Sep 17 00:00:00 2001
From: SalimTerryLi <lihangfan@espressif.com>
Date: Mon, 23 Aug 2021 14:03:23 +0800
Subject: [PATCH 1/2] soc/ll: workaround compiler bug that generate 8/16 bits
 inst instead of 32 bits one

update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
---
 .gitlab/ci/pre_check.yml                      |    9 +
 components/hal/esp32/include/hal/adc_ll.h     |   32 +-
 components/hal/esp32/include/hal/dac_ll.h     |   13 +-
 components/hal/esp32/include/hal/emac_ll.h    |    9 +-
 components/hal/esp32/include/hal/gpio_ll.h    |   16 +-
 components/hal/esp32/include/hal/i2c_ll.h     |    5 +-
 components/hal/esp32/include/hal/i2s_ll.h     |    8 +-
 components/hal/esp32/include/hal/ledc_ll.h    |    1 +
 components/hal/esp32/include/hal/mcpwm_ll.h   |   47 +-
 components/hal/esp32/include/hal/mwdt_ll.h    |    4 +-
 components/hal/esp32/include/hal/rmt_ll.h     |   23 +-
 components/hal/esp32/include/hal/rtc_io_ll.h  |    1 +
 components/hal/esp32/include/hal/rwdt_ll.h    |    1 +
 .../hal/esp32/include/hal/sigmadelta_ll.h     |    6 +-
 .../hal/esp32/include/hal/spi_flash_ll.h      |    4 +-
 components/hal/esp32/include/hal/spi_ll.h     |    7 +-
 components/hal/esp32/include/hal/timer_ll.h   |    6 +-
 .../hal/esp32/include/hal/touch_sensor_ll.h   |   25 +-
 components/hal/esp32/include/hal/twai_ll.h    |   21 +-
 components/hal/esp32/include/hal/uart_ll.h    |   27 +-
 components/hal/esp32c3/include/hal/adc_ll.h   |   15 +-
 components/hal/esp32c3/include/hal/gpio_ll.h  |    1 +
 .../hal/esp32c3/include/hal/gpspi_flash_ll.h  |    4 +-
 components/hal/esp32c3/include/hal/i2c_ll.h   |    9 +-
 components/hal/esp32c3/include/hal/i2s_ll.h   |    8 +-
 components/hal/esp32c3/include/hal/ledc_ll.h  |    1 +
 components/hal/esp32c3/include/hal/mwdt_ll.h  |    1 +
 components/hal/esp32c3/include/hal/rmt_ll.h   |   21 +-
 components/hal/esp32c3/include/hal/rwdt_ll.h  |    4 +-
 .../hal/esp32c3/include/hal/sigmadelta_ll.h   |    6 +-
 components/hal/esp32c3/include/hal/spi_ll.h   |    7 +-
 .../hal/esp32c3/include/hal/spimem_flash_ll.h |   11 +-
 components/hal/esp32c3/include/hal/timer_ll.h |    6 +-
 components/hal/esp32c3/include/hal/twai_ll.h  |   19 +-
 components/hal/esp32c3/include/hal/uart_ll.h  |   27 +-
 components/hal/esp32h2/include/hal/adc_ll.h   |   15 +-
 components/hal/esp32h2/include/hal/gpio_ll.h  |    1 +
 .../hal/esp32h2/include/hal/gpspi_flash_ll.h  |    4 +-
 components/hal/esp32h2/include/hal/i2c_ll.h   |    9 +-
 components/hal/esp32h2/include/hal/i2s_ll.h   |    8 +-
 components/hal/esp32h2/include/hal/ledc_ll.h  |    1 +
 components/hal/esp32h2/include/hal/mwdt_ll.h  |    1 +
 components/hal/esp32h2/include/hal/rmt_ll.h   |   21 +-
 components/hal/esp32h2/include/hal/rwdt_ll.h  |    4 +-
 .../hal/esp32h2/include/hal/sigmadelta_ll.h   |    6 +-
 components/hal/esp32h2/include/hal/spi_ll.h   |    7 +-
 .../hal/esp32h2/include/hal/spimem_flash_ll.h |   11 +-
 components/hal/esp32h2/include/hal/timer_ll.h |    6 +-
 components/hal/esp32h2/include/hal/twai_ll.h  |   20 +-
 components/hal/esp32h2/include/hal/uart_ll.h  |   27 +-
 .../esp32h2/include/hal/usb_serial_jtag_ll.h  |    6 +-
 components/hal/esp32s2/include/hal/adc_ll.h   |   30 +-
 components/hal/esp32s2/include/hal/dac_ll.h   |   13 +-
 .../hal/esp32s2/include/hal/dedic_gpio_ll.h   |    5 +-
 components/hal/esp32s2/include/hal/gpio_ll.h  |    1 +
 .../hal/esp32s2/include/hal/gpspi_flash_ll.h  |    4 +-
 components/hal/esp32s2/include/hal/i2c_ll.h   |    1 +
 components/hal/esp32s2/include/hal/i2s_ll.h   |    6 +-
 components/hal/esp32s2/include/hal/ledc_ll.h  |    1 +
 components/hal/esp32s2/include/hal/mwdt_ll.h  |    1 +
 components/hal/esp32s2/include/hal/rmt_ll.h   |   23 +-
 .../hal/esp32s2/include/hal/rtc_io_ll.h       |    2 +
 components/hal/esp32s2/include/hal/rwdt_ll.h  |    4 +-
 .../hal/esp32s2/include/hal/sigmadelta_ll.h   |    6 +-
 components/hal/esp32s2/include/hal/spi_ll.h   |    9 +-
 .../hal/esp32s2/include/hal/spimem_flash_ll.h |    9 +-
 components/hal/esp32s2/include/hal/timer_ll.h |    6 +-
 .../hal/esp32s2/include/hal/touch_sensor_ll.h |   26 +-
 components/hal/esp32s2/include/hal/twai_ll.h  |   19 +-
 components/hal/esp32s2/include/hal/uart_ll.h  |   23 +-
 components/hal/esp32s3/include/hal/adc_ll.h   |   26 +-
 components/hal/esp32s3/include/hal/gpio_ll.h  |    1 +
 .../hal/esp32s3/include/hal/gpspi_flash_ll.h  |    4 +-
 components/hal/esp32s3/include/hal/i2c_ll.h   |    9 +-
 components/hal/esp32s3/include/hal/i2s_ll.h   |    8 +-
 components/hal/esp32s3/include/hal/lcd_ll.h   |    7 +-
 components/hal/esp32s3/include/hal/ledc_ll.h  |    1 +
 components/hal/esp32s3/include/hal/mcpwm_ll.h |   36 +-
 components/hal/esp32s3/include/hal/mwdt_ll.h  |    4 +-
 components/hal/esp32s3/include/hal/rmt_ll.h   |   21 +-
 .../hal/esp32s3/include/hal/rtc_io_ll.h       |    1 +
 components/hal/esp32s3/include/hal/rwdt_ll.h  |    3 +-
 .../hal/esp32s3/include/hal/sigmadelta_ll.h   |    6 +-
 components/hal/esp32s3/include/hal/spi_ll.h   |    7 +-
 .../hal/esp32s3/include/hal/spimem_flash_ll.h |    7 +-
 components/hal/esp32s3/include/hal/timer_ll.h |    6 +-
 .../hal/esp32s3/include/hal/touch_sensor_ll.h |   18 +-
 components/hal/esp32s3/include/hal/twai_ll.h  |   19 +-
 components/hal/esp32s3/include/hal/uart_ll.h  |   28 +-
 .../hal/platform_port/include/hal/misc.h      |   20 +
 .../soc/esp32/include/soc/emac_dma_struct.h   |    2 +-
 .../soc/esp32/include/soc/emac_ext_struct.h   |    2 +-
 .../soc/esp32/include/soc/emac_mac_struct.h   |    2 +-
 components/soc/esp32/include/soc/i2c_struct.h |    4 +-
 .../soc/esp32/include/soc/pcnt_struct.h       |    2 +-
 components/soc/esp32/include/soc/rmt_struct.h |    6 +-
 .../soc/esp32/include/soc/sdmmc_struct.h      |   37 +-
 .../esp32/include/soc/timer_group_struct.h    |    2 +-
 .../soc/esp32/include/soc/twai_struct.h       |   87 +-
 .../soc/esp32/include/soc/uart_struct.h       |    4 +-
 .../soc/esp32/include/soc/uhci_struct.h       |    2 +-
 .../soc/esp32c3/include/soc/apb_ctrl_struct.h |    2 +-
 .../esp32c3/include/soc/apb_saradc_struct.h   |    2 +-
 .../soc/esp32c3/include/soc/efuse_struct.h    |    2 +-
 .../soc/esp32c3/include/soc/gdma_struct.h     |    2 +-
 .../soc/esp32c3/include/soc/gpio_sd_struct.h  |    2 +-
 .../soc/esp32c3/include/soc/gpio_struct.h     |    2 +-
 .../soc/esp32c3/include/soc/i2c_struct.h      |    2 +-
 .../soc/esp32c3/include/soc/i2s_struct.h      |    2 +-
 .../soc/esp32c3/include/soc/ledc_struct.h     |    2 +-
 .../soc/esp32c3/include/soc/rmt_struct.h      |    8 +-
 .../soc/esp32c3/include/soc/rtc_cntl_struct.h |    2 +-
 .../soc/esp32c3/include/soc/rtc_i2c_struct.h  |    2 +-
 .../esp32c3/include/soc/sensitive_struct.h    |    5 +-
 .../soc/esp32c3/include/soc/spi_mem_struct.h  |    2 +-
 .../soc/esp32c3/include/soc/spi_struct.h      |    2 +-
 .../soc/esp32c3/include/soc/syscon_struct.h   |    2 +-
 .../soc/esp32c3/include/soc/system_struct.h   |    2 +-
 .../soc/esp32c3/include/soc/systimer_struct.h |   10 +
 .../soc/esp32c3/include/soc/twai_struct.h     |   88 +-
 .../soc/esp32c3/include/soc/uart_struct.h     |    2 +-
 .../soc/esp32c3/include/soc/uhci_struct.h     |    2 +-
 .../include/soc/usb_serial_jtag_struct.h      |    2 +-
 .../soc/esp32h2/include/soc/apb_ctrl_struct.h |    2 +-
 .../esp32h2/include/soc/apb_saradc_struct.h   |    2 +-
 .../soc/esp32h2/include/soc/efuse_struct.h    |    2 +-
 .../soc/esp32h2/include/soc/gdma_struct.h     |    2 +-
 .../soc/esp32h2/include/soc/gpio_sd_struct.h  |    2 +-
 .../soc/esp32h2/include/soc/gpio_struct.h     |    2 +-
 .../soc/esp32h2/include/soc/i2c_struct.h      |    2 +-
 .../soc/esp32h2/include/soc/i2s_struct.h      |    2 +-
 .../soc/esp32h2/include/soc/ledc_struct.h     |    2 +-
 .../soc/esp32h2/include/soc/rmt_struct.h      |    8 +-
 .../soc/esp32h2/include/soc/rtc_cntl_struct.h |    2 +-
 .../soc/esp32h2/include/soc/rtc_i2c_struct.h  |    2 +-
 .../esp32h2/include/soc/sensitive_struct.h    |    2 +-
 .../soc/esp32h2/include/soc/spi_mem_struct.h  |    2 +-
 .../soc/esp32h2/include/soc/spi_struct.h      |    2 +-
 .../soc/esp32h2/include/soc/syscon_struct.h   |    2 +-
 .../soc/esp32h2/include/soc/system_struct.h   |    2 +-
 .../soc/esp32h2/include/soc/systimer_struct.h |   10 +
 .../soc/esp32h2/include/soc/twai_struct.h     |   88 +-
 .../soc/esp32h2/include/soc/uart_struct.h     |    2 +-
 .../soc/esp32h2/include/soc/uhci_struct.h     |    2 +-
 .../include/soc/usb_serial_jtag_struct.h      |    2 +-
 .../soc/esp32s2/include/soc/apb_ctrl_struct.h |    2 +-
 .../esp32s2/include/soc/apb_saradc_struct.h   |    2 +-
 .../soc/esp32s2/include/soc/cp_dma_struct.h   |    6 +
 .../esp32s2/include/soc/dedic_gpio_struct.h   |   12 +
 .../soc/esp32s2/include/soc/efuse_struct.h    |    2 +-
 .../soc/esp32s2/include/soc/gpio_sd_struct.h  |    2 +-
 .../soc/esp32s2/include/soc/gpio_struct.h     |    2 +-
 .../soc/esp32s2/include/soc/i2c_struct.h      |    2 +-
 .../soc/esp32s2/include/soc/i2s_struct.h      |    2 +-
 .../soc/esp32s2/include/soc/ledc_struct.h     |    2 +-
 .../soc/esp32s2/include/soc/rmt_struct.h      |    8 +-
 .../soc/esp32s2/include/soc/rtc_cntl_struct.h |    2 +-
 .../soc/esp32s2/include/soc/rtc_i2c_struct.h  |    2 +-
 .../soc/esp32s2/include/soc/rtc_io_struct.h   |    2 +-
 .../soc/esp32s2/include/soc/sens_struct.h     |    2 +-
 .../soc/esp32s2/include/soc/syscon_struct.h   |    2 +-
 .../soc/esp32s2/include/soc/systimer_struct.h |    4 +
 .../soc/esp32s2/include/soc/twai_struct.h     |   86 +-
 .../soc/esp32s2/include/soc/uart_struct.h     |    2 +-
 .../soc/esp32s2/include/soc/uhci_struct.h     |    2 +-
 .../soc/esp32s2/include/soc/usb_wrap_struct.h |    1 +
 .../soc/esp32s2/include/soc/usbh_struct.h     |    2 +-
 .../soc/esp32s3/include/soc/apb_ctrl_struct.h |    2 +-
 .../esp32s3/include/soc/apb_saradc_struct.h   |    2 +-
 .../esp32s3/include/soc/assist_debug_struct.h |    2 +-
 .../soc/esp32s3/include/soc/efuse_struct.h    |    2 +-
 .../soc/esp32s3/include/soc/extmem_struct.h   |    2 +-
 .../soc/esp32s3/include/soc/gdma_struct.h     |    2 +-
 .../soc/esp32s3/include/soc/gpio_sd_struct.h  |    2 +-
 .../soc/esp32s3/include/soc/gpio_struct.h     |    2 +-
 .../soc/esp32s3/include/soc/hinf_struct.h     |    2 +-
 .../soc/esp32s3/include/soc/host_struct.h     |    2 +-
 .../soc/esp32s3/include/soc/i2s_struct.h      |    2 +-
 .../include/soc/interrupt_core0_struct.h      |    2 +-
 .../include/soc/interrupt_core1_struct.h      |    2 +-
 .../esp32s3/include/soc/interrupt_struct.h    |    2 +-
 .../soc/esp32s3/include/soc/ledc_struct.h     |    2 +-
 .../esp32s3/include/soc/peri_backup_struct.h  |    2 +-
 .../soc/esp32s3/include/soc/rmt_struct.h      |    4 +-
 .../soc/esp32s3/include/soc/rtc_cntl_struct.h |    2 +-
 .../soc/esp32s3/include/soc/rtc_io_struct.h   |    2 +-
 .../soc/esp32s3/include/soc/sdmmc_struct.h    |   38 +-
 .../soc/esp32s3/include/soc/sens_struct.h     |    2 +-
 .../esp32s3/include/soc/sensitive_struct.h    |    2 +-
 components/soc/esp32s3/include/soc/slc_reg.h  | 1912 -----------------
 .../soc/esp32s3/include/soc/slc_struct.h      |  592 -----
 .../soc/esp32s3/include/soc/spi_mem_struct.h  |    2 +-
 .../soc/esp32s3/include/soc/spi_struct.h      |    2 +-
 .../soc/esp32s3/include/soc/syscon_struct.h   |    2 +-
 .../soc/esp32s3/include/soc/system_struct.h   |    2 +-
 .../soc/esp32s3/include/soc/systimer_struct.h |   11 +
 .../soc/esp32s3/include/soc/twai_struct.h     |   90 +-
 .../soc/esp32s3/include/soc/uhci_struct.h     |    2 +-
 .../include/soc/usb_serial_jtag_struct.h      |    2 +-
 .../soc/esp32s3/include/soc/usb_wrap_struct.h |    1 +
 .../soc/esp32s3/include/soc/usbh_struct.h     |    2 +-
 .../include/soc/world_controller_struct.h     |    2 +-
 .../soc/include/soc/sdio_slave_periph.h       |    3 +
 tools/ci/check_soc_struct_headers.py          |  420 ++++
 tools/ci/executable-list.txt                  |    1 +
 205 files changed, 1439 insertions(+), 3252 deletions(-)
 delete mode 100644 components/soc/esp32s3/include/soc/slc_reg.h
 delete mode 100644 components/soc/esp32s3/include/soc/slc_struct.h
 create mode 100755 tools/ci/check_soc_struct_headers.py

diff --git a/.gitlab/ci/pre_check.yml b/.gitlab/ci/pre_check.yml
index 3ddccfadca..676ef0a44b 100644
--- a/.gitlab/ci/pre_check.yml
+++ b/.gitlab/ci/pre_check.yml
@@ -113,6 +113,15 @@ check_public_headers:
   script:
     - python tools/ci/check_public_headers.py --jobs 4 --prefix xtensa-esp32-elf-
 
+check_soc_struct_headers:
+  extends:
+    - .pre_check_base_template
+    - .rules:build
+  tags:
+    - build
+  script:
+    - find ${IDF_PATH}/components/soc/*/include/soc/ -name "*_struct.h" -print0 | xargs -0 -n1 ./tools/ci/check_soc_struct_headers.py
+
 check_esp_err_to_name:
   extends:
     - .pre_check_base_template
diff --git a/components/hal/esp32/include/hal/adc_ll.h b/components/hal/esp32/include/hal/adc_ll.h
index 587d7e7a34..1b5969ac43 100644
--- a/components/hal/esp32/include/hal/adc_ll.h
+++ b/components/hal/esp32/include/hal/adc_ll.h
@@ -3,7 +3,11 @@
 #include "soc/adc_periph.h"
 #include "hal/adc_types.h"
 #include "soc/rtc_io_struct.h"
+#include "soc/sens_struct.h"
+#include "soc/syscon_struct.h"
+#include "soc/rtc_cntl_struct.h"
 #include <stdbool.h>
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -52,11 +56,11 @@ typedef enum {
 static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
 {
     // Internal FSM reset wait time
-    SYSCON.saradc_fsm.rstb_wait = rst_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, rstb_wait, rst_wait);
     // Internal FSM start wait time
-    SYSCON.saradc_fsm.start_wait = start_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, start_wait, start_wait);
     // Internal FSM standby wait time
-    SYSCON.saradc_fsm.standby_wait = standby_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, standby_wait, standby_wait);
 }
 
 /**
@@ -67,7 +71,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
  */
 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 {
-    SYSCON.saradc_fsm.sample_cycle = sample_cycle;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, sample_cycle, sample_cycle);
 }
 
 /**
@@ -78,7 +82,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from APB clk, e.g. 80 / 2 = 40Mhz, */
-    SYSCON.saradc_ctrl.sar_clk_div = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl, sar_clk_div, div);
 }
 
 /**
@@ -99,7 +103,7 @@ static inline void adc_ll_digi_set_output_format(adc_digi_output_format_t format
  */
 static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
 {
-    SYSCON.saradc_ctrl2.max_meas_num = meas_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl2, max_meas_num, meas_num);
 }
 
 /**
@@ -320,7 +324,7 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
 static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
 {
     if (adc_n == ADC_NUM_1) {
-        while (SENS.sar_slave_addr1.meas_status != 0);
+        while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {}
         SENS.sar_meas_start1.meas1_start_sar = 0;
         SENS.sar_meas_start1.meas1_start_sar = 1;
     } else { // adc_n == ADC_NUM_2
@@ -359,9 +363,9 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
 {
     int ret_val = 0;
     if (adc_n == ADC_NUM_1) {
-        ret_val = SENS.sar_meas_start1.meas1_data_sar;
+        ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start1, meas1_data_sar);
     } else { // adc_n == ADC_NUM_2
-        ret_val = SENS.sar_meas_start2.meas2_data_sar;
+        ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start2, meas2_data_sar);
     }
     return ret_val;
 }
@@ -444,9 +448,9 @@ static inline adc_ll_power_t adc_ll_get_power_manage(void)
 static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
 {
     if (adc_n == ADC_NUM_1) {
-        SENS.sar_read_ctrl.sar1_clk_div = div;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div);
     } else { // adc_n == ADC_NUM_2
-        SENS.sar_read_ctrl2.sar2_clk_div = div;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div);
     }
 }
 
@@ -563,9 +567,9 @@ static inline void adc_ll_amp_disable(void)
     SENS.sar_meas_ctrl.amp_rst_fb_fsm = 0;
     SENS.sar_meas_ctrl.amp_short_ref_fsm = 0;
     SENS.sar_meas_ctrl.amp_short_ref_gnd_fsm = 0;
-    SENS.sar_meas_wait1.sar_amp_wait1 = 1;
-    SENS.sar_meas_wait1.sar_amp_wait2 = 1;
-    SENS.sar_meas_wait2.sar_amp_wait3 = 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait1, 1);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait2, 1);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait2, sar_amp_wait3, 1);
 }
 
 /*---------------------------------------------------------------
diff --git a/components/hal/esp32/include/hal/dac_ll.h b/components/hal/esp32/include/hal/dac_ll.h
index 5ea4da8978..ec1c20c4fb 100644
--- a/components/hal/esp32/include/hal/dac_ll.h
+++ b/components/hal/esp32/include/hal/dac_ll.h
@@ -21,7 +21,10 @@
 #pragma once
 
 #include <stdlib.h>
+#include "hal/misc.h"
 #include "soc/dac_periph.h"
+#include "soc/rtc_io_struct.h"
+#include "soc/sens_struct.h"
 #include "hal/dac_types.h"
 
 #ifdef __cplusplus
@@ -62,10 +65,10 @@ static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t val
 {
     if (channel == DAC_CHANNEL_1) {
         SENS.sar_dac_ctrl2.dac_cw_en1 = 0;
-        RTCIO.pad_dac[channel].dac = value;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
     } else if (channel == DAC_CHANNEL_2) {
         SENS.sar_dac_ctrl2.dac_cw_en2 = 0;
-        RTCIO.pad_dac[channel].dac = value;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
     }
 }
 
@@ -124,7 +127,7 @@ static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable)
 static inline void dac_ll_cw_set_freq(uint32_t freq)
 {
     uint32_t sw_freq = freq * 0xFFFF / RTC_FAST_CLK_FREQ_APPROX;
-    SENS.sar_dac_ctrl1.sw_fstep = (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq);
 }
 
 /**
@@ -171,12 +174,12 @@ static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset)
         if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_CW_PHASE_180) {
             offset = 0 - offset;
         }
-        SENS.sar_dac_ctrl2.dac_dc1 = offset ? offset : (-128 - offset);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset ? offset : (-128 - offset));
     } else if (channel == DAC_CHANNEL_2) {
         if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_CW_PHASE_180) {
             offset = 0 - offset;
         }
-        SENS.sar_dac_ctrl2.dac_dc2 = offset ? offset : (-128 - offset);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset ? offset : (-128 - offset));
     }
 }
 
diff --git a/components/hal/esp32/include/hal/emac_ll.h b/components/hal/esp32/include/hal/emac_ll.h
index 36477e36f5..dff803b5a9 100644
--- a/components/hal/esp32/include/hal/emac_ll.h
+++ b/components/hal/esp32/include/hal/emac_ll.h
@@ -23,6 +23,7 @@
 #pragma once
 
 #include <stdint.h>
+#include "hal/misc.h"
 #include "hal/eth_types.h"
 #include "soc/emac_dma_struct.h"
 #include "soc/emac_mac_struct.h"
@@ -310,7 +311,7 @@ static inline void emac_ll_promiscuous_mode_enable(emac_mac_dev_t *mac_regs, boo
 /* gmacfc */
 static inline void emac_ll_set_pause_time(emac_mac_dev_t *mac_regs, uint32_t time)
 {
-    mac_regs->gmacfc.pause_time = time;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mac_regs->gmacfc, pause_time, time);
 }
 
 static inline void emac_ll_zero_quanta_pause_enable(emac_mac_dev_t *mac_regs, bool enable)
@@ -346,18 +347,18 @@ static inline void emac_ll_clear(emac_mac_dev_t *mac_regs)
 /* emacmiidata */
 static inline void emac_ll_set_phy_data(emac_mac_dev_t *mac_regs, uint32_t data)
 {
-    mac_regs->emacmiidata.mii_data = data;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mac_regs->emacmiidata, mii_data, data);
 }
 
 static inline uint32_t emac_ll_get_phy_data(emac_mac_dev_t *mac_regs)
 {
-    return mac_regs->emacmiidata.mii_data;
+    return HAL_FORCE_READ_U32_REG_FIELD(mac_regs->emacmiidata, mii_data);
 }
 
 /* emacaddr0 */
 static inline void emac_ll_set_addr(emac_mac_dev_t *mac_regs, const uint8_t *addr)
 {
-    mac_regs->emacaddr0high.address0_hi = (addr[5] << 8) | addr[4];
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mac_regs->emacaddr0high, address0_hi, (addr[5] << 8) | addr[4]);
     mac_regs->emacaddr0low = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | (addr[0]);
 }
 /*************** End of mac regs operation *********************/
diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h
index 8c1acb3a1c..f5ac5909d5 100644
--- a/components/hal/esp32/include/hal/gpio_ll.h
+++ b/components/hal/esp32/include/hal/gpio_ll.h
@@ -25,9 +25,11 @@
 #include <stdbool.h>
 #include "soc/soc.h"
 #include "soc/gpio_periph.h"
+#include "soc/gpio_struct.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/rtc_io_reg.h"
 #include "hal/gpio_types.h"
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -245,7 +247,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
   */
 static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
-    *status = (core_id == 0) ? hw->pcpu_int1.intr : hw->acpu_int1.intr;
+    *status = (core_id == 0) ? HAL_FORCE_READ_U32_REG_FIELD(hw->pcpu_int1, intr) : HAL_FORCE_READ_U32_REG_FIELD(hw->pcpu_int1, intr);
 }
 
 /**
@@ -267,7 +269,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
   */
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
-    hw->status1_w1tc.intr_st = mask;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->status1_w1tc, intr_st, mask);
 }
 
 /**
@@ -330,7 +332,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
     if (gpio_num < 32) {
         hw->enable_w1tc = (0x1 << gpio_num);
     } else {
-        hw->enable1_w1tc.data = (0x1 << (gpio_num - 32));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->enable1_w1tc, data, (0x1 << (gpio_num - 32)));
     }
 
     // Ensure no other output signal is routed via GPIO matrix to this pin
@@ -349,7 +351,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
     if (gpio_num < 32) {
         hw->enable_w1ts = (0x1 << gpio_num);
     } else {
-        hw->enable1_w1ts.data = (0x1 << (gpio_num - 32));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->enable1_w1ts, data, (0x1 << (gpio_num - 32)));
     }
 }
 
@@ -432,13 +434,13 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32
         if (gpio_num < 32) {
             hw->out_w1ts = (1 << gpio_num);
         } else {
-            hw->out1_w1ts.data = (1 << (gpio_num - 32));
+            HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1ts, data, (1 << (gpio_num - 32)));
         }
     } else {
         if (gpio_num < 32) {
             hw->out_w1tc = (1 << gpio_num);
         } else {
-            hw->out1_w1tc.data = (1 << (gpio_num - 32));
+            HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1tc, data, (1 << (gpio_num - 32)));
         }
     }
 }
@@ -460,7 +462,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
     if (gpio_num < 32) {
         return (hw->in >> gpio_num) & 0x1;
     } else {
-        return (hw->in1.data >> (gpio_num - 32)) & 0x1;
+        return (HAL_FORCE_READ_U32_REG_FIELD(hw->in1, data) >> (gpio_num - 32)) & 0x1;
     }
 }
 
diff --git a/components/hal/esp32/include/hal/i2c_ll.h b/components/hal/esp32/include/hal/i2c_ll.h
index 550c1b76d2..650dbbaa04 100644
--- a/components/hal/esp32/include/hal/i2c_ll.h
+++ b/components/hal/esp32/include/hal/i2c_ll.h
@@ -15,7 +15,10 @@
 // The LL layer for I2C register operations
 
 #pragma once
+
+#include "hal/misc.h"
 #include "soc/i2c_periph.h"
+#include "soc/i2c_struct.h"
 #include "hal/i2c_types.h"
 
 #ifdef __cplusplus
@@ -558,7 +561,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for(int i = 0; i < len; i++) {
-        ptr[i] = hw->fifo_data.data;
+        ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->fifo_data, data);
     }
 }
 
diff --git a/components/hal/esp32/include/hal/i2s_ll.h b/components/hal/esp32/include/hal/i2s_ll.h
index 0633030925..159446b41d 100644
--- a/components/hal/esp32/include/hal/i2s_ll.h
+++ b/components/hal/esp32/include/hal/i2s_ll.h
@@ -23,7 +23,9 @@
 #pragma once
 
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/i2s_periph.h"
+#include "soc/i2s_struct.h"
 #include "hal/i2s_types.h"
 
 #ifdef __cplusplus
@@ -272,7 +274,7 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  */
 static inline void i2s_ll_tx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
 {
-    hw->clkm_conf.clkm_div_num = set->mclk_div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, set->mclk_div);
     hw->clkm_conf.clkm_div_b = set->b;
     hw->clkm_conf.clkm_div_a = set->a;
 }
@@ -296,7 +298,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  */
 static inline void i2s_ll_rx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
 {
-    hw->clkm_conf.clkm_div_num = set->mclk_div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, set->mclk_div);
     hw->clkm_conf.clkm_div_b = set->b;
     hw->clkm_conf.clkm_div_a = set->a;
 }
@@ -775,7 +777,7 @@ static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm_ena)
  */
 static inline void i2s_ll_tx_set_pdm_prescale(i2s_dev_t *hw, bool prescale)
 {
-    hw->pdm_conf.tx_prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->pdm_conf, tx_prescale, prescale);
 }
 
 /**
diff --git a/components/hal/esp32/include/hal/ledc_ll.h b/components/hal/esp32/include/hal/ledc_ll.h
index f7331872b6..1682c7c410 100644
--- a/components/hal/esp32/include/hal/ledc_ll.h
+++ b/components/hal/esp32/include/hal/ledc_ll.h
@@ -19,6 +19,7 @@
 
 #include "hal/ledc_types.h"
 #include "soc/ledc_periph.h"
+#include "soc/ledc_struct.h"
 
 #define LEDC_LL_GET_HW() &LEDC
 
diff --git a/components/hal/esp32/include/hal/mcpwm_ll.h b/components/hal/esp32/include/hal/mcpwm_ll.h
index 2fff763661..02b667341c 100644
--- a/components/hal/esp32/include/hal/mcpwm_ll.h
+++ b/components/hal/esp32/include/hal/mcpwm_ll.h
@@ -23,6 +23,7 @@
 #pragma once
 
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/soc_caps.h"
 #include "soc/mcpwm_struct.h"
 #include "hal/mcpwm_types.h"
@@ -44,17 +45,12 @@ extern "C" {
 // Set/Get group clock: PWM_clk = CLK_160M / (prescale + 1)
 static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int pre_scale)
 {
-    // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8bit instruction (e.g. s8i, which is not allowed to access a register)
-    // We take care of the "read-modify-write" procedure by ourselves.
-    mcpwm_clk_cfg_reg_t clkcfg = mcpwm->clk_cfg;
-    clkcfg.clk_prescale = pre_scale - 1;
-    mcpwm->clk_cfg = clkcfg;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->clk_cfg, clk_prescale, pre_scale - 1);
 }
 
 static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm)
 {
-    mcpwm_clk_cfg_reg_t clkcfg = mcpwm->clk_cfg;
-    return clkcfg.clk_prescale + 1;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->clk_cfg, clk_prescale) + 1;
 }
 
 static inline void mcpwm_ll_group_enable_shadow_mode(mcpwm_dev_t *mcpwm)
@@ -272,25 +268,20 @@ static inline void mcpwm_ll_intr_enable_capture(mcpwm_dev_t *mcpwm, uint32_t cap
 
 static inline void mcpwm_ll_timer_set_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id, uint32_t prescale)
 {
-    // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8bit instruction (e.g. s8i, which is not allowed to access a register)
-    // We take care of the "read-modify-write" procedure by ourselves.
-    mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0;
-    cfg0.timer_prescale = prescale - 1;
-    mcpwm->timer[timer_id].timer_cfg0 = cfg0;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_prescale, prescale - 1);
 }
 
 static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id)
 {
-    mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0;
-    return cfg0.timer_prescale + 1;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_prescale) + 1;
 }
 
 static inline void mcpwm_ll_timer_set_peak(mcpwm_dev_t *mcpwm, int timer_id, uint32_t peak, bool symmetric)
 {
     if (!symmetric) { // in asymmetric mode, period = [0,peak-1]
-        mcpwm->timer[timer_id].timer_cfg0.timer_period = peak - 1;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period, peak - 1);
     } else { // in symmetric mode, period = [0,peak-1] + [peak,1]
-        mcpwm->timer[timer_id].timer_cfg0.timer_period = peak;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period, peak);
     }
 }
 
@@ -298,10 +289,10 @@ static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id,
 {
     // asymmetric mode
     if (!symmetric) {
-        return mcpwm->timer[timer_id].timer_cfg0.timer_period + 1;
+        return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + 1;
     }
     // symmetric mode
-    return mcpwm->timer[timer_id].timer_cfg0.timer_period;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period);
 }
 
 static inline void mcpwm_ll_timer_update_period_at_once(mcpwm_dev_t *mcpwm, int timer_id)
@@ -385,7 +376,7 @@ static inline void mcpwm_ll_timer_set_execute_command(mcpwm_dev_t *mcpwm, int ti
 
 static inline uint32_t mcpwm_ll_timer_get_count_value(mcpwm_dev_t *mcpwm, int timer_id)
 {
-    return mcpwm->timer[timer_id].timer_status.timer_value;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_status, timer_value);
 }
 
 static inline mcpwm_timer_direction_t mcpwm_ll_timer_get_count_direction(mcpwm_dev_t *mcpwm, int timer_id)
@@ -428,7 +419,7 @@ static inline void mcpwm_ll_timer_trigger_soft_sync(mcpwm_dev_t *mcpwm, int time
 
 static inline void mcpwm_ll_timer_set_sync_phase_value(mcpwm_dev_t *mcpwm, int timer_id, uint32_t phase_value)
 {
-    mcpwm->timer[timer_id].timer_sync.timer_phase = phase_value;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_sync, timer_phase, phase_value);
 }
 
 static inline void mcpwm_ll_timer_set_sync_phase_direction(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_direction_t direction)
@@ -515,12 +506,12 @@ static inline void mcpwm_ll_operator_enable_update_compare_on_sync(mcpwm_dev_t *
 
 static inline void mcpwm_ll_operator_set_compare_value(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, uint32_t compare_value)
 {
-    mcpwm->operator[operator_id].timestamp[compare_id].gen = compare_value;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operator[operator_id].timestamp[compare_id], gen, compare_value);
 }
 
 static inline uint32_t mcpwm_ll_operator_get_compare_value(mcpwm_dev_t *mcpwm, int operator_id, int compare_id)
 {
-    return mcpwm->operator[operator_id].timestamp[compare_id].gen;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->operator[operator_id].timestamp[compare_id], gen);
 }
 
 static inline void mcpwm_ll_operator_update_action_at_once(mcpwm_dev_t *mcpwm, int operator_id)
@@ -719,22 +710,22 @@ static inline uint32_t mcpwm_ll_deadtime_get_switch_topology(mcpwm_dev_t *mcpwm,
 
 static inline void mcpwm_ll_deadtime_set_falling_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t fed)
 {
-    mcpwm->operator[operator_id].dt_fed_cfg.dt_fed = fed - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operator[operator_id].dt_fed_cfg, dt_fed, fed - 1);
 }
 
 static inline uint32_t mcpwm_ll_deadtime_get_falling_delay(mcpwm_dev_t *mcpwm, int operator_id)
 {
-    return mcpwm->operator[operator_id].dt_fed_cfg.dt_fed + 1;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->operator[operator_id].dt_fed_cfg, dt_fed) + 1;
 }
 
 static inline void mcpwm_ll_deadtime_set_rising_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t red)
 {
-    mcpwm->operator[operator_id].dt_red_cfg.dt_red = red - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operator[operator_id].dt_red_cfg, dt_red, red - 1);
 }
 
 static inline uint32_t mcpwm_ll_deadtime_get_rising_delay(mcpwm_dev_t *mcpwm, int operator_id)
 {
-    return mcpwm->operator[operator_id].dt_red_cfg.dt_red + 1;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->operator[operator_id].dt_red_cfg, dt_red) + 1;
 }
 
 static inline void mcpwm_ll_deadtime_update_delay_at_once(mcpwm_dev_t *mcpwm, int operator_id)
@@ -1006,12 +997,12 @@ static inline bool mcpwm_ll_capture_is_negedge(mcpwm_dev_t *mcpwm, int channel)
 
 static inline void mcpwm_ll_capture_set_prescale(mcpwm_dev_t *mcpwm, int channel, uint32_t prescale)
 {
-    mcpwm->cap_chn_cfg[channel].capn_prescale = prescale - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->cap_chn_cfg[channel], capn_prescale, prescale - 1);
 }
 
 static inline uint32_t mcpwm_ll_capture_get_prescale(mcpwm_dev_t *mcpwm, int channel)
 {
-    return mcpwm->cap_chn_cfg[channel].capn_prescale + 1;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->cap_chn_cfg[channel], capn_prescale) + 1;
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32/include/hal/mwdt_ll.h b/components/hal/esp32/include/hal/mwdt_ll.h
index 9a981c6855..267f15ef2c 100644
--- a/components/hal/esp32/include/hal/mwdt_ll.h
+++ b/components/hal/esp32/include/hal/mwdt_ll.h
@@ -23,7 +23,9 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
 #include "hal/wdt_types.h"
 #include "esp_attr.h"
 
@@ -201,7 +203,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t* hw, bool enable)
  */
 FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
 {
-    hw->wdt_config1.clk_prescale = prescaler;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config1, clk_prescale, prescaler);
 }
 
 /**
diff --git a/components/hal/esp32/include/hal/rmt_ll.h b/components/hal/esp32/include/hal/rmt_ll.h
index edd4f27912..dfd8199d5b 100644
--- a/components/hal/esp32/include/hal/rmt_ll.h
+++ b/components/hal/esp32/include/hal/rmt_ll.h
@@ -15,6 +15,7 @@
 
 #include <stdbool.h>
 #include <stddef.h>
+#include "hal/misc.h"
 #include "soc/rmt_struct.h"
 
 #ifdef __cplusplus
@@ -119,23 +120,23 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel
 
 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->conf_ch[channel].conf0.div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
 }
 
 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->conf_ch[channel].conf0.div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
 }
 
 static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    uint32_t div = dev->conf_ch[channel].conf0.div_cnt;
+    uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
     return div == 0 ? 256 : div;
 }
 
 static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    uint32_t div = dev->conf_ch[channel].conf0.div_cnt;
+    uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
     return div == 0 ? 256 : div;
 }
 
@@ -146,12 +147,12 @@ static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, b
 
 static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->conf_ch[channel].conf0.idle_thres = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres, thres);
 }
 
 static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->conf_ch[channel].conf0.idle_thres;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres);
 }
 
 static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
@@ -186,7 +187,7 @@ static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, boo
 
 static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->conf_ch[channel].conf1.rx_filter_thres = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres, thres);
 }
 
 static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -324,14 +325,14 @@ static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
 
 static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
 {
-    dev->carrier_duty_ch[channel].high = high_ticks;
-    dev->carrier_duty_ch[channel].low = low_ticks;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], high, high_ticks);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], low, low_ticks);
 }
 
 static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->carrier_duty_ch[channel].high;
-    *low_ticks = dev->carrier_duty_ch[channel].low;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], high);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], low);
 }
 
 static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
diff --git a/components/hal/esp32/include/hal/rtc_io_ll.h b/components/hal/esp32/include/hal/rtc_io_ll.h
index 3e5a1af8ff..f96452532e 100644
--- a/components/hal/esp32/include/hal/rtc_io_ll.h
+++ b/components/hal/esp32/include/hal/rtc_io_ll.h
@@ -22,6 +22,7 @@
 
 #include <stdlib.h>
 #include "soc/rtc_io_periph.h"
+#include "soc/rtc_io_struct.h"
 #include "hal/rtc_io_types.h"
 #include "hal/gpio_types.h"
 
diff --git a/components/hal/esp32/include/hal/rwdt_ll.h b/components/hal/esp32/include/hal/rwdt_ll.h
index c1d2d60607..e409eeaa8b 100644
--- a/components/hal/esp32/include/hal/rwdt_ll.h
+++ b/components/hal/esp32/include/hal/rwdt_ll.h
@@ -25,6 +25,7 @@ extern "C" {
 #include <stdbool.h>
 #include "hal/wdt_types.h"
 #include "soc/rtc_cntl_periph.h"
+#include "soc/rtc_cntl_struct.h"
 #include "esp_attr.h"
 
 //Type check wdt_stage_action_t
diff --git a/components/hal/esp32/include/hal/sigmadelta_ll.h b/components/hal/esp32/include/hal/sigmadelta_ll.h
index 929546fe0c..9e151871d2 100644
--- a/components/hal/esp32/include/hal/sigmadelta_ll.h
+++ b/components/hal/esp32/include/hal/sigmadelta_ll.h
@@ -22,7 +22,9 @@
 #pragma once
 
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/sigmadelta_periph.h"
+#include "soc/gpio_sd_struct.h"
 #include "hal/sigmadelta_types.h"
 
 #ifdef __cplusplus
@@ -53,7 +55,7 @@ static inline void sigmadelta_ll_set_en(gpio_sd_dev_t *hw, bool en)
  */
 static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, int8_t duty)
 {
-    hw->channel[channel].duty = duty;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)duty);
 }
 
 /**
@@ -65,7 +67,7 @@ static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_
  */
 static inline void sigmadelta_ll_set_prescale(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, uint8_t prescale)
 {
-    hw->channel[channel].prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale);
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32/include/hal/spi_flash_ll.h b/components/hal/esp32/include/hal/spi_flash_ll.h
index 7c0862eddc..3f18774a29 100644
--- a/components/hal/esp32/include/hal/spi_flash_ll.h
+++ b/components/hal/esp32/include/hal/spi_flash_ll.h
@@ -24,11 +24,13 @@
 
 #include <stdlib.h>
 #include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
 #include <sys/param.h> // For MIN/MAX
 #include <stdbool.h>
 #include <string.h>
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -393,7 +395,7 @@ static inline void spi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void spi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
-    dev->user1.usr_dummy_cyclelen = dummy_n - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
 }
 
 static inline void spi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h
index d9b520e473..89b4dedae3 100644
--- a/components/hal/esp32/include/hal/spi_ll.h
+++ b/components/hal/esp32/include/hal/spi_ll.h
@@ -27,6 +27,7 @@
 #include "esp_types.h"
 #include "esp32/rom/lldesc.h"
 #include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
 #include "hal/misc.h"
 #include "hal/spi_types.h"
 #include "hal/assert.h"
@@ -700,7 +701,7 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
-    hw->user1.usr_dummy_cyclelen = dummy_n - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
 }
 
 /**
@@ -858,13 +859,13 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 {
     if (lsbfirst) {
         // The output command start from bit0 to bit 15, kept as is.
-        hw->user2.usr_command_value = cmd;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd);
     } else {
         /* Output command will be sent from bit 7 to 0 of command_value, and
          * then bit 15 to 8 of the same register field. Shift and swap to send
          * more straightly.
          */
-        hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen));
 
     }
 }
diff --git a/components/hal/esp32/include/hal/timer_ll.h b/components/hal/esp32/include/hal/timer_ll.h
index f9efc82d22..35ce7d1025 100644
--- a/components/hal/esp32/include/hal/timer_ll.h
+++ b/components/hal/esp32/include/hal/timer_ll.h
@@ -22,9 +22,11 @@ extern "C" {
 #endif
 
 #include <stdlib.h>
+#include "hal/misc.h"
 #include "hal/assert.h"
 #include "hal/timer_types.h"
 #include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
 
 _Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
 _Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
@@ -50,7 +52,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
     }
     int timer_en = hw->hw_timer[timer_num].config.enable;
     hw->hw_timer[timer_num].config.enable = 0;
-    hw->hw_timer[timer_num].config.divider = divider;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider, divider);
     hw->hw_timer[timer_num].config.enable = timer_en;
 }
 
@@ -65,7 +67,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
  */
 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
 {
-    uint32_t d = hw->hw_timer[timer_num].config.divider;
+    uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider);
     if (d == 0) {
         d = 65536;
     } else if (d == 1) {
diff --git a/components/hal/esp32/include/hal/touch_sensor_ll.h b/components/hal/esp32/include/hal/touch_sensor_ll.h
index 5642d28cc2..07f17d4b65 100644
--- a/components/hal/esp32/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32/include/hal/touch_sensor_ll.h
@@ -24,7 +24,11 @@
 
 #include <stdlib.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/touch_sensor_periph.h"
+#include "soc/sens_struct.h"
+#include "soc/rtc_io_struct.h"
+#include "soc/rtc_cntl_struct.h"
 #include "hal/touch_sensor_types.h"
 
 
@@ -60,9 +64,9 @@ static inline touch_pad_t touch_ll_num_wrap(touch_pad_t touch_num)
 static inline void touch_ll_set_meas_time(uint16_t meas_time)
 {
     //touch sensor measure time= meas_cycle / 8Mhz
-    SENS.sar_touch_ctrl1.touch_meas_delay = meas_time;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_meas_delay, meas_time);
     //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
-    SENS.sar_touch_ctrl1.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_xpd_wait, SOC_TOUCH_PAD_MEASURE_WAIT_MAX);
 }
 
 /**
@@ -72,7 +76,7 @@ static inline void touch_ll_set_meas_time(uint16_t meas_time)
  */
 static inline void touch_ll_get_meas_time(uint16_t *meas_time)
 {
-    *meas_time = SENS.sar_touch_ctrl1.touch_meas_delay;
+    *meas_time = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_meas_delay);
 }
 
 /**
@@ -86,7 +90,7 @@ static inline void touch_ll_get_meas_time(uint16_t *meas_time)
 static inline void touch_ll_set_sleep_time(uint16_t sleep_time)
 {
     //touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK( can be 150k or 32k depending on the options)
-    SENS.sar_touch_ctrl2.touch_sleep_cycles = sleep_time;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl2, touch_sleep_cycles, sleep_time);
 }
 
 /**
@@ -96,7 +100,7 @@ static inline void touch_ll_set_sleep_time(uint16_t sleep_time)
  */
 static inline void touch_ll_get_sleep_time(uint16_t *sleep_time)
 {
-    *sleep_time = SENS.sar_touch_ctrl2.touch_sleep_cycles;
+    *sleep_time = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_ctrl2, touch_sleep_cycles);
 }
 
 /**
@@ -291,9 +295,9 @@ static inline void touch_ll_set_threshold(touch_pad_t touch_num, uint16_t thresh
 {
     touch_pad_t tp_wrap = touch_ll_num_wrap(touch_num);
     if (tp_wrap & 0x1) {
-        SENS.touch_thresh[tp_wrap / 2].l_thresh = threshold;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], l_thresh, threshold);
     } else {
-        SENS.touch_thresh[tp_wrap / 2].h_thresh = threshold;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], h_thresh, threshold);
     }
 }
 
@@ -308,8 +312,8 @@ static inline void touch_ll_get_threshold(touch_pad_t touch_num, uint16_t *thres
     touch_pad_t tp_wrap = touch_ll_num_wrap(touch_num);
     if (threshold) {
         *threshold = (tp_wrap & 0x1 ) ?
-                     SENS.touch_thresh[tp_wrap / 2].l_thresh :
-                     SENS.touch_thresh[tp_wrap / 2].h_thresh;
+            HAL_FORCE_READ_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], l_thresh) :
+            HAL_FORCE_READ_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], h_thresh);
     }
 }
 
@@ -489,7 +493,8 @@ static inline void touch_ll_intr_clear(void)
 static inline uint32_t touch_ll_read_raw_data(touch_pad_t touch_num)
 {
     touch_pad_t tp_wrap = touch_ll_num_wrap(touch_num);
-    return ((tp_wrap & 0x1) ? SENS.touch_meas[tp_wrap / 2].l_val : SENS.touch_meas[tp_wrap / 2].h_val);
+    return ((tp_wrap & 0x1) ? HAL_FORCE_READ_U32_REG_FIELD(SENS.touch_meas[tp_wrap / 2], l_val) :
+                              HAL_FORCE_READ_U32_REG_FIELD(SENS.touch_meas[tp_wrap / 2], h_val));
 }
 
 /**
diff --git a/components/hal/esp32/include/hal/twai_ll.h b/components/hal/esp32/include/hal/twai_ll.h
index 0a37c61631..72949aa9cf 100644
--- a/components/hal/esp32/include/hal/twai_ll.h
+++ b/components/hal/esp32/include/hal/twai_ll.h
@@ -32,6 +32,7 @@ extern "C" {
 #include "hal/misc.h"
 #include "hal/twai_types.h"
 #include "soc/twai_periph.h"
+#include "soc/twai_struct.h"
 
 /* ------------------------- Defines and Typedefs --------------------------- */
 
@@ -491,7 +492,7 @@ static inline void twai_ll_parse_err_code_cap(twai_dev_t *hw,
  */
 static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl)
 {
-    hw->error_warning_limit_reg.ewl = ewl;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl);
 }
 
 /**
@@ -531,7 +532,7 @@ static inline uint32_t twai_ll_get_rec(twai_dev_t *hw)
  */
 static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec)
 {
-    hw->rx_error_counter_reg.rxerr = rec;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec);
 }
 
 /* ------------------------ TX Error Count Register ------------------------- */
@@ -559,7 +560,7 @@ static inline uint32_t twai_ll_get_tec(twai_dev_t *hw)
  */
 static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
 {
-    hw->tx_error_counter_reg.txerr = tec;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec);
 }
 
 /* ---------------------- Acceptance Filter Registers ----------------------- */
@@ -578,8 +579,8 @@ static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_
     uint32_t code_swapped = HAL_SWAP32(code);
     uint32_t mask_swapped = HAL_SWAP32(mask);
     for (int i = 0; i < 4; i++) {
-        hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
-        hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0xFF));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0xFF));
     }
     hw->mode_reg.afm = single_filter;
 }
@@ -614,7 +615,7 @@ static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t
 {
     //Copy RX buffer registers into frame
     for (int i = 0; i < 13; i++) {
-        rx_frame->bytes[i] =  hw->tx_rx_buffer[i].byte;
+        rx_frame->bytes[i] =  HAL_FORCE_READ_U32_REG_FIELD(hw->tx_rx_buffer[i], byte);
     }
 }
 
@@ -794,8 +795,8 @@ static inline void twai_ll_save_reg(twai_dev_t *hw, twai_ll_reg_save_t *reg_save
     reg_save->bus_timing_1_reg = (uint8_t) hw->bus_timing_1_reg.val;
     reg_save->error_warning_limit_reg = (uint8_t) hw->error_warning_limit_reg.val;
     for (int i = 0; i < 4; i++) {
-        reg_save->acr_reg[i] = hw->acceptance_filter.acr[i].byte;
-        reg_save->amr_reg[i] = hw->acceptance_filter.amr[i].byte;
+        reg_save->acr_reg[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte);
+        reg_save->amr_reg[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte);
     }
     reg_save->rx_error_counter_reg = (uint8_t) hw->rx_error_counter_reg.val;
     reg_save->tx_error_counter_reg = (uint8_t) hw->tx_error_counter_reg.val;
@@ -821,8 +822,8 @@ static inline void twai_ll_restore_reg(twai_dev_t *hw, twai_ll_reg_save_t *reg_s
     hw->bus_timing_1_reg.val = reg_save->bus_timing_1_reg;
     hw->error_warning_limit_reg.val = reg_save->error_warning_limit_reg;
     for (int i = 0; i < 4; i++) {
-        hw->acceptance_filter.acr[i].byte = reg_save->acr_reg[i];
-        hw->acceptance_filter.amr[i].byte = reg_save->amr_reg[i];
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, reg_save->acr_reg[i]);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, reg_save->amr_reg[i]);
     }
     hw->rx_error_counter_reg.val = reg_save->rx_error_counter_reg;
     hw->tx_error_counter_reg.val = reg_save->tx_error_counter_reg;
diff --git a/components/hal/esp32/include/hal/uart_ll.h b/components/hal/esp32/include/hal/uart_ll.h
index ed52f969bd..de8fc640ff 100644
--- a/components/hal/esp32/include/hal/uart_ll.h
+++ b/components/hal/esp32/include/hal/uart_ll.h
@@ -17,8 +17,11 @@
 
 
 #pragma once
+
+#include "hal/misc.h"
 #include "esp_attr.h"
 #include "soc/uart_periph.h"
+#include "soc/uart_struct.h"
 #include "hal/uart_types.h"
 
 #ifdef __cplusplus
@@ -249,7 +252,7 @@ FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
     //Get the UART APB fifo addr
     uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_REG(0) : (hw == &UART1) ? UART_FIFO_REG(1) : UART_FIFO_REG(2);
     do {
-        fifo_cnt = hw->status.rxfifo_cnt;
+        fifo_cnt = HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
         rxmem_sta.val = hw->mem_rx_status.val;
         if(fifo_cnt != 0 ||  (rxmem_sta.rd_addr != rxmem_sta.wr_addr)) {
             READ_PERI_REG(fifo_addr);
@@ -287,7 +290,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
  */
 FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
 {
-    uint32_t fifo_cnt = hw->status.rxfifo_cnt;
+    uint32_t fifo_cnt = HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
     typeof(hw->mem_rx_status) rx_status = hw->mem_rx_status;
     uint32_t len = 0;
 
@@ -313,7 +316,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
  */
 FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
 {
-    return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
+    return UART_LL_FIFO_DEF_LEN - HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt);
 }
 
 /**
@@ -453,7 +456,7 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num
 FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
 {
     if(break_num > 0) {
-        hw->idle_conf.tx_brk_num = break_num;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->idle_conf, tx_brk_num, break_num);
         hw->conf0.txd_brk = 1;
     } else {
         hw->conf0.txd_brk = 0;
@@ -518,10 +521,10 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
     if(sw_flow_ctrl_en) {
         hw->flow_conf.xonoff_del = 1;
         hw->flow_conf.sw_flow_con_en = 1;
-        hw->swfc_conf.xon_threshold = flow_ctrl->xon_thrd;
-        hw->swfc_conf.xoff_threshold = flow_ctrl->xoff_thrd;
-        hw->swfc_conf.xon_char = flow_ctrl->xon_char;
-        hw->swfc_conf.xoff_char = flow_ctrl->xoff_char;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_threshold, flow_ctrl->xon_thrd);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xoff_threshold, flow_ctrl->xoff_thrd);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_char, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xoff_char, flow_ctrl->xoff_char);
     } else {
         hw->flow_conf.sw_flow_con_en = 0;
         hw->flow_conf.xonoff_del = 0;
@@ -543,8 +546,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
  */
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
-    hw->at_cmd_char.data = cmd_char->cmd_char;
-    hw->at_cmd_char.char_num = cmd_char->char_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
     hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle;
     hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle;
     hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout;
@@ -729,8 +732,8 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
  */
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
-    *cmd_char = hw->at_cmd_char.data;
-    *char_num = hw->at_cmd_char.char_num;
+    *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
 }
 
 /**
diff --git a/components/hal/esp32c3/include/hal/adc_ll.h b/components/hal/esp32c3/include/hal/adc_ll.h
index a2fd21f2b5..49ff4a23f4 100644
--- a/components/hal/esp32c3/include/hal/adc_ll.h
+++ b/components/hal/esp32c3/include/hal/adc_ll.h
@@ -15,6 +15,7 @@
 
 #include <stdbool.h>
 #include <stdlib.h>
+#include "hal/misc.h"
 #include "regi2c_ctrl.h"
 #include "esp_attr.h"
 
@@ -94,11 +95,11 @@ typedef enum {
 static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
 {
     // Internal FSM reset wait time
-    APB_SARADC.fsm_wait.rstb_wait = rst_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait);
     // Internal FSM start wait time
-    APB_SARADC.fsm_wait.xpd_wait = start_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait);
     // Internal FSM standby wait time
-    APB_SARADC.fsm_wait.standby_wait = standby_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait);
 }
 
 /**
@@ -124,7 +125,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock devided from digital controller clock clk */
-    APB_SARADC.ctrl.sar_clk_div = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div);
 }
 
 /**
@@ -135,7 +136,7 @@ static inline void adc_ll_digi_set_clk_div(uint32_t div)
  */
 static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
 {
-    APB_SARADC.ctrl2.max_meas_num = meas_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num);
 }
 
 /**
@@ -267,7 +268,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  */
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
-    APB_SARADC.apb_adc_clkm_conf.clkm_div_num = div_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num);
     APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b;
     APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a;
 }
@@ -404,7 +405,7 @@ static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx)
  */
 static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
 {
-    APB_SARADC.dma_conf.apb_adc_eof_num = num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num);
 }
 
 /**
diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h
index da61aa198c..6214bc06e3 100644
--- a/components/hal/esp32c3/include/hal/gpio_ll.h
+++ b/components/hal/esp32c3/include/hal/gpio_ll.h
@@ -24,6 +24,7 @@
 
 #include "soc/soc.h"
 #include "soc/gpio_periph.h"
+#include "soc/gpio_struct.h"
 #include "soc/rtc_cntl_reg.h"
 #include "hal/gpio_types.h"
 #include "stdlib.h"
diff --git a/components/hal/esp32c3/include/hal/gpspi_flash_ll.h b/components/hal/esp32c3/include/hal/gpspi_flash_ll.h
index 9f7f8e54a1..212e03a06d 100644
--- a/components/hal/esp32c3/include/hal/gpspi_flash_ll.h
+++ b/components/hal/esp32c3/include/hal/gpspi_flash_ll.h
@@ -24,11 +24,13 @@
 
 #include <stdlib.h>
 #include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
 #include <sys/param.h> // For MIN/MAX
 #include <stdbool.h>
 #include <string.h>
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -363,7 +365,7 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
-    dev->user1.usr_dummy_cyclelen = dummy_n - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
 }
 
 /**
diff --git a/components/hal/esp32c3/include/hal/i2c_ll.h b/components/hal/esp32c3/include/hal/i2c_ll.h
index d8fbfd206c..31743005b6 100644
--- a/components/hal/esp32c3/include/hal/i2c_ll.h
+++ b/components/hal/esp32c3/include/hal/i2c_ll.h
@@ -15,8 +15,11 @@
 // The LL layer for I2C register operations
 
 #pragma once
+
+#include "hal/misc.h"
 #include "soc/i2c_periph.h"
 #include "soc/soc_caps.h"
+#include "soc/i2c_struct.h"
 #include "hal/i2c_types.h"
 #include "soc/rtc_cntl_reg.h"
 #include "esp_rom_sys.h"
@@ -154,7 +157,7 @@ static inline void i2c_ll_update(i2c_dev_t *hw)
  */
 static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg)
 {
-    hw->clk_conf.sclk_div_num = bus_cfg->clkm_div - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1);
     //scl period
     hw->scl_low_period.period = bus_cfg->scl_low - 1;
     hw->scl_high_period.period = bus_cfg->scl_high;
@@ -576,7 +579,7 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l
 static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for (int i = 0; i< len; i++) {
-        hw->fifo_data.data = ptr[i];
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo_data, data, ptr[i]);
     }
 }
 
@@ -592,7 +595,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for(int i = 0; i < len; i++) {
-        ptr[i] = hw->fifo_data.data;
+        ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->fifo_data, data);
     }
 }
 
diff --git a/components/hal/esp32c3/include/hal/i2s_ll.h b/components/hal/esp32c3/include/hal/i2s_ll.h
index 3bca90102c..30fbfb7e51 100644
--- a/components/hal/esp32c3/include/hal/i2s_ll.h
+++ b/components/hal/esp32c3/include/hal/i2s_ll.h
@@ -21,7 +21,9 @@
 
 #pragma once
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/i2s_periph.h"
+#include "soc/i2s_struct.h"
 #include "hal/i2s_types.h"
 
 #ifdef __cplusplus
@@ -218,7 +220,7 @@ static inline void i2s_ll_tx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
             hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
         }
     }
-    hw->tx_clkm_conf.tx_clkm_div_num = set->mclk_div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, set->mclk_div);
 }
 
 /**
@@ -257,7 +259,7 @@ static inline void i2s_ll_rx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
             hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
         }
     }
-    hw->rx_clkm_conf.rx_clkm_div_num = set->mclk_div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, set->mclk_div);
 }
 
 /**
@@ -500,7 +502,7 @@ static inline void i2s_ll_tx_enable_pdm(i2s_dev_t *hw, bool pdm_enable)
  */
 static inline void i2s_ll_tx_set_pdm_prescale(i2s_dev_t *hw, bool prescale)
 {
-    hw->tx_pcm2pdm_conf.tx_pdm_prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_pcm2pdm_conf, tx_pdm_prescale, prescale);
 }
 
 /**
diff --git a/components/hal/esp32c3/include/hal/ledc_ll.h b/components/hal/esp32c3/include/hal/ledc_ll.h
index eafae904ba..fb495b0319 100644
--- a/components/hal/esp32c3/include/hal/ledc_ll.h
+++ b/components/hal/esp32c3/include/hal/ledc_ll.h
@@ -19,6 +19,7 @@
 
 #include "hal/ledc_types.h"
 #include "soc/ledc_periph.h"
+#include "soc/ledc_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/hal/esp32c3/include/hal/mwdt_ll.h b/components/hal/esp32c3/include/hal/mwdt_ll.h
index b192a8400f..944108439e 100644
--- a/components/hal/esp32c3/include/hal/mwdt_ll.h
+++ b/components/hal/esp32c3/include/hal/mwdt_ll.h
@@ -24,6 +24,7 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
 #include "hal/wdt_types.h"
 #include "esp_attr.h"
 
diff --git a/components/hal/esp32c3/include/hal/rmt_ll.h b/components/hal/esp32c3/include/hal/rmt_ll.h
index f5427d150a..0f703aebc7 100644
--- a/components/hal/esp32c3/include/hal/rmt_ll.h
+++ b/components/hal/esp32c3/include/hal/rmt_ll.h
@@ -16,6 +16,7 @@
 #include <stdint.h>
 #include <stdbool.h>
 #include <stddef.h>
+#include "hal/misc.h"
 #include "soc/rmt_struct.h"
 
 #ifdef __cplusplus
@@ -58,7 +59,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel,
     // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b)
     dev->sys_conf.sclk_active = 0;
     dev->sys_conf.sclk_sel = src;
-    dev->sys_conf.sclk_div_num = div_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sys_conf, sclk_div_num, div_num);
     dev->sys_conf.sclk_div_a = div_a;
     dev->sys_conf.sclk_div_b = div_b;
     dev->sys_conf.sclk_active = 1;
@@ -140,22 +141,22 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel
 
 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->tx_conf[channel].div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_conf[channel], div_cnt, div);
 }
 
 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->rx_conf[channel].conf0.div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt, div);
 }
 
 static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->tx_conf[channel].div_cnt;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->tx_conf[channel], div_cnt);
 }
 
 static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->rx_conf[channel].conf0.div_cnt;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt);
 }
 
 static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -231,7 +232,7 @@ static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, boo
 
 static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->rx_conf[channel].conf1.rx_filter_thres = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf1, rx_filter_thres, thres);
 }
 
 static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -441,14 +442,14 @@ static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
 
 static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->tx_carrier[channel].high;
-    *low_ticks = dev->tx_carrier[channel].low;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_carrier[channel], high);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_carrier[channel], low);
 }
 
 static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->rx_carrier[channel].high_thres;
-    *low_ticks = dev->rx_carrier[channel].low_thres;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_carrier[channel], high_thres);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_carrier[channel], low_thres);
 }
 
 static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
diff --git a/components/hal/esp32c3/include/hal/rwdt_ll.h b/components/hal/esp32c3/include/hal/rwdt_ll.h
index 87ae4f7294..0986ce3dec 100644
--- a/components/hal/esp32c3/include/hal/rwdt_ll.h
+++ b/components/hal/esp32c3/include/hal/rwdt_ll.h
@@ -23,8 +23,10 @@ extern "C" {
 
 #include <stdlib.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "hal/wdt_types.h"
 #include "soc/rtc_cntl_periph.h"
+#include "soc/rtc_cntl_struct.h"
 #include "soc/efuse_reg.h"
 #include "esp_attr.h"
 
@@ -239,7 +241,7 @@ FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rtc_cntl_dev_t *hw, bool enable
  */
 FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rtc_cntl_dev_t *hw, uint32_t width)
 {
-    hw->wdt_config0.chip_reset_width = width;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config0, chip_reset_width, width);
 }
 
 /**
diff --git a/components/hal/esp32c3/include/hal/sigmadelta_ll.h b/components/hal/esp32c3/include/hal/sigmadelta_ll.h
index 87f75dab9e..f6c37054a3 100644
--- a/components/hal/esp32c3/include/hal/sigmadelta_ll.h
+++ b/components/hal/esp32c3/include/hal/sigmadelta_ll.h
@@ -22,7 +22,9 @@
 #pragma once
 
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/sigmadelta_periph.h"
+#include "soc/gpio_sd_struct.h"
 #include "hal/sigmadelta_types.h"
 
 #ifdef __cplusplus
@@ -53,7 +55,7 @@ static inline void sigmadelta_ll_set_en(gpio_sd_dev_t *hw, bool en)
  */
 static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, int8_t duty)
 {
-    hw->channel[channel].duty = duty;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)duty);
 }
 
 /**
@@ -65,7 +67,7 @@ static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_
  */
 static inline void sigmadelta_ll_set_prescale(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, uint8_t prescale)
 {
-    hw->channel[channel].prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale);
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32c3/include/hal/spi_ll.h b/components/hal/esp32c3/include/hal/spi_ll.h
index 99dd305ac3..38e1676d04 100644
--- a/components/hal/esp32c3/include/hal/spi_ll.h
+++ b/components/hal/esp32c3/include/hal/spi_ll.h
@@ -27,6 +27,7 @@
 #include "esp_attr.h"
 #include "esp_types.h"
 #include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
 #include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
@@ -901,13 +902,13 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 {
     if (lsbfirst) {
         // The output command start from bit0 to bit 15, kept as is.
-        hw->user2.usr_command_value = cmd;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd);
     } else {
         /* Output command will be sent from bit 7 to 0 of command_value, and
          * then bit 15 to 8 of the same register field. Shift and swap to send
          * more straightly.
          */
-        hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen));
     }
 }
 
@@ -923,7 +924,7 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
-    hw->user1.usr_dummy_cyclelen = dummy_n - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
 }
 
 /**
diff --git a/components/hal/esp32c3/include/hal/spimem_flash_ll.h b/components/hal/esp32c3/include/hal/spimem_flash_ll.h
index 7641c3d723..92c8748dd4 100644
--- a/components/hal/esp32c3/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32c3/include/hal/spimem_flash_ll.h
@@ -28,6 +28,7 @@
 #include <string.h>
 
 #include "soc/spi_periph.h"
+#include "soc/spi_mem_struct.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
 
@@ -157,7 +158,7 @@ static inline void spimem_flash_ll_auto_resume_init(spi_mem_dev_t *dev, bool aut
  */
 static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd)
 {
-    dev->flash_sus_cmd.flash_pes_command = sus_cmd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_pes_command, sus_cmd);
 }
 
 /**
@@ -169,7 +170,7 @@ static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_
  */
 static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd)
 {
-    dev->flash_sus_cmd.flash_per_command = res_cmd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_per_command, res_cmd);
 }
 
 /**
@@ -181,7 +182,7 @@ static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t
  */
 static inline void spimem_flash_ll_rd_sus_cmd_setup(spi_mem_dev_t *dev, uint32_t pesr_cmd)
 {
-    dev->flash_sus_cmd.wait_pesr_command = pesr_cmd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, wait_pesr_command, pesr_cmd);
 }
 
 /**
@@ -218,7 +219,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool
 static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf)
 {
     dev->flash_sus_ctrl.frd_sus_2b = 0;
-    dev->flash_sus_ctrl.pesr_end_msk = sus_conf;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf);
 }
 
 /**
@@ -229,7 +230,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3
  */
 static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti)
 {
-    dev->flash_waiti_ctrl.waiti_cmd = 0x05;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05);
     dev->flash_sus_ctrl.flash_per_wait_en = auto_waiti;
     dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti;
 }
diff --git a/components/hal/esp32c3/include/hal/timer_ll.h b/components/hal/esp32c3/include/hal/timer_ll.h
index b85436f0d3..5e51b102f1 100644
--- a/components/hal/esp32c3/include/hal/timer_ll.h
+++ b/components/hal/esp32c3/include/hal/timer_ll.h
@@ -22,7 +22,9 @@ extern "C" {
 #endif
 
 #include <stdlib.h>
+#include "hal/misc.h"
 #include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
 #include "hal/timer_types.h"
 #include "hal/assert.h"
 
@@ -55,7 +57,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
     int timer_en = hw->hw_timer[timer_num].config.tx_en;
     hw->hw_timer[timer_num].config.tx_en = 0;
     hw->hw_timer[timer_num].config.tx_divcnt_rst = 1;
-    hw->hw_timer[timer_num].config.tx_divider = divider;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
     hw->hw_timer[timer_num].config.tx_en = timer_en;
 }
 
@@ -70,7 +72,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
  */
 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
 {
-    uint32_t d = hw->hw_timer[timer_num].config.tx_divider;
+    uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider);
     if (d == 0) {
         d = 65536;
     } else if (d == 1) {
diff --git a/components/hal/esp32c3/include/hal/twai_ll.h b/components/hal/esp32c3/include/hal/twai_ll.h
index 92e0401118..371d4dd361 100644
--- a/components/hal/esp32c3/include/hal/twai_ll.h
+++ b/components/hal/esp32c3/include/hal/twai_ll.h
@@ -31,6 +31,7 @@ extern "C" {
 #include "hal/misc.h"
 #include "hal/twai_types.h"
 #include "soc/twai_periph.h"
+#include "soc/twai_struct.h"
 
 /* ------------------------- Defines and Typedefs --------------------------- */
 
@@ -399,7 +400,7 @@ static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw)
  */
 static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl)
 {
-    hw->error_warning_limit_reg.ewl = ewl;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl);
 }
 
 /**
@@ -439,7 +440,7 @@ static inline uint32_t twai_ll_get_rec(twai_dev_t *hw)
  */
 static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec)
 {
-    hw->rx_error_counter_reg.rxerr = rec;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec);
 }
 
 /* ------------------------ TX Error Count Register ------------------------- */
@@ -467,7 +468,7 @@ static inline uint32_t twai_ll_get_tec(twai_dev_t *hw)
  */
 static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
 {
-    hw->tx_error_counter_reg.txerr = tec;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec);
 }
 
 /* ---------------------- Acceptance Filter Registers ----------------------- */
@@ -486,8 +487,8 @@ static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_
     uint32_t code_swapped = HAL_SWAP32(code);
     uint32_t mask_swapped = HAL_SWAP32(mask);
     for (int i = 0; i < 4; i++) {
-        hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
-        hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0xFF));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0xFF));
     }
     hw->mode_reg.afm = single_filter;
 }
@@ -522,7 +523,7 @@ static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t
 {
     //Copy RX buffer registers into frame
     for (int i = 0; i < 13; i++) {
-        rx_frame->bytes[i] =  hw->tx_rx_buffer[i].byte;
+        rx_frame->bytes[i] =  HAL_FORCE_READ_U32_REG_FIELD(hw->tx_rx_buffer[i], byte);
     }
 }
 
@@ -652,14 +653,14 @@ static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider)
 {
     if (divider >= 2 && divider <= 490) {
         hw->clock_divider_reg.co = 0;
-        hw->clock_divider_reg.cd = (divider / 2) - 1;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1);
     } else if (divider == 1) {
         //Setting the divider reg to max value (255) means a divider of 1
         hw->clock_divider_reg.co = 0;
-        hw->clock_divider_reg.cd = 255;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255);
     } else {
         hw->clock_divider_reg.co = 1;
-        hw->clock_divider_reg.cd = 0;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0);
     }
 }
 
diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h
index 344a6ecc42..f94296327a 100644
--- a/components/hal/esp32c3/include/hal/uart_ll.h
+++ b/components/hal/esp32c3/include/hal/uart_ll.h
@@ -17,8 +17,11 @@
 
 
 #pragma once
+
+#include "hal/misc.h"
 #include "hal/uart_types.h"
 #include "soc/uart_periph.h"
+#include "soc/uart_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -163,7 +166,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
     // an integer part and a fractional part.
     hw->clk_div.div_int = clk_div >> 4;
     hw->clk_div.div_frag = clk_div &  0xf;
-    hw->clk_conf.sclk_div_num = sclk_div - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
 #undef DIV_UP
 }
 
@@ -178,7 +181,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
 {
     uint32_t sclk_freq = uart_ll_get_sclk_freq(hw);
     typeof(hw->clk_div) div_reg = hw->clk_div;
-    return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (hw->clk_conf.sclk_div_num + 1));
+    return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1));
 }
 
 /**
@@ -451,7 +454,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
 static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
 {
     if (break_num > 0) {
-        hw->txbrk_conf.tx_brk_num = break_num;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf, tx_brk_num, break_num);
         hw->conf0.txd_brk = 1;
     } else {
         hw->conf0.txd_brk = 0;
@@ -518,8 +521,8 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
         hw->flow_conf.sw_flow_con_en = 1;
         hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
         hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd;
-        hw->swfc_conf1.xon_char = flow_ctrl->xon_char;
-        hw->swfc_conf0.xoff_char = flow_ctrl->xoff_char;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char);
     } else {
         hw->flow_conf.sw_flow_con_en = 0;
         hw->flow_conf.xonoff_del = 0;
@@ -541,11 +544,11 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
  */
 static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
-    hw->at_cmd_char.data = cmd_char->cmd_char;
-    hw->at_cmd_char.char_num = cmd_char->char_num;
-    hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle;
-    hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle;
-    hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout);
 }
 
 /**
@@ -734,8 +737,8 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
  */
 static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
-    *cmd_char = hw->at_cmd_char.data;
-    *char_num = hw->at_cmd_char.char_num;
+    *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
 }
 
 /**
diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h
index 6e6ce7c2fc..7806465258 100644
--- a/components/hal/esp32h2/include/hal/adc_ll.h
+++ b/components/hal/esp32h2/include/hal/adc_ll.h
@@ -24,6 +24,7 @@
 #include "soc/apb_saradc_reg.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -94,11 +95,11 @@ typedef enum {
 static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
 {
     // Internal FSM reset wait time
-    APB_SARADC.fsm_wait.rstb_wait = rst_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait);
     // Internal FSM start wait time
-    APB_SARADC.fsm_wait.xpd_wait = start_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait);
     // Internal FSM standby wait time
-    APB_SARADC.fsm_wait.standby_wait = standby_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait);
 }
 
 /**
@@ -124,7 +125,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock devided from digital controller clock clk */
-    APB_SARADC.ctrl.sar_clk_div = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div);
 }
 
 /**
@@ -135,7 +136,7 @@ static inline void adc_ll_digi_set_clk_div(uint32_t div)
  */
 static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
 {
-    APB_SARADC.ctrl2.max_meas_num = meas_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num);
 }
 
 /**
@@ -267,7 +268,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  */
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
-    APB_SARADC.apb_adc_clkm_conf.clkm_div_num = div_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num);
     APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b;
     APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a;
 }
@@ -404,7 +405,7 @@ static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx)
  */
 static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
 {
-    APB_SARADC.dma_conf.apb_adc_eof_num = num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num);
 }
 
 /**
diff --git a/components/hal/esp32h2/include/hal/gpio_ll.h b/components/hal/esp32h2/include/hal/gpio_ll.h
index e35a71db39..c6d751847c 100644
--- a/components/hal/esp32h2/include/hal/gpio_ll.h
+++ b/components/hal/esp32h2/include/hal/gpio_ll.h
@@ -25,6 +25,7 @@
 #include "soc/soc.h"
 #include "soc/gpio_periph.h"
 #include "soc/rtc_cntl_reg.h"
+#include "soc/gpio_struct.h"
 #include "hal/gpio_types.h"
 #include "stdlib.h"
 
diff --git a/components/hal/esp32h2/include/hal/gpspi_flash_ll.h b/components/hal/esp32h2/include/hal/gpspi_flash_ll.h
index d26e00c720..d6b227e6f6 100644
--- a/components/hal/esp32h2/include/hal/gpspi_flash_ll.h
+++ b/components/hal/esp32h2/include/hal/gpspi_flash_ll.h
@@ -24,11 +24,13 @@
 
 #include <stdlib.h>
 #include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
 #include <sys/param.h> // For MIN/MAX
 #include <stdbool.h>
 #include <string.h>
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -363,7 +365,7 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
-    dev->user1.usr_dummy_cyclelen = dummy_n - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
 }
 
 /**
diff --git a/components/hal/esp32h2/include/hal/i2c_ll.h b/components/hal/esp32h2/include/hal/i2c_ll.h
index 88d4493b0e..2e34e4a55c 100644
--- a/components/hal/esp32h2/include/hal/i2c_ll.h
+++ b/components/hal/esp32h2/include/hal/i2c_ll.h
@@ -15,8 +15,11 @@
 // The LL layer for I2C register operations
 
 #pragma once
+
+#include "hal/misc.h"
 #include "soc/i2c_periph.h"
 #include "soc/soc_caps.h"
+#include "soc/i2c_struct.h"
 #include "hal/i2c_types.h"
 #include "soc/rtc_cntl_reg.h"
 #include "esp_rom_sys.h"
@@ -154,7 +157,7 @@ static inline void i2c_ll_update(i2c_dev_t *hw)
  */
 static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg)
 {
-    hw->clk_conf.sclk_div_num = bus_cfg->clkm_div - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1);
     //scl period
     hw->scl_low_period.period = bus_cfg->scl_low - 1;
     hw->scl_high_period.period = bus_cfg->scl_high;
@@ -576,7 +579,7 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l
 static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for (int i = 0; i< len; i++) {
-        hw->fifo_data.data = ptr[i];
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo_data, data, ptr[i]);
     }
 }
 
@@ -592,7 +595,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for(int i = 0; i < len; i++) {
-        ptr[i] = hw->fifo_data.data;
+        ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->fifo_data, data);
     }
 }
 
diff --git a/components/hal/esp32h2/include/hal/i2s_ll.h b/components/hal/esp32h2/include/hal/i2s_ll.h
index 398c2487ec..9819a8ed4b 100644
--- a/components/hal/esp32h2/include/hal/i2s_ll.h
+++ b/components/hal/esp32h2/include/hal/i2s_ll.h
@@ -22,7 +22,9 @@
 
 #pragma once
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/i2s_periph.h"
+#include "soc/i2s_struct.h"
 #include "hal/i2s_types.h"
 
 #ifdef __cplusplus
@@ -219,7 +221,7 @@ static inline void i2s_ll_tx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
             hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
         }
     }
-    hw->tx_clkm_conf.tx_clkm_div_num = set->mclk_div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, set->mclk_div);
 }
 
 /**
@@ -258,7 +260,7 @@ static inline void i2s_ll_rx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
             hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
         }
     }
-    hw->rx_clkm_conf.rx_clkm_div_num = set->mclk_div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, set->mclk_div);
 }
 
 /**
@@ -501,7 +503,7 @@ static inline void i2s_ll_tx_enable_pdm(i2s_dev_t *hw, bool pdm_enable)
  */
 static inline void i2s_ll_tx_set_pdm_prescale(i2s_dev_t *hw, bool prescale)
 {
-    hw->tx_pcm2pdm_conf.tx_pdm_prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_pcm2pdm_conf, tx_pdm_prescale, prescale);
 }
 
 /**
diff --git a/components/hal/esp32h2/include/hal/ledc_ll.h b/components/hal/esp32h2/include/hal/ledc_ll.h
index eafae904ba..fb495b0319 100644
--- a/components/hal/esp32h2/include/hal/ledc_ll.h
+++ b/components/hal/esp32h2/include/hal/ledc_ll.h
@@ -19,6 +19,7 @@
 
 #include "hal/ledc_types.h"
 #include "soc/ledc_periph.h"
+#include "soc/ledc_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/hal/esp32h2/include/hal/mwdt_ll.h b/components/hal/esp32h2/include/hal/mwdt_ll.h
index b192a8400f..944108439e 100644
--- a/components/hal/esp32h2/include/hal/mwdt_ll.h
+++ b/components/hal/esp32h2/include/hal/mwdt_ll.h
@@ -24,6 +24,7 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
 #include "hal/wdt_types.h"
 #include "esp_attr.h"
 
diff --git a/components/hal/esp32h2/include/hal/rmt_ll.h b/components/hal/esp32h2/include/hal/rmt_ll.h
index f5427d150a..6aa3655075 100644
--- a/components/hal/esp32h2/include/hal/rmt_ll.h
+++ b/components/hal/esp32h2/include/hal/rmt_ll.h
@@ -17,6 +17,7 @@
 #include <stdbool.h>
 #include <stddef.h>
 #include "soc/rmt_struct.h"
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -58,7 +59,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel,
     // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b)
     dev->sys_conf.sclk_active = 0;
     dev->sys_conf.sclk_sel = src;
-    dev->sys_conf.sclk_div_num = div_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sys_conf, sclk_div_num, div_num);
     dev->sys_conf.sclk_div_a = div_a;
     dev->sys_conf.sclk_div_b = div_b;
     dev->sys_conf.sclk_active = 1;
@@ -140,22 +141,22 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel
 
 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->tx_conf[channel].div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_conf[channel], div_cnt, div);
 }
 
 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->rx_conf[channel].conf0.div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt, div);
 }
 
 static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->tx_conf[channel].div_cnt;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->tx_conf[channel], div_cnt);
 }
 
 static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->rx_conf[channel].conf0.div_cnt;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt);
 }
 
 static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -231,7 +232,7 @@ static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, boo
 
 static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->rx_conf[channel].conf1.rx_filter_thres = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf1, rx_filter_thres, thres);
 }
 
 static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -441,14 +442,14 @@ static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
 
 static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->tx_carrier[channel].high;
-    *low_ticks = dev->tx_carrier[channel].low;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_carrier[channel], high);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_carrier[channel], low);
 }
 
 static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->rx_carrier[channel].high_thres;
-    *low_ticks = dev->rx_carrier[channel].low_thres;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_carrier[channel], high_thres);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_carrier[channel], low_thres);
 }
 
 static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
diff --git a/components/hal/esp32h2/include/hal/rwdt_ll.h b/components/hal/esp32h2/include/hal/rwdt_ll.h
index 87ae4f7294..0986ce3dec 100644
--- a/components/hal/esp32h2/include/hal/rwdt_ll.h
+++ b/components/hal/esp32h2/include/hal/rwdt_ll.h
@@ -23,8 +23,10 @@ extern "C" {
 
 #include <stdlib.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "hal/wdt_types.h"
 #include "soc/rtc_cntl_periph.h"
+#include "soc/rtc_cntl_struct.h"
 #include "soc/efuse_reg.h"
 #include "esp_attr.h"
 
@@ -239,7 +241,7 @@ FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rtc_cntl_dev_t *hw, bool enable
  */
 FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rtc_cntl_dev_t *hw, uint32_t width)
 {
-    hw->wdt_config0.chip_reset_width = width;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config0, chip_reset_width, width);
 }
 
 /**
diff --git a/components/hal/esp32h2/include/hal/sigmadelta_ll.h b/components/hal/esp32h2/include/hal/sigmadelta_ll.h
index 87f75dab9e..f6c37054a3 100644
--- a/components/hal/esp32h2/include/hal/sigmadelta_ll.h
+++ b/components/hal/esp32h2/include/hal/sigmadelta_ll.h
@@ -22,7 +22,9 @@
 #pragma once
 
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/sigmadelta_periph.h"
+#include "soc/gpio_sd_struct.h"
 #include "hal/sigmadelta_types.h"
 
 #ifdef __cplusplus
@@ -53,7 +55,7 @@ static inline void sigmadelta_ll_set_en(gpio_sd_dev_t *hw, bool en)
  */
 static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, int8_t duty)
 {
-    hw->channel[channel].duty = duty;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)duty);
 }
 
 /**
@@ -65,7 +67,7 @@ static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_
  */
 static inline void sigmadelta_ll_set_prescale(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, uint8_t prescale)
 {
-    hw->channel[channel].prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale);
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32h2/include/hal/spi_ll.h b/components/hal/esp32h2/include/hal/spi_ll.h
index 0cbb0bf3d5..764f3fd872 100644
--- a/components/hal/esp32h2/include/hal/spi_ll.h
+++ b/components/hal/esp32h2/include/hal/spi_ll.h
@@ -27,6 +27,7 @@
 #include "esp_attr.h"
 #include "esp_types.h"
 #include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
 #include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
@@ -900,13 +901,13 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 {
     if (lsbfirst) {
         // The output command start from bit0 to bit 15, kept as is.
-        hw->user2.usr_command_value = cmd;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd);
     } else {
         /* Output command will be sent from bit 7 to 0 of command_value, and
          * then bit 15 to 8 of the same register field. Shift and swap to send
          * more straightly.
          */
-        hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen));
     }
 }
 
@@ -922,7 +923,7 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
-    hw->user1.usr_dummy_cyclelen = dummy_n - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
 }
 
 /**
diff --git a/components/hal/esp32h2/include/hal/spimem_flash_ll.h b/components/hal/esp32h2/include/hal/spimem_flash_ll.h
index 14613abe02..0c464a20b2 100644
--- a/components/hal/esp32h2/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32h2/include/hal/spimem_flash_ll.h
@@ -28,6 +28,7 @@
 #include <string.h>
 
 #include "soc/spi_periph.h"
+#include "soc/spi_mem_struct.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
 
@@ -157,7 +158,7 @@ static inline void spimem_flash_ll_auto_resume_init(spi_mem_dev_t *dev, bool aut
  */
 static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd)
 {
-    dev->flash_sus_cmd.flash_pes_command = sus_cmd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_pes_command, sus_cmd);
 }
 
 /**
@@ -169,7 +170,7 @@ static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_
  */
 static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd)
 {
-    dev->flash_sus_cmd.flash_per_command = res_cmd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_per_command, res_cmd);
 }
 
 /**
@@ -181,7 +182,7 @@ static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t
  */
 static inline void spimem_flash_ll_rd_sus_cmd_setup(spi_mem_dev_t *dev, uint32_t pesr_cmd)
 {
-    dev->flash_sus_cmd.wait_pesr_command = pesr_cmd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, wait_pesr_command, pesr_cmd);
 }
 
 /**
@@ -218,7 +219,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool
 static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf)
 {
     dev->flash_sus_ctrl.frd_sus_2b = 0;
-    dev->flash_sus_ctrl.pesr_end_msk = sus_conf;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf);
 }
 
 /**
@@ -229,7 +230,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3
  */
 static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti)
 {
-    dev->flash_waiti_ctrl.waiti_cmd = 0x05;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05);
     dev->flash_sus_ctrl.flash_per_wait_en = auto_waiti;
     dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti;
 }
diff --git a/components/hal/esp32h2/include/hal/timer_ll.h b/components/hal/esp32h2/include/hal/timer_ll.h
index 9a5318f194..4032a1b1dd 100644
--- a/components/hal/esp32h2/include/hal/timer_ll.h
+++ b/components/hal/esp32h2/include/hal/timer_ll.h
@@ -22,7 +22,9 @@ extern "C" {
 #endif
 
 #include <stdlib.h>
+#include "hal/misc.h"
 #include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
 #include "hal/timer_types.h"
 #include "hal/assert.h"
 
@@ -55,7 +57,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
     int timer_en = hw->hw_timer[timer_num].config.tx_en;
     hw->hw_timer[timer_num].config.tx_en = 0;
     hw->hw_timer[timer_num].config.tx_divcnt_rst = 1;
-    hw->hw_timer[timer_num].config.tx_divider = divider;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
     hw->hw_timer[timer_num].config.tx_en = timer_en;
 }
 
@@ -70,7 +72,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
  */
 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
 {
-    uint32_t d = hw->hw_timer[timer_num].config.tx_divider;
+    uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider);
     if (d == 0) {
         d = 65536;
     } else if (d == 1) {
diff --git a/components/hal/esp32h2/include/hal/twai_ll.h b/components/hal/esp32h2/include/hal/twai_ll.h
index ed6fbc5795..92c46d010b 100644
--- a/components/hal/esp32h2/include/hal/twai_ll.h
+++ b/components/hal/esp32h2/include/hal/twai_ll.h
@@ -28,8 +28,10 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "hal/twai_types.h"
 #include "soc/twai_periph.h"
+#include "soc/twai_struct.h"
 
 /* ------------------------- Defines and Typedefs --------------------------- */
 
@@ -398,7 +400,7 @@ static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw)
  */
 static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl)
 {
-    hw->error_warning_limit_reg.ewl = ewl;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl);
 }
 
 /**
@@ -438,7 +440,7 @@ static inline uint32_t twai_ll_get_rec(twai_dev_t *hw)
  */
 static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec)
 {
-    hw->rx_error_counter_reg.rxerr = rec;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec);
 }
 
 /* ------------------------ TX Error Count Register ------------------------- */
@@ -466,7 +468,7 @@ static inline uint32_t twai_ll_get_tec(twai_dev_t *hw)
  */
 static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
 {
-    hw->tx_error_counter_reg.txerr = tec;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec);
 }
 
 /* ---------------------- Acceptance Filter Registers ----------------------- */
@@ -485,8 +487,8 @@ static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_
     uint32_t code_swapped = __builtin_bswap32(code);
     uint32_t mask_swapped = __builtin_bswap32(mask);
     for (int i = 0; i < 4; i++) {
-        hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
-        hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0xFF));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0xFF));
     }
     hw->mode_reg.afm = single_filter;
 }
@@ -521,7 +523,7 @@ static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t
 {
     //Copy RX buffer registers into frame
     for (int i = 0; i < 13; i++) {
-        rx_frame->bytes[i] =  hw->tx_rx_buffer[i].byte;
+        rx_frame->bytes[i] =  HAL_FORCE_READ_U32_REG_FIELD(hw->tx_rx_buffer[i], byte);
     }
 }
 
@@ -651,14 +653,14 @@ static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider)
 {
     if (divider >= 2 && divider <= 490) {
         hw->clock_divider_reg.co = 0;
-        hw->clock_divider_reg.cd = (divider / 2) - 1;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1);
     } else if (divider == 1) {
         //Setting the divider reg to max value (255) means a divider of 1
         hw->clock_divider_reg.co = 0;
-        hw->clock_divider_reg.cd = 255;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255);
     } else {
         hw->clock_divider_reg.co = 1;
-        hw->clock_divider_reg.cd = 0;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0);
     }
 }
 
diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h
index 6d8fd0f3e9..ca51779548 100644
--- a/components/hal/esp32h2/include/hal/uart_ll.h
+++ b/components/hal/esp32h2/include/hal/uart_ll.h
@@ -17,8 +17,11 @@
 
 
 #pragma once
+
+#include "hal/misc.h"
 #include "hal/uart_types.h"
 #include "soc/uart_periph.h"
+#include "soc/uart_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -163,7 +166,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
     // an integer part and a fractional part.
     hw->clk_div.div_int = clk_div >> 4;
     hw->clk_div.div_frag = clk_div &  0xf;
-    hw->clk_conf.sclk_div_num = sclk_div - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
 #undef DIV_UP
 }
 
@@ -178,7 +181,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
 {
     uint32_t sclk_freq = uart_ll_get_sclk_freq(hw);
     typeof(hw->clk_div) div_reg = hw->clk_div;
-    return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (hw->clk_conf.sclk_div_num + 1));
+    return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1));
 }
 
 /**
@@ -451,7 +454,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
 static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
 {
     if (break_num > 0) {
-        hw->txbrk_conf.tx_brk_num = break_num;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf, tx_brk_num, break_num);
         hw->conf0.txd_brk = 1;
     } else {
         hw->conf0.txd_brk = 0;
@@ -518,8 +521,8 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
         hw->flow_conf.sw_flow_con_en = 1;
         hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
         hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd;
-        hw->swfc_conf1.xon_char = flow_ctrl->xon_char;
-        hw->swfc_conf0.xoff_char = flow_ctrl->xoff_char;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char);
     } else {
         hw->flow_conf.sw_flow_con_en = 0;
         hw->flow_conf.xonoff_del = 0;
@@ -541,11 +544,11 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
  */
 static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
-    hw->at_cmd_char.data = cmd_char->cmd_char;
-    hw->at_cmd_char.char_num = cmd_char->char_num;
-    hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle;
-    hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle;
-    hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout);
 }
 
 /**
@@ -734,8 +737,8 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
  */
 static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
-    *cmd_char = hw->at_cmd_char.data;
-    *char_num = hw->at_cmd_char.char_num;
+    *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
 }
 
 /**
diff --git a/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
index e75cf67b43..0241436ec4 100644
--- a/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
+++ b/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
@@ -15,6 +15,8 @@
 // The LL layer of the USB-serial-jtag controller
 
 #pragma once
+
+#include "hal/misc.h"
 #include "soc/usb_serial_jtag_reg.h"
 #include "soc/usb_serial_jtag_struct.h"
 
@@ -108,7 +110,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
     int i;
     for (i = 0; i < (int)rd_len; i++) {
         if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
-        buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
+        buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte);
     }
     return i;
 }
@@ -127,7 +129,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
     int i;
     for (i = 0; i < (int)wr_len; i++) {
         if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
-        USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
+        HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]);
     }
     return i;
 }
diff --git a/components/hal/esp32s2/include/hal/adc_ll.h b/components/hal/esp32s2/include/hal/adc_ll.h
index ffad47a5c3..a44f50915f 100644
--- a/components/hal/esp32s2/include/hal/adc_ll.h
+++ b/components/hal/esp32s2/include/hal/adc_ll.h
@@ -1,9 +1,11 @@
 #pragma once
 
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/adc_periph.h"
 #include "hal/adc_types.h"
 #include "soc/apb_saradc_struct.h"
+#include "soc/sens_struct.h"
 #include "soc/apb_saradc_reg.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
@@ -83,11 +85,11 @@ typedef enum {
 static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
 {
     // Internal FSM reset wait time
-    APB_SARADC.fsm_wait.rstb_wait = rst_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait);
     // Internal FSM start wait time
-    APB_SARADC.fsm_wait.xpd_wait = start_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait);
     // Internal FSM standby wait time
-    APB_SARADC.fsm_wait.standby_wait = standby_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait);
 }
 
 /**
@@ -115,7 +117,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock devided from digital controller clock clk */
-    APB_SARADC.ctrl.sar_clk_div = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div);
 }
 
 /**
@@ -136,7 +138,7 @@ static inline void adc_ll_digi_set_output_format(adc_digi_output_format_t format
  */
 static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
 {
-    APB_SARADC.ctrl2.max_meas_num = meas_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num);
 }
 
 /**
@@ -307,7 +309,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  */
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
-    APB_SARADC.apb_adc_clkm_conf.clkm_div_num = div_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num);
     APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b;
     APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a;
 }
@@ -427,9 +429,9 @@ static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable)
 static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n)
 {
     if (adc_n == ADC_NUM_1) {
-        return APB_SARADC.filter_status.adc1_filter_data;
+        return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc1_filter_data);
     } else { // adc_n == ADC_NUM_2
-        return APB_SARADC.filter_status.adc2_filter_data;
+        return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc2_filter_data);
     }
 }
 
@@ -595,7 +597,7 @@ static inline uint32_t adc_ll_digi_get_intr_status(adc_ll_num_t adc_n)
  */
 static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
 {
-    APB_SARADC.dma_conf.apb_adc_eof_num = num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num);
 }
 
 /**
@@ -710,7 +712,7 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
 static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
 {
     if (adc_n == ADC_NUM_1) {
-        while (SENS.sar_slave_addr1.meas_status != 0);
+        while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {}
         SENS.sar_meas1_ctrl2.meas1_start_sar = 0;
         SENS.sar_meas1_ctrl2.meas1_start_sar = 1;
     } else { // adc_n == ADC_NUM_2
@@ -749,9 +751,9 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
 {
     int ret_val = 0;
     if (adc_n == ADC_NUM_1) {
-        ret_val = SENS.sar_meas1_ctrl2.meas1_data_sar;
+        ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas1_ctrl2, meas1_data_sar);
     } else { // adc_n == ADC_NUM_2
-        ret_val = SENS.sar_meas2_ctrl2.meas2_data_sar;
+        ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas2_ctrl2, meas2_data_sar);
     }
     return ret_val;
 }
@@ -906,9 +908,9 @@ static inline adc_ll_power_t adc_ll_get_power_manage(void)
 static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
 {
     if (adc_n == ADC_NUM_1) {
-        SENS.sar_reader1_ctrl.sar1_clk_div = div;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div);
     } else { // adc_n == ADC_NUM_2
-        SENS.sar_reader2_ctrl.sar2_clk_div = div;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div);
     }
 }
 
diff --git a/components/hal/esp32s2/include/hal/dac_ll.h b/components/hal/esp32s2/include/hal/dac_ll.h
index 11f3284f11..28c8ae2066 100644
--- a/components/hal/esp32s2/include/hal/dac_ll.h
+++ b/components/hal/esp32s2/include/hal/dac_ll.h
@@ -21,9 +21,12 @@
 #pragma once
 
 #include <stdlib.h>
+#include "hal/misc.h"
 #include "soc/dac_periph.h"
 #include "hal/dac_types.h"
 #include "soc/apb_saradc_struct.h"
+#include "soc/sens_struct.h"
+#include "soc/rtc_io_struct.h"
 #include "soc/apb_saradc_reg.h"
 
 #ifdef __cplusplus
@@ -74,10 +77,10 @@ static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t val
 {
     if (channel == DAC_CHANNEL_1) {
         SENS.sar_dac_ctrl2.dac_cw_en1 = 0;
-        RTCIO.pad_dac[channel].dac = value;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
     } else if (channel == DAC_CHANNEL_2) {
         SENS.sar_dac_ctrl2.dac_cw_en2 = 0;
-        RTCIO.pad_dac[channel].dac = value;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value);
     }
 }
 
@@ -145,7 +148,7 @@ static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable)
 static inline void dac_ll_cw_set_freq(uint32_t freq)
 {
     uint32_t sw_freq = freq * 0xFFFF / RTC_FAST_CLK_FREQ_APPROX;
-    SENS.sar_dac_ctrl1.sw_fstep = (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq);
 }
 
 /**
@@ -192,12 +195,12 @@ static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset)
         if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_CW_PHASE_180) {
             offset = 0 - offset;
         }
-        SENS.sar_dac_ctrl2.dac_dc1 = offset ? offset : (-128 - offset);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset ? offset : (-128 - offset));
     } else if (channel == DAC_CHANNEL_2) {
         if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_CW_PHASE_180) {
             offset = 0 - offset;
         }
-        SENS.sar_dac_ctrl2.dac_dc2 = offset ? offset : (-128 - offset);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset ? offset : (-128 - offset));
     }
 }
 
diff --git a/components/hal/esp32s2/include/hal/dedic_gpio_ll.h b/components/hal/esp32s2/include/hal/dedic_gpio_ll.h
index 3cbf29b7bb..8fcdd0e7a6 100644
--- a/components/hal/esp32s2/include/hal/dedic_gpio_ll.h
+++ b/components/hal/esp32s2/include/hal/dedic_gpio_ll.h
@@ -19,6 +19,7 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/dedic_gpio_struct.h"
 
 static inline void dedic_gpio_ll_enable_instruction_access_out(dedic_dev_t *dev, uint32_t channel_mask, bool enable)
@@ -61,12 +62,12 @@ static inline void dedic_gpio_ll_toggle_channel(dedic_dev_t *dev, uint32_t chann
 
 static inline uint32_t dedic_gpio_ll_read_out_all(dedic_dev_t *dev)
 {
-    return dev->gpio_out_scan.gpio_out_status;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->gpio_out_scan, gpio_out_status);
 }
 
 static inline uint32_t dedic_gpio_ll_read_in_all(dedic_dev_t *dev)
 {
-    return dev->gpio_in_scan.gpio_in_status;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->gpio_in_scan, gpio_in_status);
 }
 
 static inline void dedic_gpio_ll_set_input_delay(dedic_dev_t *dev, uint32_t channel, uint32_t delay_cpu_clks)
diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h
index d6330db630..34cdc464bc 100644
--- a/components/hal/esp32s2/include/hal/gpio_ll.h
+++ b/components/hal/esp32s2/include/hal/gpio_ll.h
@@ -26,6 +26,7 @@
 #include "soc/gpio_periph.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/rtc_io_reg.h"
+#include "soc/gpio_struct.h"
 #include "hal/gpio_types.h"
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32s2/include/hal/gpspi_flash_ll.h b/components/hal/esp32s2/include/hal/gpspi_flash_ll.h
index 6f7d441c06..79fc727bdd 100644
--- a/components/hal/esp32s2/include/hal/gpspi_flash_ll.h
+++ b/components/hal/esp32s2/include/hal/gpspi_flash_ll.h
@@ -24,11 +24,13 @@
 
 #include <stdlib.h>
 #include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
 #include <sys/param.h> // For MIN/MAX
 #include <stdbool.h>
 #include <string.h>
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -357,7 +359,7 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
-    dev->user1.usr_dummy_cyclelen = dummy_n - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
 }
 
 /**
diff --git a/components/hal/esp32s2/include/hal/i2c_ll.h b/components/hal/esp32s2/include/hal/i2c_ll.h
index 81fb326b55..1d2b8a0c13 100644
--- a/components/hal/esp32s2/include/hal/i2c_ll.h
+++ b/components/hal/esp32s2/include/hal/i2c_ll.h
@@ -16,6 +16,7 @@
 
 #pragma once
 #include "soc/i2c_periph.h"
+#include "soc/i2c_struct.h"
 #include "hal/i2c_types.h"
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32s2/include/hal/i2s_ll.h b/components/hal/esp32s2/include/hal/i2s_ll.h
index 810ee64c7b..725d4343b2 100644
--- a/components/hal/esp32s2/include/hal/i2s_ll.h
+++ b/components/hal/esp32s2/include/hal/i2s_ll.h
@@ -23,7 +23,9 @@
 #pragma once
 
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/i2s_periph.h"
+#include "soc/i2s_struct.h"
 #include "hal/i2s_types.h"
 
 #ifdef __cplusplus
@@ -268,7 +270,7 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  */
 static inline void i2s_ll_tx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
 {
-    hw->clkm_conf.clkm_div_num = set->mclk_div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, set->mclk_div);
     hw->clkm_conf.clkm_div_b = set->b;
     hw->clkm_conf.clkm_div_a = set->a;
 }
@@ -292,7 +294,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  */
 static inline void i2s_ll_rx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
 {
-    hw->clkm_conf.clkm_div_num = set->mclk_div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, set->mclk_div);
     hw->clkm_conf.clkm_div_b = set->b;
     hw->clkm_conf.clkm_div_a = set->a;
 }
diff --git a/components/hal/esp32s2/include/hal/ledc_ll.h b/components/hal/esp32s2/include/hal/ledc_ll.h
index 19d61f127f..677a2e36d3 100644
--- a/components/hal/esp32s2/include/hal/ledc_ll.h
+++ b/components/hal/esp32s2/include/hal/ledc_ll.h
@@ -19,6 +19,7 @@
 
 #include "hal/ledc_types.h"
 #include "soc/ledc_periph.h"
+#include "soc/ledc_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/hal/esp32s2/include/hal/mwdt_ll.h b/components/hal/esp32s2/include/hal/mwdt_ll.h
index 2d9fcd9850..6d50f740b6 100644
--- a/components/hal/esp32s2/include/hal/mwdt_ll.h
+++ b/components/hal/esp32s2/include/hal/mwdt_ll.h
@@ -24,6 +24,7 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
 #include "hal/wdt_types.h"
 #include "esp_attr.h"
 
diff --git a/components/hal/esp32s2/include/hal/rmt_ll.h b/components/hal/esp32s2/include/hal/rmt_ll.h
index 0354afc766..958fe7aef5 100644
--- a/components/hal/esp32s2/include/hal/rmt_ll.h
+++ b/components/hal/esp32s2/include/hal/rmt_ll.h
@@ -15,6 +15,7 @@
 
 #include <stdbool.h>
 #include <stddef.h>
+#include "hal/misc.h"
 #include "soc/rmt_struct.h"
 
 #ifdef __cplusplus
@@ -126,23 +127,23 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel
 
 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->conf_ch[channel].conf0.div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
 }
 
 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->conf_ch[channel].conf0.div_cnt = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
 }
 
 static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    uint32_t div = dev->conf_ch[channel].conf0.div_cnt;
+    uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
     return div == 0 ? 256 : div;
 }
 
 static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    uint32_t div = dev->conf_ch[channel].conf0.div_cnt;
+    uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
     return div == 0 ? 256 : div;
 }
 
@@ -153,12 +154,12 @@ static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, b
 
 static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->conf_ch[channel].conf0.idle_thres = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres, thres);
 }
 
 static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->conf_ch[channel].conf0.idle_thres;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres);
 }
 
 static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
@@ -219,7 +220,7 @@ static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, boo
 
 static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->conf_ch[channel].conf1.rx_filter_thres = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres, thres);
 }
 
 static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -415,14 +416,14 @@ static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
 
 static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->carrier_duty_ch[channel].high;
-    *low_ticks = dev->carrier_duty_ch[channel].low;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], high);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->carrier_duty_ch[channel], low);
 }
 
 static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->ch_rx_carrier_rm[channel].carrier_high_thres_ch;
-    *low_ticks = dev->ch_rx_carrier_rm[channel].carrier_low_thres_ch;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_high_thres_ch);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_low_thres_ch);
 }
 
 static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
diff --git a/components/hal/esp32s2/include/hal/rtc_io_ll.h b/components/hal/esp32s2/include/hal/rtc_io_ll.h
index c519f70030..cdd19466b6 100644
--- a/components/hal/esp32s2/include/hal/rtc_io_ll.h
+++ b/components/hal/esp32s2/include/hal/rtc_io_ll.h
@@ -22,6 +22,8 @@
 
 #include <stdlib.h>
 #include "soc/rtc_io_periph.h"
+#include "soc/rtc_io_struct.h"
+#include "soc/sens_struct.h"
 #include "hal/rtc_io_types.h"
 #include "hal/gpio_types.h"
 
diff --git a/components/hal/esp32s2/include/hal/rwdt_ll.h b/components/hal/esp32s2/include/hal/rwdt_ll.h
index 681c2fdf4f..f3cc3c0cc4 100644
--- a/components/hal/esp32s2/include/hal/rwdt_ll.h
+++ b/components/hal/esp32s2/include/hal/rwdt_ll.h
@@ -23,8 +23,10 @@ extern "C" {
 
 #include <stdlib.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "hal/wdt_types.h"
 #include "soc/rtc_cntl_periph.h"
+#include "soc/rtc_cntl_struct.h"
 #include "soc/efuse_reg.h"
 #include "esp_attr.h"
 
@@ -239,7 +241,7 @@ FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rtc_cntl_dev_t* hw, bool enable
  */
 FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rtc_cntl_dev_t *hw, uint32_t width)
 {
-    hw->wdt_config0.chip_reset_width = width;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config0, chip_reset_width, width);
 }
 
 /**
diff --git a/components/hal/esp32s2/include/hal/sigmadelta_ll.h b/components/hal/esp32s2/include/hal/sigmadelta_ll.h
index e06464a5ff..20406e19fd 100644
--- a/components/hal/esp32s2/include/hal/sigmadelta_ll.h
+++ b/components/hal/esp32s2/include/hal/sigmadelta_ll.h
@@ -22,7 +22,9 @@
 #pragma once
 
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/sigmadelta_periph.h"
+#include "soc/gpio_sd_struct.h"
 #include "hal/sigmadelta_types.h"
 
 #ifdef __cplusplus
@@ -53,7 +55,7 @@ static inline void sigmadelta_ll_set_en(gpio_sd_dev_t *hw, bool en)
  */
 static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, int8_t duty)
 {
-    hw->channel[channel].duty = duty;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)duty);
 }
 
 /**
@@ -65,7 +67,7 @@ static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_
  */
 static inline void sigmadelta_ll_set_prescale(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, uint8_t prescale)
 {
-    hw->channel[channel].prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale);
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h
index 894fa9affe..b81b36c53b 100644
--- a/components/hal/esp32s2/include/hal/spi_ll.h
+++ b/components/hal/esp32s2/include/hal/spi_ll.h
@@ -27,6 +27,7 @@
 #include "esp_types.h"
 #include "esp_attr.h"
 #include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
 #include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
@@ -734,7 +735,7 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
-    hw->user1.usr_dummy_cyclelen = dummy_n - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
 }
 
 /**
@@ -895,13 +896,13 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 {
     if (lsbfirst) {
         // The output command start from bit0 to bit 15, kept as is.
-        hw->user2.usr_command_value = cmd;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd);
     } else {
         /* Output command will be sent from bit 7 to 0 of command_value, and
          * then bit 15 to 8 of the same register field. Shift and swap to send
          * more straightly.
          */
-        hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen));
 
     }
 }
@@ -1071,7 +1072,7 @@ static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw)
 
 static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
 {
-    return hw->slave1.last_addr;
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->slave1, last_addr);
 }
 
 /*------------------------------------------------------------------------------
diff --git a/components/hal/esp32s2/include/hal/spimem_flash_ll.h b/components/hal/esp32s2/include/hal/spimem_flash_ll.h
index b04020eb51..2bbd6e90ff 100644
--- a/components/hal/esp32s2/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32s2/include/hal/spimem_flash_ll.h
@@ -28,6 +28,7 @@
 #include <string.h>
 
 #include "soc/spi_periph.h"
+#include "soc/spi_mem_struct.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
 
@@ -167,7 +168,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3
  */
 static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd)
 {
-    dev->flash_sus_ctrl.flash_pes_command = sus_cmd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, flash_pes_command, sus_cmd);
 }
 
 /**
@@ -179,7 +180,7 @@ static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_
  */
 static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd)
 {
-    dev->flash_sus_ctrl.flash_per_command = res_cmd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, flash_per_command, res_cmd);
 }
 
 /**
@@ -226,7 +227,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool
  */
 static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti)
 {
-    dev->flash_waiti_ctrl.waiti_cmd = 0x05; // Set the command to send, to fetch flash status reg value.
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05); // Set the command to send, to fetch flash status reg value.
     dev->flash_waiti_ctrl.waiti_en = auto_waiti;  // enable auto wait-idle function.
 }
 
@@ -516,7 +517,7 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
-    dev->user1.usr_dummy_cyclelen = dummy_n - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
 }
 
 /**
diff --git a/components/hal/esp32s2/include/hal/timer_ll.h b/components/hal/esp32s2/include/hal/timer_ll.h
index cc728169ec..59921e2364 100644
--- a/components/hal/esp32s2/include/hal/timer_ll.h
+++ b/components/hal/esp32s2/include/hal/timer_ll.h
@@ -22,7 +22,9 @@ extern "C" {
 #endif
 
 #include <stdlib.h>
+#include "hal/misc.h"
 #include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
 #include "hal/timer_types.h"
 #include "hal/assert.h"
 
@@ -50,7 +52,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
     }
     int timer_en = hw->hw_timer[timer_num].config.tx_en;
     hw->hw_timer[timer_num].config.tx_en = 0;
-    hw->hw_timer[timer_num].config.tx_divider = divider;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
     hw->hw_timer[timer_num].config.tx_en = timer_en;
 }
 
@@ -65,7 +67,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
  */
 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
 {
-    uint32_t d = hw->hw_timer[timer_num].config.tx_divider;
+    uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider);
     if (d == 0) {
         d = 65536;
     } else if (d == 1) {
diff --git a/components/hal/esp32s2/include/hal/touch_sensor_ll.h b/components/hal/esp32s2/include/hal/touch_sensor_ll.h
index 2fa8227153..30c3cc1014 100644
--- a/components/hal/esp32s2/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32s2/include/hal/touch_sensor_ll.h
@@ -24,8 +24,12 @@
 
 #include <stdlib.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/touch_sensor_periph.h"
 #include "soc/soc_caps.h"
+#include "soc/sens_struct.h"
+#include "soc/rtc_cntl_struct.h"
+#include "soc/rtc_io_struct.h"
 #include "hal/touch_sensor_types.h"
 
 #ifdef __cplusplus
@@ -47,9 +51,9 @@ extern "C" {
 static inline void touch_ll_set_meas_times(uint16_t meas_time)
 {
     //The times of charge and discharge in each measure process of touch channels.
-    RTCCNTL.touch_ctrl1.touch_meas_num = meas_time;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_meas_num, meas_time);
     //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
-    RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX; //wait volt stable
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl2, touch_xpd_wait, SOC_TOUCH_PAD_MEASURE_WAIT_MAX); //wait volt stable
 }
 
 /**
@@ -59,7 +63,7 @@ static inline void touch_ll_set_meas_times(uint16_t meas_time)
  */
 static inline void touch_ll_get_measure_times(uint16_t *meas_time)
 {
-    *meas_time = RTCCNTL.touch_ctrl1.touch_meas_num;
+    *meas_time = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_meas_num);
 }
 
 /**
@@ -73,7 +77,7 @@ static inline void touch_ll_get_measure_times(uint16_t *meas_time)
 static inline void touch_ll_set_sleep_time(uint16_t sleep_time)
 {
     // touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK(90k)
-    RTCCNTL.touch_ctrl1.touch_sleep_cycles = sleep_time;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_sleep_cycles, sleep_time);
 }
 
 /**
@@ -83,7 +87,7 @@ static inline void touch_ll_set_sleep_time(uint16_t sleep_time)
  */
 static inline void touch_ll_get_sleep_time(uint16_t *sleep_time)
 {
-    *sleep_time = RTCCNTL.touch_ctrl1.touch_sleep_cycles;
+    *sleep_time = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_sleep_cycles);
 }
 
 /**
@@ -990,7 +994,7 @@ static inline void touch_ll_proximity_get_channel_num(touch_pad_t prox_pad[])
  */
 static inline void touch_ll_proximity_set_meas_times(uint32_t times)
 {
-    RTCCNTL.touch_approach.touch_approach_meas_time = times;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time, times);
 }
 
 /**
@@ -1000,7 +1004,7 @@ static inline void touch_ll_proximity_set_meas_times(uint32_t times)
  */
 static inline void touch_ll_proximity_get_meas_times(uint32_t *times)
 {
-    *times = RTCCNTL.touch_approach.touch_approach_meas_time;
+    *times = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time);
 }
 
 /**
@@ -1011,11 +1015,11 @@ static inline void touch_ll_proximity_get_meas_times(uint32_t *times)
 static inline void touch_ll_proximity_read_meas_cnt(touch_pad_t touch_num, uint32_t *cnt)
 {
     if (SENS.sar_touch_conf.touch_approach_pad0 == touch_num) {
-        *cnt = SENS.sar_touch_appr_status.touch_approach_pad0_cnt;
+        *cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad0_cnt);
     } else if (SENS.sar_touch_conf.touch_approach_pad1 == touch_num) {
-        *cnt = SENS.sar_touch_appr_status.touch_approach_pad1_cnt;
+        *cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad1_cnt);
     } else if (SENS.sar_touch_conf.touch_approach_pad2 == touch_num) {
-        *cnt = SENS.sar_touch_appr_status.touch_approach_pad2_cnt;
+        *cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad2_cnt);
     }
 }
 
@@ -1163,7 +1167,7 @@ static inline void touch_ll_sleep_read_debounce(uint32_t *debounce)
  */
 static inline void touch_ll_sleep_read_proximity_cnt(uint32_t *approach_cnt)
 {
-    *approach_cnt = SENS.sar_touch_appr_status.touch_slp_approach_cnt;
+    *approach_cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_slp_approach_cnt);
 }
 
 /**
diff --git a/components/hal/esp32s2/include/hal/twai_ll.h b/components/hal/esp32s2/include/hal/twai_ll.h
index 106f3adc6f..7a04c18aef 100644
--- a/components/hal/esp32s2/include/hal/twai_ll.h
+++ b/components/hal/esp32s2/include/hal/twai_ll.h
@@ -31,6 +31,7 @@ extern "C" {
 #include "hal/misc.h"
 #include "hal/twai_types.h"
 #include "soc/twai_periph.h"
+#include "soc/twai_struct.h"
 
 /* ------------------------- Defines and Typedefs --------------------------- */
 
@@ -399,7 +400,7 @@ static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw)
  */
 static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl)
 {
-    hw->error_warning_limit_reg.ewl = ewl;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl);
 }
 
 /**
@@ -439,7 +440,7 @@ static inline uint32_t twai_ll_get_rec(twai_dev_t *hw)
  */
 static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec)
 {
-    hw->rx_error_counter_reg.rxerr = rec;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec);
 }
 
 /* ------------------------ TX Error Count Register ------------------------- */
@@ -467,7 +468,7 @@ static inline uint32_t twai_ll_get_tec(twai_dev_t *hw)
  */
 static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
 {
-    hw->tx_error_counter_reg.txerr = tec;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec);
 }
 
 /* ---------------------- Acceptance Filter Registers ----------------------- */
@@ -486,8 +487,8 @@ static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_
     uint32_t code_swapped = HAL_SWAP32(code);
     uint32_t mask_swapped = HAL_SWAP32(mask);
     for (int i = 0; i < 4; i++) {
-        hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
-        hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0xFF));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0xFF));
     }
     hw->mode_reg.afm = single_filter;
 }
@@ -522,7 +523,7 @@ static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t
 {
     //Copy RX buffer registers into frame
     for (int i = 0; i < 13; i++) {
-        rx_frame->bytes[i] =  hw->tx_rx_buffer[i].byte;
+        rx_frame->bytes[i] =  HAL_FORCE_READ_U32_REG_FIELD(hw->tx_rx_buffer[i], byte);
     }
 }
 
@@ -652,14 +653,14 @@ static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider)
 {
     if (divider >= 2 && divider <= 490) {
         hw->clock_divider_reg.co = 0;
-        hw->clock_divider_reg.cd = (divider / 2) - 1;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1);
     } else if (divider == 1) {
         //Setting the divider reg to max value (255) means a divider of 1
         hw->clock_divider_reg.co = 0;
-        hw->clock_divider_reg.cd = 255;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255);
     } else {
         hw->clock_divider_reg.co = 1;
-        hw->clock_divider_reg.cd = 0;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0);
     }
 }
 
diff --git a/components/hal/esp32s2/include/hal/uart_ll.h b/components/hal/esp32s2/include/hal/uart_ll.h
index 15b96f8bed..9309d3b8f2 100644
--- a/components/hal/esp32s2/include/hal/uart_ll.h
+++ b/components/hal/esp32s2/include/hal/uart_ll.h
@@ -17,8 +17,11 @@
 
 
 #pragma once
+
+#include "hal/misc.h"
 #include "hal/uart_types.h"
 #include "soc/uart_periph.h"
+#include "soc/uart_struct.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -403,7 +406,7 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num
 FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
 {
     if(break_num > 0) {
-        hw->idle_conf.tx_brk_num = break_num;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->idle_conf, tx_brk_num, break_num);
         hw->conf0.txd_brk = 1;
     } else {
         hw->conf0.txd_brk = 0;
@@ -470,8 +473,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
         hw->flow_conf.sw_flow_con_en = 1;
         hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
         hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd;
-        hw->swfc_conf1.xon_char = flow_ctrl->xon_char;
-        hw->swfc_conf0.xoff_char = flow_ctrl->xoff_char;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char);
     } else {
         hw->flow_conf.sw_flow_con_en = 0;
         hw->flow_conf.xonoff_del = 0;
@@ -493,11 +496,11 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
  */
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
-    hw->at_cmd_char.data = cmd_char->cmd_char;
-    hw->at_cmd_char.char_num = cmd_char->char_num;
-    hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle;
-    hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle;
-    hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout);
 }
 
 /**
@@ -679,8 +682,8 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
  */
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
-    *cmd_char = hw->at_cmd_char.data;
-    *char_num = hw->at_cmd_char.char_num;
+    *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
 }
 
 /**
diff --git a/components/hal/esp32s3/include/hal/adc_ll.h b/components/hal/esp32s3/include/hal/adc_ll.h
index 58302045e5..c554e6cf4b 100644
--- a/components/hal/esp32s3/include/hal/adc_ll.h
+++ b/components/hal/esp32s3/include/hal/adc_ll.h
@@ -18,9 +18,11 @@
 #include "soc/adc_periph.h"
 #include "hal/adc_types.h"
 #include "soc/apb_saradc_struct.h"
+#include "soc/sens_struct.h"
 #include "soc/apb_saradc_reg.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -109,11 +111,11 @@ typedef struct {
 static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
 {
     // Internal FSM reset wait time
-    APB_SARADC.fsm_wait.rstb_wait = rst_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait);
     // Internal FSM start wait time
-    APB_SARADC.fsm_wait.xpd_wait = start_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait);
     // Internal FSM standby wait time
-    APB_SARADC.fsm_wait.standby_wait = standby_wait;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait);
 }
 
 /**
@@ -138,7 +140,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
-    APB_SARADC.ctrl.sar_clk_div = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div);
 }
 
 /**
@@ -149,7 +151,7 @@ static inline void adc_ll_digi_set_clk_div(uint32_t div)
  */
 static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
 {
-    APB_SARADC.ctrl2.max_meas_num = meas_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num);
 }
 
 /**
@@ -307,7 +309,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  */
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
-    APB_SARADC.apb_adc_clkm_conf.clkm_div_num = div_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num);
     APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b;
     APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a;
 }
@@ -450,7 +452,7 @@ static inline void adc_ll_digi_monitor_enable(adc_ll_num_t adc_n, bool enable)
  */
 static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
 {
-    APB_SARADC.dma_conf.apb_adc_eof_num = num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num);
 }
 
 /**
@@ -765,9 +767,9 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
 static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
 {
     if (adc_n == ADC_NUM_1) {
-        SENS.sar_reader1_ctrl.sar1_clk_div = div;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div);
     } else { // adc_n == ADC_NUM_2
-        SENS.sar_reader2_ctrl.sar2_clk_div = div;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div);
     }
 }
 
@@ -828,7 +830,7 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
 static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
 {
     if (adc_n == ADC_NUM_1) {
-        while (SENS.sar_slave_addr1.meas_status != 0);
+        while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {}
         SENS.sar_meas1_ctrl2.meas1_start_sar = 0;
         SENS.sar_meas1_ctrl2.meas1_start_sar = 1;
     } else { // adc_n == ADC_NUM_2
@@ -867,9 +869,9 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
 {
     int ret_val = 0;
     if (adc_n == ADC_NUM_1) {
-        ret_val = SENS.sar_meas1_ctrl2.meas1_data_sar;
+        ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas1_ctrl2, meas1_data_sar);
     } else { // adc_n == ADC_NUM_2
-        ret_val = SENS.sar_meas2_ctrl2.meas2_data_sar;
+        ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas2_ctrl2, meas2_data_sar);
     }
     return ret_val;
 }
diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h
index 0b054bf25d..2248c41afc 100644
--- a/components/hal/esp32s3/include/hal/gpio_ll.h
+++ b/components/hal/esp32s3/include/hal/gpio_ll.h
@@ -28,6 +28,7 @@
 #include "soc/rtc_io_reg.h"
 #include "soc/usb_serial_jtag_reg.h"
 #include "hal/gpio_types.h"
+#include "soc/gpio_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/hal/esp32s3/include/hal/gpspi_flash_ll.h b/components/hal/esp32s3/include/hal/gpspi_flash_ll.h
index 6669db4be2..47f11e637a 100644
--- a/components/hal/esp32s3/include/hal/gpspi_flash_ll.h
+++ b/components/hal/esp32s3/include/hal/gpspi_flash_ll.h
@@ -24,11 +24,13 @@
 
 #include <stdlib.h>
 #include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
 #include <sys/param.h> // For MIN/MAX
 #include <stdbool.h>
 #include <string.h>
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -369,7 +371,7 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
 static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
 {
     dev->user.usr_dummy = dummy_n ? 1 : 0;
-    dev->user1.usr_dummy_cyclelen = dummy_n - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1)
 }
 
 /**
diff --git a/components/hal/esp32s3/include/hal/i2c_ll.h b/components/hal/esp32s3/include/hal/i2c_ll.h
index 566ada8b3f..eae2a660fb 100644
--- a/components/hal/esp32s3/include/hal/i2c_ll.h
+++ b/components/hal/esp32s3/include/hal/i2c_ll.h
@@ -15,8 +15,11 @@
 // The LL layer for I2C register operations
 
 #pragma once
+
+#include "hal/misc.h"
 #include "soc/i2c_periph.h"
 #include "soc/soc_caps.h"
+#include "soc/i2c_struct.h"
 #include "hal/i2c_types.h"
 
 #ifdef __cplusplus
@@ -148,7 +151,7 @@ static inline void i2c_ll_update(i2c_dev_t *hw)
  */
 static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg)
 {
-    hw->clk_conf.sclk_div_num = bus_cfg->clkm_div - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1);
     //scl period
     hw->scl_low_period.scl_low_period = bus_cfg->scl_low - 1;
     hw->scl_high_period.scl_high_period = bus_cfg->scl_high;
@@ -574,7 +577,7 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l
 static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for (int i = 0; i< len; i++) {
-        hw->data.fifo_rdata = ptr[i];
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]);
     }
 }
 
@@ -590,7 +593,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
     for(int i = 0; i < len; i++) {
-        ptr[i] = hw->data.fifo_rdata;
+        ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->data, fifo_rdata);
     }
 }
 
diff --git a/components/hal/esp32s3/include/hal/i2s_ll.h b/components/hal/esp32s3/include/hal/i2s_ll.h
index 4dff8f3a12..791918fae0 100644
--- a/components/hal/esp32s3/include/hal/i2s_ll.h
+++ b/components/hal/esp32s3/include/hal/i2s_ll.h
@@ -21,7 +21,9 @@
 
 #pragma once
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/i2s_periph.h"
+#include "soc/i2s_struct.h"
 #include "hal/i2s_types.h"
 
 #ifdef __cplusplus
@@ -221,7 +223,7 @@ static inline void i2s_ll_tx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
             hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
         }
     }
-    hw->tx_clkm_conf.tx_clkm_div_num = set->mclk_div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, set->mclk_div);
 }
 
 /**
@@ -260,7 +262,7 @@ static inline void i2s_ll_rx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
             hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
         }
     }
-    hw->rx_clkm_conf.rx_clkm_div_num = set->mclk_div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, set->mclk_div);
 }
 
 /**
@@ -555,7 +557,7 @@ static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw)
  */
 static inline void i2s_ll_tx_set_pdm_prescale(i2s_dev_t *hw, bool prescale)
 {
-    hw->tx_pcm2pdm_conf.tx_prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_pcm2pdm_conf, tx_prescale, prescale);
 }
 
 /**
diff --git a/components/hal/esp32s3/include/hal/lcd_ll.h b/components/hal/esp32s3/include/hal/lcd_ll.h
index d93abb3672..1d95d9e125 100644
--- a/components/hal/esp32s3/include/hal/lcd_ll.h
+++ b/components/hal/esp32s3/include/hal/lcd_ll.h
@@ -15,6 +15,7 @@
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/lcd_cam_reg.h"
 #include "soc/lcd_cam_struct.h"
 #include "hal/assert.h"
@@ -47,7 +48,7 @@ static inline void lcd_ll_set_group_clock_src(lcd_cam_dev_t *dev, int src, int d
     // lcd_clk = module_clock_src / (div_num + div_b / div_a)
     HAL_ASSERT(div_num >= 2);
     dev->lcd_clock.lcd_clk_sel = src;
-    dev->lcd_clock.lcd_clkm_div_num = div_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lcd_clock, lcd_clkm_div_num, div_num);
     dev->lcd_clock.lcd_clkm_div_a = div_a;
     dev->lcd_clock.lcd_clkm_div_b = div_b;
 }
@@ -188,7 +189,7 @@ static inline void lcd_ll_enable_output_hsync_in_porch_region(lcd_cam_dev_t *dev
 
 static inline void lcd_ll_set_hsync_position(lcd_cam_dev_t *dev, uint32_t offset_in_line)
 {
-    dev->lcd_ctrl2.lcd_hsync_position = offset_in_line;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lcd_ctrl2, lcd_hsync_position, offset_in_line);
 }
 
 static inline void lcd_ll_set_horizontal_timing(lcd_cam_dev_t *dev, uint32_t hsw, uint32_t hbp, uint32_t active_width, uint32_t hfp)
@@ -202,7 +203,7 @@ static inline void lcd_ll_set_horizontal_timing(lcd_cam_dev_t *dev, uint32_t hsw
 static inline void lcd_ll_set_vertical_timing(lcd_cam_dev_t *dev, uint32_t vsw, uint32_t vbp, uint32_t active_height, uint32_t vfp)
 {
     dev->lcd_ctrl2.lcd_vsync_width = vsw - 1;
-    dev->lcd_ctrl1.lcd_vb_front = vbp + vsw - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lcd_ctrl1, lcd_vb_front, vbp + vsw - 1);
     dev->lcd_ctrl.lcd_va_height = active_height - 1;
     dev->lcd_ctrl.lcd_vt_height = vsw + vbp + active_height + vfp - 1;
 }
diff --git a/components/hal/esp32s3/include/hal/ledc_ll.h b/components/hal/esp32s3/include/hal/ledc_ll.h
index eafae904ba..fb495b0319 100644
--- a/components/hal/esp32s3/include/hal/ledc_ll.h
+++ b/components/hal/esp32s3/include/hal/ledc_ll.h
@@ -19,6 +19,7 @@
 
 #include "hal/ledc_types.h"
 #include "soc/ledc_periph.h"
+#include "soc/ledc_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/hal/esp32s3/include/hal/mcpwm_ll.h b/components/hal/esp32s3/include/hal/mcpwm_ll.h
index 958a1c31f4..ddd66b144d 100644
--- a/components/hal/esp32s3/include/hal/mcpwm_ll.h
+++ b/components/hal/esp32s3/include/hal/mcpwm_ll.h
@@ -23,6 +23,7 @@
 #pragma once
 
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/soc_caps.h"
 #include "soc/mcpwm_struct.h"
 #include "hal/mcpwm_types.h"
@@ -288,9 +289,9 @@ static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int
 static inline void mcpwm_ll_timer_set_peak(mcpwm_dev_t *mcpwm, int timer_id, uint32_t peak, bool symmetric)
 {
     if (!symmetric) { // in asymmetric mode, period = [0,peak-1]
-        mcpwm->timer[timer_id].timer_cfg0.timer_period = peak - 1;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period, peak - 1);
     } else { // in symmetric mode, period = [0,peak-1] + [peak,1]
-        mcpwm->timer[timer_id].timer_cfg0.timer_period = peak;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period, peak);
     }
 }
 
@@ -298,10 +299,10 @@ static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id,
 {
     // asymmetric mode
     if (!symmetric) {
-        return mcpwm->timer[timer_id].timer_cfg0.timer_period + 1;
+        return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + 1;
     }
     // symmetric mode
-    return mcpwm->timer[timer_id].timer_cfg0.timer_period;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period);
 }
 
 static inline void mcpwm_ll_timer_update_period_at_once(mcpwm_dev_t *mcpwm, int timer_id)
@@ -388,13 +389,16 @@ static inline uint32_t mcpwm_ll_timer_get_count_value(mcpwm_dev_t *mcpwm, int ti
     // status.value saves the "next count value", so need an extra round up here to get the current count value according to count mode
     // timer is paused
     if (mcpwm->timer[timer_id].timer_cfg1.timer_mod == 0) {
-        return mcpwm->timer[timer_id].timer_status.timer_value;
+        return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_status, timer_value);
     }
     if (mcpwm->timer[timer_id].timer_status.timer_direction) { // down direction
-        return (mcpwm->timer[timer_id].timer_status.timer_value + 1) % (mcpwm->timer[timer_id].timer_cfg0.timer_period + 1);
+        return (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_status, timer_value) + 1) %
+               (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + 1);
     }
     // up direction
-    return (mcpwm->timer[timer_id].timer_status.timer_value + mcpwm->timer[timer_id].timer_cfg0.timer_period) % (mcpwm->timer[timer_id].timer_cfg0.timer_period + 1);
+    return (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_status, timer_value) +
+                HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period)) %
+           (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + 1);
 }
 
 static inline mcpwm_timer_direction_t mcpwm_ll_timer_get_count_direction(mcpwm_dev_t *mcpwm, int timer_id)
@@ -437,7 +441,7 @@ static inline void mcpwm_ll_timer_trigger_soft_sync(mcpwm_dev_t *mcpwm, int time
 
 static inline void mcpwm_ll_timer_set_sync_phase_value(mcpwm_dev_t *mcpwm, int timer_id, uint32_t phase_value)
 {
-    mcpwm->timer[timer_id].timer_sync.timer_phase = phase_value;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_sync, timer_phase, phase_value);
 }
 
 static inline void mcpwm_ll_timer_set_sync_phase_direction(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_direction_t direction)
@@ -524,12 +528,12 @@ static inline void mcpwm_ll_operator_enable_update_compare_on_sync(mcpwm_dev_t *
 
 static inline void mcpwm_ll_operator_set_compare_value(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, uint32_t compare_value)
 {
-    mcpwm->operator[operator_id].timestamp[compare_id].gen = compare_value;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operator[operator_id].timestamp[compare_id], gen, compare_value);
 }
 
 static inline uint32_t mcpwm_ll_operator_get_compare_value(mcpwm_dev_t *mcpwm, int operator_id, int compare_id)
 {
-    return mcpwm->operator[operator_id].timestamp[compare_id].gen;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->operator[operator_id].timestamp[compare_id], gen);
 }
 
 static inline void mcpwm_ll_operator_update_action_at_once(mcpwm_dev_t *mcpwm, int operator_id)
@@ -728,22 +732,22 @@ static inline uint32_t mcpwm_ll_deadtime_get_switch_topology(mcpwm_dev_t *mcpwm,
 
 static inline void mcpwm_ll_deadtime_set_falling_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t fed)
 {
-    mcpwm->operator[operator_id].dt_fed_cfg.dt_fed = fed - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operator[operator_id].dt_fed_cfg, dt_fed, fed - 1);
 }
 
 static inline uint32_t mcpwm_ll_deadtime_get_falling_delay(mcpwm_dev_t *mcpwm, int operator_id)
 {
-    return mcpwm->operator[operator_id].dt_fed_cfg.dt_fed + 1;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->operator[operator_id].dt_fed_cfg, dt_fed) + 1;
 }
 
 static inline void mcpwm_ll_deadtime_set_rising_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t red)
 {
-    mcpwm->operator[operator_id].dt_red_cfg.dt_red = red - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operator[operator_id].dt_red_cfg, dt_red, red - 1);
 }
 
 static inline uint32_t mcpwm_ll_deadtime_get_rising_delay(mcpwm_dev_t *mcpwm, int operator_id)
 {
-    return mcpwm->operator[operator_id].dt_red_cfg.dt_red + 1;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->operator[operator_id].dt_red_cfg, dt_red) + 1;
 }
 
 static inline void mcpwm_ll_deadtime_update_delay_at_once(mcpwm_dev_t *mcpwm, int operator_id)
@@ -1015,12 +1019,12 @@ static inline bool mcpwm_ll_capture_is_negedge(mcpwm_dev_t *mcpwm, int channel)
 
 static inline void mcpwm_ll_capture_set_prescale(mcpwm_dev_t *mcpwm, int channel, uint32_t prescale)
 {
-    mcpwm->cap_chn_cfg[channel].capn_prescale = prescale - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->cap_chn_cfg[channel], capn_prescale, prescale - 1);
 }
 
 static inline uint32_t mcpwm_ll_capture_get_prescale(mcpwm_dev_t *mcpwm, int channel)
 {
-    return mcpwm->cap_chn_cfg[channel].capn_prescale + 1;
+    return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->cap_chn_cfg[channel], capn_prescale) + 1;
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32s3/include/hal/mwdt_ll.h b/components/hal/esp32s3/include/hal/mwdt_ll.h
index 0d34e2cc87..c15d7b8cd5 100644
--- a/components/hal/esp32s3/include/hal/mwdt_ll.h
+++ b/components/hal/esp32s3/include/hal/mwdt_ll.h
@@ -23,7 +23,9 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
 #include "hal/wdt_types.h"
 #include "esp_attr.h"
 
@@ -219,7 +221,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
  */
 FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
 {
-    hw->wdtconfig1.wdt_clk_prescale = prescaler;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler);
 }
 
 /**
diff --git a/components/hal/esp32s3/include/hal/rmt_ll.h b/components/hal/esp32s3/include/hal/rmt_ll.h
index 0dc87853fa..2ef9273be1 100644
--- a/components/hal/esp32s3/include/hal/rmt_ll.h
+++ b/components/hal/esp32s3/include/hal/rmt_ll.h
@@ -15,6 +15,7 @@
 
 #include <stddef.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/rmt_struct.h"
 
 #ifdef __cplusplus
@@ -57,7 +58,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel,
     // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b)
     dev->sys_conf.sclk_active = 0;
     dev->sys_conf.sclk_sel = src;
-    dev->sys_conf.sclk_div_num = div_num;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sys_conf, sclk_div_num, div_num);
     dev->sys_conf.sclk_div_a = div_a;
     dev->sys_conf.sclk_div_b = div_b;
     dev->sys_conf.sclk_active = 1;
@@ -139,22 +140,22 @@ static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel
 
 static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->chnconf0[channel].div_cnt_n = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_n, div);
 }
 
 static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
 {
-    dev->chmconf[channel].conf0.div_cnt_m = div;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_m, div);
 }
 
 static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->chnconf0[channel].div_cnt_n;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_n);
 }
 
 static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
 {
-    return dev->chmconf[channel].conf0.div_cnt_m;
+    return HAL_FORCE_READ_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_m);
 }
 
 static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -230,7 +231,7 @@ static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, boo
 
 static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
 {
-    dev->chmconf[channel].conf1.rx_filter_thres_m = thres;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf1, rx_filter_thres_m, thres);
 }
 
 static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -440,14 +441,14 @@ static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
 
 static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks )
 {
-    *high_ticks = dev->chncarrier_duty[channel].carrier_high_chn;
-    *low_ticks = dev->chncarrier_duty[channel].carrier_low_chn;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->chncarrier_duty[channel], carrier_high_chn);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->chncarrier_duty[channel], carrier_low_chn);
 }
 
 static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
 {
-    *high_ticks = dev->chm_rx_carrier_rm[channel].carrier_high_thres_chm;
-    *low_ticks = dev->chm_rx_carrier_rm[channel].carrier_low_thres_chm;
+    *high_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->chm_rx_carrier_rm[channel], carrier_high_thres_chm);
+    *low_ticks = HAL_FORCE_READ_U32_REG_FIELD(dev->chm_rx_carrier_rm[channel], carrier_low_thres_chm);
 }
 
 static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
diff --git a/components/hal/esp32s3/include/hal/rtc_io_ll.h b/components/hal/esp32s3/include/hal/rtc_io_ll.h
index 22990e6504..bde6bf3c66 100644
--- a/components/hal/esp32s3/include/hal/rtc_io_ll.h
+++ b/components/hal/esp32s3/include/hal/rtc_io_ll.h
@@ -22,6 +22,7 @@
 
 #include <stdlib.h>
 #include "soc/rtc_io_periph.h"
+#include "soc/rtc_io_struct.h"
 #include "hal/rtc_io_types.h"
 #include "hal/gpio_types.h"
 
diff --git a/components/hal/esp32s3/include/hal/rwdt_ll.h b/components/hal/esp32s3/include/hal/rwdt_ll.h
index 57af63721b..da716126ff 100644
--- a/components/hal/esp32s3/include/hal/rwdt_ll.h
+++ b/components/hal/esp32s3/include/hal/rwdt_ll.h
@@ -25,6 +25,7 @@ extern "C" {
 #include <stdbool.h>
 #include "hal/wdt_types.h"
 #include "soc/rtc_cntl_periph.h"
+#include "soc/rtc_cntl_struct.h"
 #include "soc/efuse_reg.h"
 #include "esp_attr.h"
 
@@ -259,7 +260,7 @@ FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rtc_cntl_dev_t *hw, bool enable
  */
 FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rtc_cntl_dev_t *hw, uint32_t width)
 {
-    hw->wdt_config0.chip_reset_width = width;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config0, chip_reset_width, width);
 }
 
 /**
diff --git a/components/hal/esp32s3/include/hal/sigmadelta_ll.h b/components/hal/esp32s3/include/hal/sigmadelta_ll.h
index 99d75853c5..ecae8cf352 100644
--- a/components/hal/esp32s3/include/hal/sigmadelta_ll.h
+++ b/components/hal/esp32s3/include/hal/sigmadelta_ll.h
@@ -23,7 +23,9 @@
 
 #include <stdbool.h>
 #include "soc/sigmadelta_periph.h"
+#include "soc/gpio_sd_struct.h"
 #include "hal/sigmadelta_types.h"
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -53,7 +55,7 @@ static inline void sigmadelta_ll_set_en(gpio_sd_dev_t *hw, bool en)
  */
 static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, int8_t duty)
 {
-    hw->channel[channel].duty = duty;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint8_t)duty);
 }
 
 /**
@@ -65,7 +67,7 @@ static inline void sigmadelta_ll_set_duty(gpio_sd_dev_t *hw, sigmadelta_channel_
  */
 static inline void sigmadelta_ll_set_prescale(gpio_sd_dev_t *hw, sigmadelta_channel_t channel, uint8_t prescale)
 {
-    hw->channel[channel].prescale = prescale;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale);
 }
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32s3/include/hal/spi_ll.h b/components/hal/esp32s3/include/hal/spi_ll.h
index c67cf1351c..bc4a68b6bf 100644
--- a/components/hal/esp32s3/include/hal/spi_ll.h
+++ b/components/hal/esp32s3/include/hal/spi_ll.h
@@ -27,6 +27,7 @@
 #include "esp_attr.h"
 #include "esp_types.h"
 #include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
 #include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
@@ -915,13 +916,13 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 {
     if (lsbfirst) {
         // The output command start from bit0 to bit 15, kept as is.
-        hw->user2.usr_command_value = cmd;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd);
     } else {
         /* Output command will be sent from bit 7 to 0 of command_value, and
          * then bit 15 to 8 of the same register field. Shift and swap to send
          * more straightly.
          */
-        hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen));
 
     }
 }
@@ -938,7 +939,7 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b
 static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
 {
     hw->user.usr_dummy = dummy_n ? 1 : 0;
-    hw->user1.usr_dummy_cyclelen = dummy_n - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
 }
 
 /**
diff --git a/components/hal/esp32s3/include/hal/spimem_flash_ll.h b/components/hal/esp32s3/include/hal/spimem_flash_ll.h
index 098c14c4c2..d435cbfaf7 100644
--- a/components/hal/esp32s3/include/hal/spimem_flash_ll.h
+++ b/components/hal/esp32s3/include/hal/spimem_flash_ll.h
@@ -28,6 +28,7 @@
 #include <string.h>
 
 #include "soc/spi_periph.h"
+#include "soc/spi_mem_struct.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
 
@@ -157,7 +158,7 @@ static inline void spimem_flash_ll_auto_resume_init(spi_mem_dev_t *dev, bool aut
  */
 static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd)
 {
-    dev->flash_sus_ctrl.flash_pes_command = sus_cmd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, flash_pes_command, sus_cmd);
 }
 
 /**
@@ -169,7 +170,7 @@ static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_
  */
 static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd)
 {
-    dev->flash_sus_ctrl.flash_per_command = res_cmd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, flash_per_command, res_cmd);
 }
 
 /**
@@ -226,7 +227,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3
  */
 static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti)
 {
-    dev->flash_waiti_ctrl.waiti_cmd = 0x05; // Set the command to send, to fetch flash status reg value.
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05); // Set the command to send, to fetch flash status reg value.
     dev->flash_waiti_ctrl.waiti_en = auto_waiti;  // enable auto wait-idle function.
 }
 
diff --git a/components/hal/esp32s3/include/hal/timer_ll.h b/components/hal/esp32s3/include/hal/timer_ll.h
index de95e437ea..36288f7887 100644
--- a/components/hal/esp32s3/include/hal/timer_ll.h
+++ b/components/hal/esp32s3/include/hal/timer_ll.h
@@ -22,7 +22,9 @@ extern "C" {
 #endif
 
 #include <stdlib.h>
+#include "hal/misc.h"
 #include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
 #include "hal/timer_types.h"
 #include "hal/assert.h"
 
@@ -55,7 +57,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
     }
     int timer_en = hw->hw_timer[timer_num].config.tn_en;
     hw->hw_timer[timer_num].config.tn_en = 0;
-    hw->hw_timer[timer_num].config.tn_divider = divider;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tn_divider, divider);
     hw->hw_timer[timer_num].config.tn_en = timer_en;
 }
 
@@ -70,7 +72,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
  */
 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
 {
-    uint32_t d = hw->hw_timer[timer_num].config.tn_divider;
+    uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, tn_divider);
     if (d == 0) {
         d = 65536;
     } else if (d == 1) {
diff --git a/components/hal/esp32s3/include/hal/touch_sensor_ll.h b/components/hal/esp32s3/include/hal/touch_sensor_ll.h
index 48d62faf47..1d62690be0 100644
--- a/components/hal/esp32s3/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32s3/include/hal/touch_sensor_ll.h
@@ -24,7 +24,11 @@
 
 #include <stdlib.h>
 #include <stdbool.h>
+#include "hal/misc.h"
 #include "soc/touch_sensor_periph.h"
+#include "soc/rtc_cntl_struct.h"
+#include "soc/rtc_io_struct.h"
+#include "soc/sens_struct.h"
 #include "soc/soc_caps.h"
 #include "hal/touch_sensor_types.h"
 
@@ -47,9 +51,9 @@ extern "C" {
 static inline void touch_ll_set_meas_times(uint16_t meas_time)
 {
     //The times of charge and discharge in each measure process of touch channels.
-    RTCCNTL.touch_ctrl1.touch_meas_num = meas_time;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_meas_num, meas_time);
     //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
-    RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX; //wait volt stable
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl2, touch_xpd_wait, SOC_TOUCH_PAD_MEASURE_WAIT_MAX); //wait volt stable
 }
 
 /**
@@ -59,7 +63,7 @@ static inline void touch_ll_set_meas_times(uint16_t meas_time)
  */
 static inline void touch_ll_get_measure_times(uint16_t *meas_time)
 {
-    *meas_time = RTCCNTL.touch_ctrl1.touch_meas_num;
+    *meas_time = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_meas_num);
 }
 
 /**
@@ -73,7 +77,7 @@ static inline void touch_ll_get_measure_times(uint16_t *meas_time)
 static inline void touch_ll_set_sleep_time(uint16_t sleep_time)
 {
     // touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK(150k)
-    RTCCNTL.touch_ctrl1.touch_sleep_cycles = sleep_time;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_sleep_cycles, sleep_time);
 }
 
 /**
@@ -83,7 +87,7 @@ static inline void touch_ll_set_sleep_time(uint16_t sleep_time)
  */
 static inline void touch_ll_get_sleep_time(uint16_t *sleep_time)
 {
-    *sleep_time = RTCCNTL.touch_ctrl1.touch_sleep_cycles;
+    *sleep_time = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_sleep_cycles);
 }
 
 /**
@@ -990,7 +994,7 @@ static inline void touch_ll_proximity_get_channel_num(touch_pad_t prox_pad[])
  */
 static inline void touch_ll_proximity_set_meas_times(uint32_t times)
 {
-    RTCCNTL.touch_approach.touch_approach_meas_time = times;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time, times);
 }
 
 /**
@@ -1000,7 +1004,7 @@ static inline void touch_ll_proximity_set_meas_times(uint32_t times)
  */
 static inline void touch_ll_proximity_get_meas_times(uint32_t *times)
 {
-    *times = RTCCNTL.touch_approach.touch_approach_meas_time;
+    *times = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time);
 }
 
 /**
diff --git a/components/hal/esp32s3/include/hal/twai_ll.h b/components/hal/esp32s3/include/hal/twai_ll.h
index 62941845a4..e9eef59104 100644
--- a/components/hal/esp32s3/include/hal/twai_ll.h
+++ b/components/hal/esp32s3/include/hal/twai_ll.h
@@ -31,6 +31,7 @@ extern "C" {
 #include "hal/misc.h"
 #include "hal/twai_types.h"
 #include "soc/twai_periph.h"
+#include "soc/twai_struct.h"
 
 /* ------------------------- Defines and Typedefs --------------------------- */
 
@@ -399,7 +400,7 @@ static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw)
  */
 static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl)
 {
-    hw->error_warning_limit_reg.ewl = ewl;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl);
 }
 
 /**
@@ -439,7 +440,7 @@ static inline uint32_t twai_ll_get_rec(twai_dev_t *hw)
  */
 static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec)
 {
-    hw->rx_error_counter_reg.rxerr = rec;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec);
 }
 
 /* ------------------------ TX Error Count Register ------------------------- */
@@ -467,7 +468,7 @@ static inline uint32_t twai_ll_get_tec(twai_dev_t *hw)
  */
 static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
 {
-    hw->tx_error_counter_reg.txerr = tec;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec);
 }
 
 /* ---------------------- Acceptance Filter Registers ----------------------- */
@@ -486,8 +487,8 @@ static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_
     uint32_t code_swapped = HAL_SWAP32(code);
     uint32_t mask_swapped = HAL_SWAP32(mask);
     for (int i = 0; i < 4; i++) {
-        hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
-        hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0xFF));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0xFF));
     }
     hw->mode_reg.afm = single_filter;
 }
@@ -522,7 +523,7 @@ static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t
 {
     //Copy RX buffer registers into frame
     for (int i = 0; i < 13; i++) {
-        rx_frame->bytes[i] =  hw->tx_rx_buffer[i].byte;
+        rx_frame->bytes[i] =  HAL_FORCE_READ_U32_REG_FIELD(hw->tx_rx_buffer[i], byte);
     }
 }
 
@@ -652,14 +653,14 @@ static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider)
 {
     if (divider >= 2 && divider <= 490) {
         hw->clock_divider_reg.co = 0;
-        hw->clock_divider_reg.cd = (divider / 2) - 1;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1);
     } else if (divider == 1) {
         //Setting the divider reg to max value (255) means a divider of 1
         hw->clock_divider_reg.co = 0;
-        hw->clock_divider_reg.cd = 255;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255);
     } else {
         hw->clock_divider_reg.co = 1;
-        hw->clock_divider_reg.cd = 0;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0);
     }
 }
 
diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h
index 5570d58bf3..f437c502e0 100644
--- a/components/hal/esp32s3/include/hal/uart_ll.h
+++ b/components/hal/esp32s3/include/hal/uart_ll.h
@@ -17,8 +17,11 @@
 
 
 #pragma once
+
+#include "hal/misc.h"
 #include "hal/uart_types.h"
 #include "soc/uart_periph.h"
+#include "soc/uart_struct.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -149,7 +152,7 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
     // an integer part and a fractional part.
     hw->clkdiv.clkdiv = clk_div >> 4;
     hw->clkdiv.clkdiv_frag = clk_div &  0xf;
-    hw->clk_conf.sclk_div_num = sclk_div - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
 #undef DIV_UP
 }
 
@@ -164,7 +167,8 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
 {
     uint32_t sclk_freq = uart_ll_get_sclk_freq(hw);
     uart_clkdiv_reg_t div_reg = hw->clkdiv;
-    return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * (hw->clk_conf.sclk_div_num + 1));
+    return ((sclk_freq << 4)) /
+        (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1));
 }
 
 /**
@@ -437,7 +441,7 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num
 FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
 {
     if (break_num > 0) {
-        hw->txbrk_conf.tx_brk_num = break_num;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf, tx_brk_num, break_num);
         hw->conf0.txd_brk = 1;
     } else {
         hw->conf0.txd_brk = 0;
@@ -503,8 +507,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
         hw->flow_conf.sw_flow_con_en = 1;
         hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
         hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd;
-        hw->swfc_conf1.xon_char = flow_ctrl->xon_char;
-        hw->swfc_conf0.xoff_char = flow_ctrl->xoff_char;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char);
     } else {
         hw->flow_conf.sw_flow_con_en = 0;
         hw->flow_conf.xonoff_del = 0;
@@ -526,11 +530,11 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
  */
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
-    hw->at_cmd_char.at_cmd_char = cmd_char->cmd_char;
-    hw->at_cmd_char.char_num = cmd_char->char_num;
-    hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle;
-    hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle;
-    hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, at_cmd_char, cmd_char->cmd_char);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout);
 }
 
 /**
@@ -713,8 +717,8 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
  */
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
-    *cmd_char = hw->at_cmd_char.at_cmd_char;
-    *char_num = hw->at_cmd_char.char_num;
+    *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, at_cmd_char);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
 }
 
 /**
diff --git a/components/hal/platform_port/include/hal/misc.h b/components/hal/platform_port/include/hal/misc.h
index 472ec8be2a..3b2f172ab9 100644
--- a/components/hal/platform_port/include/hal/misc.h
+++ b/components/hal/platform_port/include/hal/misc.h
@@ -16,3 +16,23 @@
 #define HAL_SWAP16(d) __builtin_bswap16((d))
 #define HAL_SWAP32(d) __builtin_bswap32((d))
 #define HAL_SWAP64(d) __builtin_bswap64((d))
+
+/** @cond */    //Doxy command to hide preprocessor definitions from docs */
+
+// In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction with size optimization enabled
+// which is not allowed on s2 and later chips (s2, s3, c3, h2)
+// use these wrappers for manually read-modify-write with l32i and s32i
+
+// modify register as uint32_t
+#define HAL_FORCE_MODIFY_U32_REG_FIELD(base_reg, field, val)    \
+{                                                           \
+    typeof(base_reg) temp_reg = (base_reg);                 \
+    temp_reg.field = (val);                                 \
+    (base_reg) = temp_reg;                                  \
+}
+
+// read register as uint32_t
+#define HAL_FORCE_READ_U32_REG_FIELD(base_reg, field)      \
+( ((typeof(base_reg))((base_reg).val)).field )
+
+/** @endcond */
diff --git a/components/soc/esp32/include/soc/emac_dma_struct.h b/components/soc/esp32/include/soc/emac_dma_struct.h
index 35d1361281..1f9a9832e1 100644
--- a/components/soc/esp32/include/soc/emac_dma_struct.h
+++ b/components/soc/esp32/include/soc/emac_dma_struct.h
@@ -20,7 +20,7 @@ extern "C"
 
 #include <stdint.h>
 
-typedef volatile struct {
+typedef volatile struct emac_dma_dev_s {
     union {
         struct {
             uint32_t sw_rst : 1;         /*When this bit is set  the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC  you should read a zero (0) value in this bit.*/
diff --git a/components/soc/esp32/include/soc/emac_ext_struct.h b/components/soc/esp32/include/soc/emac_ext_struct.h
index 9b65c8d91c..5d2e1fecf5 100644
--- a/components/soc/esp32/include/soc/emac_ext_struct.h
+++ b/components/soc/esp32/include/soc/emac_ext_struct.h
@@ -19,7 +19,7 @@ extern "C" {
 
 #include <stdint.h>
 
-typedef volatile struct {
+typedef volatile struct emac_ext_dev_s {
     union {
         struct {
             uint32_t div_num : 4;
diff --git a/components/soc/esp32/include/soc/emac_mac_struct.h b/components/soc/esp32/include/soc/emac_mac_struct.h
index b7f5b80ff5..a798b00f99 100644
--- a/components/soc/esp32/include/soc/emac_mac_struct.h
+++ b/components/soc/esp32/include/soc/emac_mac_struct.h
@@ -19,7 +19,7 @@ extern "C" {
 
 #include <stdint.h>
 
-typedef volatile struct {
+typedef volatile struct emac_mac_dev_s {
     union {
         struct {
             uint32_t pltf : 2;          /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/
diff --git a/components/soc/esp32/include/soc/i2c_struct.h b/components/soc/esp32/include/soc/i2c_struct.h
index 3b17aeb463..7e4afb0601 100644
--- a/components/soc/esp32/include/soc/i2c_struct.h
+++ b/components/soc/esp32/include/soc/i2c_struct.h
@@ -104,8 +104,8 @@ typedef volatile struct i2c_dev_s {
     } fifo_conf;
     union {
         struct {
-            uint8_t data;                           /*The register represent the byte  data read from rx_fifo when use apb fifo access*/
-            uint8_t reserved[3];
+            uint32_t data:              8;          /*The register represent the byte  data read from rx_fifo when use apb fifo access*/
+            uint32_t reserved:          24;
         };
         uint32_t val;
     } fifo_data;
diff --git a/components/soc/esp32/include/soc/pcnt_struct.h b/components/soc/esp32/include/soc/pcnt_struct.h
index caeb02ac23..ecb79f3f4f 100644
--- a/components/soc/esp32/include/soc/pcnt_struct.h
+++ b/components/soc/esp32/include/soc/pcnt_struct.h
@@ -21,7 +21,7 @@ extern "C" {
 #endif
 
 typedef volatile struct pcnt_dev_s {
-    struct{
+    struct {
         union {
             struct {
                 uint32_t filter_thres:  10;         /*This register is used to filter pulse whose width is smaller than this value for unit0.*/
diff --git a/components/soc/esp32/include/soc/rmt_struct.h b/components/soc/esp32/include/soc/rmt_struct.h
index 9736a28a77..fd1815a498 100644
--- a/components/soc/esp32/include/soc/rmt_struct.h
+++ b/components/soc/esp32/include/soc/rmt_struct.h
@@ -24,7 +24,7 @@ typedef volatile struct rmt_dev_s {
     uint32_t data_ch[8];                                /*The R/W ram address for channel0-7 by apb fifo access.
                                                         Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue
                                                         and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/
-    struct{
+    struct {
         union {
             struct {
                 uint32_t div_cnt:        8;             /*This register is used to configure the  frequency divider's factor in channel0-7.*/
@@ -250,9 +250,7 @@ typedef struct rmt_item32_s {
 //Allow access to RMT memory using RMTMEM.chan[0].data32[8]
 typedef volatile struct rmt_mem_s {
     struct {
-        union {
-            rmt_item32_t data32[64];
-        };
+        rmt_item32_t data32[64];
     } chan[8];
 } rmt_mem_t;
 extern rmt_mem_t RMTMEM;
diff --git a/components/soc/esp32/include/soc/sdmmc_struct.h b/components/soc/esp32/include/soc/sdmmc_struct.h
index 8a3bd8fcf6..814a255249 100644
--- a/components/soc/esp32/include/soc/sdmmc_struct.h
+++ b/components/soc/esp32/include/soc/sdmmc_struct.h
@@ -23,18 +23,22 @@ extern "C" {
 #endif
 
 typedef struct sdmmc_desc_s {
-    uint32_t reserved1: 1;
-    uint32_t disable_int_on_completion: 1;
-    uint32_t last_descriptor: 1;
-    uint32_t first_descriptor: 1;
-    uint32_t second_address_chained: 1;
-    uint32_t end_of_ring: 1;
-    uint32_t reserved2: 24;
-    uint32_t card_error_summary: 1;
-    uint32_t owned_by_idmac: 1;
-    uint32_t buffer1_size: 13;
-    uint32_t buffer2_size: 13;
-    uint32_t reserved3: 6;
+    struct {
+        uint32_t reserved1: 1;
+        uint32_t disable_int_on_completion: 1;
+        uint32_t last_descriptor: 1;
+        uint32_t first_descriptor: 1;
+        uint32_t second_address_chained: 1;
+        uint32_t end_of_ring: 1;
+        uint32_t reserved2: 24;
+        uint32_t card_error_summary: 1;
+        uint32_t owned_by_idmac: 1;
+    };
+    struct {
+        uint32_t buffer1_size: 13;
+        uint32_t buffer2_size: 13;
+        uint32_t reserved3: 6;
+    };
     void* buffer1_ptr;
     union {
         void* buffer2_ptr;
@@ -146,8 +150,10 @@ typedef volatile struct sdmmc_dev_s {
         uint32_t val;
     } ctype;
 
-    uint32_t blksiz: 16;        ///< block size, default 0x200
-    uint32_t : 16;
+    struct {
+        uint32_t blksiz: 16;        ///< block size, default 0x200
+        uint32_t reserved: 16;
+    };
 
     uint32_t bytcnt;            ///< number of bytes to be transferred
 
@@ -326,6 +332,7 @@ typedef volatile struct sdmmc_dev_s {
             uint32_t ces: 1;        ///< card error summary
             uint32_t reserved2: 2;
             uint32_t nis: 1;        ///< normal interrupt summary
+            uint32_t ais: 1;        ///< abnormal interrupt summary
             uint32_t fbe_code: 3;   ///< code of fatal bus error
             uint32_t fsm: 4;        ///< DMAC FSM state
             uint32_t reserved3: 15;
@@ -362,6 +369,7 @@ typedef volatile struct sdmmc_dev_s {
             uint32_t write_thr_en : 1;      ///< equivalent of read_thr_en for writes
             uint32_t reserved1 : 13;
             uint32_t card_threshold : 12;   ///< threshold value for reads/writes, in bytes
+            uint32_t reserved28: 4;
         };
         uint32_t val;
     } cardthrctl;
@@ -378,6 +386,7 @@ typedef volatile struct sdmmc_dev_s {
             uint32_t div_factor_p: 4;       ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
             uint32_t div_factor_h: 4;       ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
             uint32_t div_factor_m: 4;       ///< should be equal to div_factor_p
+            uint32_t reserved21: 11;
         };
         uint32_t val;
     } clock;
diff --git a/components/soc/esp32/include/soc/timer_group_struct.h b/components/soc/esp32/include/soc/timer_group_struct.h
index 4ea1abe75d..ec43f6d7a3 100644
--- a/components/soc/esp32/include/soc/timer_group_struct.h
+++ b/components/soc/esp32/include/soc/timer_group_struct.h
@@ -21,7 +21,7 @@ extern "C" {
 #endif
 
 typedef volatile struct timg_dev_s {
-    struct{
+    struct {
         union {
             struct {
                 uint32_t reserved0:   10;
diff --git a/components/soc/esp32/include/soc/twai_struct.h b/components/soc/esp32/include/soc/twai_struct.h
index e9454e1cc5..e4349d33ed 100644
--- a/components/soc/esp32/include/soc/twai_struct.h
+++ b/components/soc/esp32/include/soc/twai_struct.h
@@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
             uint32_t lom: 1;                    /* MOD.1 Listen Only Mode */
             uint32_t stm: 1;                    /* MOD.2 Self Test Mode */
             uint32_t afm: 1;                    /* MOD.3 Acceptance Filter Mode */
-            uint32_t reserved28: 28;            /* Internal Reserved. MOD.4 Sleep Mode not supported */
+            uint32_t reserved4: 28;             /* Internal Reserved. MOD.4 Sleep Mode not supported */
         };
         uint32_t val;
-    } mode_reg;                                 /* Address 0 */
+    } mode_reg;                                 /* Address 0x0000 */
     union {
         struct {
             uint32_t tr: 1;                     /* CMR.0 Transmission Request */
@@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
             uint32_t rrb: 1;                    /* CMR.2 Release Receive Buffer */
             uint32_t cdo: 1;                    /* CMR.3 Clear Data Overrun */
             uint32_t srr: 1;                    /* CMR.4 Self Reception Request */
-            uint32_t reserved27: 27;            /* Internal Reserved */
+            uint32_t reserved5: 27;             /* Internal Reserved */
         };
         uint32_t val;
-    } command_reg;                              /* Address 1 */
+    } command_reg;                              /* Address 0x0004 */
     union {
         struct {
             uint32_t rbs: 1;                    /* SR.0 Receive Buffer Status */
@@ -60,23 +60,24 @@ typedef volatile struct twai_dev_s {
             uint32_t ts: 1;                     /* SR.5 Transmit Status */
             uint32_t es: 1;                     /* SR.6 Error Status */
             uint32_t bs: 1;                     /* SR.7 Bus Status */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } status_reg;                               /* Address 2 */
+    } status_reg;                               /* Address 0x0008 */
     union {
         struct {
             uint32_t ri: 1;                     /* IR.0 Receive Interrupt */
             uint32_t ti: 1;                     /* IR.1 Transmit Interrupt */
             uint32_t ei: 1;                     /* IR.2 Error Interrupt */
-            uint32_t reserved2: 2;              /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
+            uint32_t doi: 1;                    /* IR.3 Data Overrun Interrupt */
+            uint32_t reserved4: 1;              /* Internal Reserved (Wake-up not supported) */
             uint32_t epi: 1;                    /* IR.5 Error Passive Interrupt */
             uint32_t ali: 1;                    /* IR.6 Arbitration Lost Interrupt */
             uint32_t bei: 1;                    /* IR.7 Bus Error Interrupt */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } interrupt_reg;                           /* Address 3 */
+    } interrupt_reg;                           /* Address 0x000C */
     union {
         struct {
             uint32_t rie: 1;                    /* IER.0 Receive Interrupt Enable */
@@ -87,70 +88,70 @@ typedef volatile struct twai_dev_s {
             uint32_t epie: 1;                   /* IER.5 Error Passive Interrupt Enable */
             uint32_t alie: 1;                   /* IER.6 Arbitration Lost Interrupt Enable */
             uint32_t beie: 1;                   /* IER.7 Bus Error Interrupt Enable */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } interrupt_enable_reg;                     /* Address 4 */
-    uint32_t reserved_05;                       /* Address 5 */
+    } interrupt_enable_reg;                     /* Address 0x0010 */
+    uint32_t reserved_14;
     union {
         struct {
             uint32_t brp: 6;                    /* BTR0[5:0] Baud Rate Prescaler */
             uint32_t sjw: 2;                    /* BTR0[7:6] Synchronization Jump Width*/
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } bus_timing_0_reg;                         /* Address 6 */
+    } bus_timing_0_reg;                         /* Address 0x0018 */
     union {
         struct {
             uint32_t tseg1: 4;                  /* BTR1[3:0] Timing Segment 1 */
             uint32_t tseg2: 3;                  /* BTR1[6:4] Timing Segment 2 */
             uint32_t sam: 1;                    /* BTR1.7 Sampling*/
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } bus_timing_1_reg;                         /* Address 7 */
-    uint32_t reserved_08;                       /* Address 8 (Output control not supported) */
-    uint32_t reserved_09;                       /* Address 9 (Test Register not supported) */
-    uint32_t reserved_10;                       /* Address 10 */
+    } bus_timing_1_reg;                         /* Address 0x001C */
+    uint32_t reserved_20;                       /* Address 0x0020 (Output control not supported) */
+    uint32_t reserved_24;                       /* Address 0x0024 (Test Register not supported) */
+    uint32_t reserved_28;                       /* Address 0x0028 */
 
     //Capture and Counter Registers
     union {
         struct {
             uint32_t alc: 5;                    /* ALC[4:0] Arbitration lost capture */
-            uint32_t reserved27: 27;            /* Internal Reserved */
+            uint32_t reserved5: 27;             /* Internal Reserved */
         };
         uint32_t val;
-    } arbitration_lost_captue_reg;              /* Address 11 */
+    } arbitration_lost_captue_reg;              /* Address 0x002C */
     union {
         struct {
             uint32_t seg: 5;                    /* ECC[4:0] Error Code Segment 0 to 5 */
             uint32_t dir: 1;                    /* ECC.5 Error Direction (TX/RX) */
             uint32_t errc: 2;                   /* ECC[7:6] Error Code */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } error_code_capture_reg;                   /* Address 12 */
+    } error_code_capture_reg;                   /* Address 0x0030 */
     union {
         struct {
             uint32_t ewl: 8;                    /* EWL[7:0] Error Warning Limit */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } error_warning_limit_reg;                  /* EWLR[7:0] Error Warning Limit: Address 13 */
+    } error_warning_limit_reg;                  /* Address 0x0034 */
     union {
         struct {
             uint32_t rxerr: 8;                  /* RXERR[7:0] Receive Error Counter */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } rx_error_counter_reg;                     /* Address 12 */
+    } rx_error_counter_reg;                     /* Address 0x0038 */
     union {
         struct {
             uint32_t txerr: 8;                  /* TXERR[7:0] Receive Error Counter */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } tx_error_counter_reg;                     /* Address 15 */
+    } tx_error_counter_reg;                     /* Address 0x003C */
 
     //Shared Registers (TX Buff/RX Buff/Acc Filter)
     union {
@@ -158,47 +159,51 @@ typedef volatile struct twai_dev_s {
             union {
                 struct {
                     uint32_t byte: 8;           /* ACRx[7:0] Acceptance Code */
-                    uint32_t reserved24: 24;    /* Internal Reserved */
+                    uint32_t reserved8: 24;     /* Internal Reserved */
                 };
                 uint32_t val;
             } acr[4];
             union {
                 struct {
                     uint32_t byte: 8;           /* AMRx[7:0] Acceptance Mask */
-                    uint32_t reserved24: 24;    /* Internal Reserved */
+                    uint32_t reserved8: 24;     /* Internal Reserved */
                 };
                 uint32_t val;
             } amr[4];
-            uint32_t reserved32[5];
+            uint32_t reserved_60;
+            uint32_t reserved_64;
+            uint32_t reserved_68;
+            uint32_t reserved_6c;
+            uint32_t reserved_70;
         } acceptance_filter;
         union {
             struct {
-                uint32_t byte: 8;
-                uint32_t reserved24: 24;
+                uint32_t byte: 8;               /* TX/RX Byte X [7:0] */
+                uint32_t reserved24: 24;        /* Internal Reserved */
             };
             uint32_t val;
         } tx_rx_buffer[13];
-    };                                          /* Address 16-28 TX/RX Buffer and Acc Filter*/;
+    };                                          /* Address 0x0040 - 0x0070 */
 
     //Misc Registers
     union {
         struct {
             uint32_t rmc: 7;                    /* RMC[6:0] RX Message Counter */
-            uint32_t reserved25: 25;            /* Internal Reserved */
+            uint32_t reserved7: 25;             /* Internal Reserved */
         };
         uint32_t val;
-    } rx_message_counter_reg;                   /* Address 29 */
-    uint32_t reserved_30;                       /* Address 30 (RX Buffer Start Address not supported) */
+    } rx_message_counter_reg;                   /* Address 0x0074 */
+    uint32_t reserved_78;                       /* Address 0x0078 (RX Buffer Start Address not supported) */
     union {
         struct {
             uint32_t cd: 3;                     /* CDR[2:0] CLKOUT frequency selector based of fOSC */
             uint32_t co: 1;                     /* CDR.3 CLKOUT enable/disable */
-            uint32_t reserved3: 3;              /* Internal Reserved. RXINTEN and CBP not supported */
+            uint32_t reserved4: 3;              /* Internal Reserved. RXINTEN and CBP not supported */
             uint32_t cm: 1;                     /* CDR.7 Register Layout. Basic:0 Extended:1 */
-            uint32_t reserved24: 24;            /* Internal Reserved  */
+            uint32_t reserved6: 24;             /* Internal Reserved  */
         };
         uint32_t val;
-    } clock_divider_reg;                        /* Address 31 */
+    } clock_divider_reg;                        /* Address 0x007C */
 } twai_dev_t;
 
 _Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
diff --git a/components/soc/esp32/include/soc/uart_struct.h b/components/soc/esp32/include/soc/uart_struct.h
index 7dc9b5144c..9feb0cb353 100644
--- a/components/soc/esp32/include/soc/uart_struct.h
+++ b/components/soc/esp32/include/soc/uart_struct.h
@@ -23,8 +23,8 @@ extern "C" {
 typedef volatile struct uart_dev_s {
     union {
         struct {
-            uint8_t rw_byte;                 /*This register stores one byte data  read by rx fifo.*/
-            uint8_t reserved[3];
+            uint32_t rw_byte:          8;           /*This register stores one byte data  read by rx fifo.*/
+            uint32_t reserved:         24;
         };
         uint32_t val;
     } fifo;
diff --git a/components/soc/esp32/include/soc/uhci_struct.h b/components/soc/esp32/include/soc/uhci_struct.h
index 3f42536c31..764268b35a 100644
--- a/components/soc/esp32/include/soc/uhci_struct.h
+++ b/components/soc/esp32/include/soc/uhci_struct.h
@@ -277,7 +277,7 @@ typedef volatile struct uhci_dev_s {
         };
         uint32_t val;
     } quick_sent;
-    struct{
+    struct {
         uint32_t w_data[2];                                /*This register stores the content of short packet's dword*/
     } q_data[7];
     union {
diff --git a/components/soc/esp32c3/include/soc/apb_ctrl_struct.h b/components/soc/esp32c3/include/soc/apb_ctrl_struct.h
index 9b832df8dd..dd20d37894 100644
--- a/components/soc/esp32c3/include/soc/apb_ctrl_struct.h
+++ b/components/soc/esp32c3/include/soc/apb_ctrl_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct apb_ctrl_dev_s {
     union {
         struct {
             uint32_t pre_div:     10;
diff --git a/components/soc/esp32c3/include/soc/apb_saradc_struct.h b/components/soc/esp32c3/include/soc/apb_saradc_struct.h
index c3ea73f150..c75e582f7d 100644
--- a/components/soc/esp32c3/include/soc/apb_saradc_struct.h
+++ b/components/soc/esp32c3/include/soc/apb_saradc_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct apb_saradc_dev_s {
     union {
         struct {
             uint32_t start_force:             1;
diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/include/soc/efuse_struct.h
index 1c51e71475..eed9c2544f 100644
--- a/components/soc/esp32c3/include/soc/efuse_struct.h
+++ b/components/soc/esp32c3/include/soc/efuse_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct efuse_dev_s {
     uint32_t pgm_data0;                                          /*Register 0 that stores data to be programmed.*/
     union {
         struct {
diff --git a/components/soc/esp32c3/include/soc/gdma_struct.h b/components/soc/esp32c3/include/soc/gdma_struct.h
index 446ff4c112..dde520f5ed 100644
--- a/components/soc/esp32c3/include/soc/gdma_struct.h
+++ b/components/soc/esp32c3/include/soc/gdma_struct.h
@@ -19,7 +19,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gdma_dev_s {
     struct {
         union {
             struct {
diff --git a/components/soc/esp32c3/include/soc/gpio_sd_struct.h b/components/soc/esp32c3/include/soc/gpio_sd_struct.h
index cc73cebd03..45e21d58e1 100644
--- a/components/soc/esp32c3/include/soc/gpio_sd_struct.h
+++ b/components/soc/esp32c3/include/soc/gpio_sd_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gpio_sd_dev_s {
     union {
         struct {
             uint32_t duty:         8;
diff --git a/components/soc/esp32c3/include/soc/gpio_struct.h b/components/soc/esp32c3/include/soc/gpio_struct.h
index f260adbd2a..45f5e55412 100644
--- a/components/soc/esp32c3/include/soc/gpio_struct.h
+++ b/components/soc/esp32c3/include/soc/gpio_struct.h
@@ -18,7 +18,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gpio_dev_s {
     uint32_t bt_select;                               /**/
     union {
         struct {
diff --git a/components/soc/esp32c3/include/soc/i2c_struct.h b/components/soc/esp32c3/include/soc/i2c_struct.h
index 22c6c47041..ccd5fdb5b0 100644
--- a/components/soc/esp32c3/include/soc/i2c_struct.h
+++ b/components/soc/esp32c3/include/soc/i2c_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 #endif
 #include "soc.h"
 
-typedef volatile struct {
+typedef volatile struct i2c_dev_s {
     union {
         struct {
             uint32_t period                        :    9;
diff --git a/components/soc/esp32c3/include/soc/i2s_struct.h b/components/soc/esp32c3/include/soc/i2s_struct.h
index 2f9c862b85..44334a8789 100644
--- a/components/soc/esp32c3/include/soc/i2s_struct.h
+++ b/components/soc/esp32c3/include/soc/i2s_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct i2s_dev_s {
     uint32_t reserved_0;
     uint32_t reserved_4;
     uint32_t reserved_8;
diff --git a/components/soc/esp32c3/include/soc/ledc_struct.h b/components/soc/esp32c3/include/soc/ledc_struct.h
index 9e5a2a96c1..0eb8c18268 100644
--- a/components/soc/esp32c3/include/soc/ledc_struct.h
+++ b/components/soc/esp32c3/include/soc/ledc_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct ledc_dev_s {
     struct {
         struct {
             union {
diff --git a/components/soc/esp32c3/include/soc/rmt_struct.h b/components/soc/esp32c3/include/soc/rmt_struct.h
index 7fc1890b12..b9b7533b3d 100644
--- a/components/soc/esp32c3/include/soc/rmt_struct.h
+++ b/components/soc/esp32c3/include/soc/rmt_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rmt_dev_s {
     uint32_t data_ch[4];                                   /**/
     union {
         struct {
@@ -291,11 +291,9 @@ typedef struct {
 } rmt_item32_t;
 
 //Allow access to RMT memory using RMTMEM.chan[0].data32[8]
-typedef volatile struct {
+typedef volatile struct rmt_mem_s {
     struct {
-        union {
-            rmt_item32_t data32[48];
-        };
+        rmt_item32_t data32[48];
     } chan[4];
 } rmt_mem_t;
 
diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_struct.h b/components/soc/esp32c3/include/soc/rtc_cntl_struct.h
index 358ebaded7..9478048648 100644
--- a/components/soc/esp32c3/include/soc/rtc_cntl_struct.h
+++ b/components/soc/esp32c3/include/soc/rtc_cntl_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rtc_cntl_dev_s {
     union {
         struct {
             uint32_t sw_stall_appcpu_c0:  2;               /*{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
diff --git a/components/soc/esp32c3/include/soc/rtc_i2c_struct.h b/components/soc/esp32c3/include/soc/rtc_i2c_struct.h
index 5141eebcd6..9f97a70cad 100644
--- a/components/soc/esp32c3/include/soc/rtc_i2c_struct.h
+++ b/components/soc/esp32c3/include/soc/rtc_i2c_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rtc_i2c_dev_s {
     union {
         struct {
             uint32_t period:        20;             /*time period that scl = 0*/
diff --git a/components/soc/esp32c3/include/soc/sensitive_struct.h b/components/soc/esp32c3/include/soc/sensitive_struct.h
index a24ccf6402..ba860e45cd 100644
--- a/components/soc/esp32c3/include/soc/sensitive_struct.h
+++ b/components/soc/esp32c3/include/soc/sensitive_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 #endif
 #include "soc.h"
 
-typedef volatile struct {
+typedef volatile struct sensitive_dev_s {
     union {
         struct {
             uint32_t reg_rom_table_lock            :    1;  /*rom_table_lock*/
@@ -959,8 +959,7 @@ typedef volatile struct {
     union {
         struct {
             uint32_t reg_clk_en                    :    1;  /*clk_en*/
-            uint32_t reserved1                     :    31;
-            uint32_t reservedNone                  :    None;  /*SENSITIVE_CLOCK_GATE_REG_REG*/
+            uint32_t reserved1                     :    31;  /*SENSITIVE_CLOCK_GATE_REG_REG*/
         };
         uint32_t val;
     } clock_gate;
diff --git a/components/soc/esp32c3/include/soc/spi_mem_struct.h b/components/soc/esp32c3/include/soc/spi_mem_struct.h
index e0f62b0d15..cde08c0207 100644
--- a/components/soc/esp32c3/include/soc/spi_mem_struct.h
+++ b/components/soc/esp32c3/include/soc/spi_mem_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct spi_mem_dev_s {
     union {
         struct {
             uint32_t mst_st:         4;                 /*The current status of SPI1 master FSM.*/
diff --git a/components/soc/esp32c3/include/soc/spi_struct.h b/components/soc/esp32c3/include/soc/spi_struct.h
index cc22595dd0..4011c8fed9 100644
--- a/components/soc/esp32c3/include/soc/spi_struct.h
+++ b/components/soc/esp32c3/include/soc/spi_struct.h
@@ -19,7 +19,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct spi_dev_s {
     union {
         struct {
             uint32_t conf_bitlen                   :    18;  /*Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.*/
diff --git a/components/soc/esp32c3/include/soc/syscon_struct.h b/components/soc/esp32c3/include/soc/syscon_struct.h
index 2a9485aa87..4be6b7f791 100644
--- a/components/soc/esp32c3/include/soc/syscon_struct.h
+++ b/components/soc/esp32c3/include/soc/syscon_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct syscon_dev_s {
     union {
         struct {
             uint32_t apb_ctrl_pre_div_cnt: 10;
diff --git a/components/soc/esp32c3/include/soc/system_struct.h b/components/soc/esp32c3/include/soc/system_struct.h
index f07fab0aff..5e04cec828 100644
--- a/components/soc/esp32c3/include/soc/system_struct.h
+++ b/components/soc/esp32c3/include/soc/system_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 #endif
 #include "soc.h"
 
-typedef volatile struct {
+typedef volatile struct system_dev_s {
     union {
         struct {
             uint32_t reserved0                     :    6;  /*reserved*/
diff --git a/components/soc/esp32c3/include/soc/systimer_struct.h b/components/soc/esp32c3/include/soc/systimer_struct.h
index af41b1f3e2..f10bc1f126 100644
--- a/components/soc/esp32c3/include/soc/systimer_struct.h
+++ b/components/soc/esp32c3/include/soc/systimer_struct.h
@@ -88,6 +88,7 @@ typedef union {
          *  update timer_unit0
          */
         uint32_t timer_unit_update: 1;
+        uint32_t reserved31: 1;
     };
     uint32_t val;
 } systimer_unit_op_reg_t;
@@ -102,6 +103,7 @@ typedef struct {
              *  timer unit load high 32 bit
              */
             uint32_t timer_unit_load_hi: 20;
+            uint32_t reserved20: 12;
         };
         uint32_t val;
     } hi;
@@ -126,6 +128,7 @@ typedef struct {
              *  timer target high 32 bit
              */
             uint32_t timer_target_hi: 20;
+            uint32_t reserved20: 12;
         };
         uint32_t val;
     } hi;
@@ -172,6 +175,7 @@ typedef struct {
              *  timer read value high 20bit
              */
             uint32_t timer_unit_value_hi: 20;
+            uint32_t reserved20: 12;
         };
         uint32_t val;
     } hi;
@@ -195,6 +199,7 @@ typedef union {
          *  timer comp load value
          */
         uint32_t timer_comp_load: 1;
+        uint32_t reserved1: 31;
     };
     uint32_t val;
 } systimer_comp_load_reg_t;
@@ -208,6 +213,7 @@ typedef union {
          *  timer unit load value
          */
         uint32_t timer_unit_load: 1;
+        uint32_t reserved1: 31;
     };
     uint32_t val;
 } systimer_unit_load_reg_t;
@@ -230,6 +236,7 @@ typedef union {
          *  interupt2 enable
          */
         uint32_t target2_int_ena: 1;
+        uint32_t reserved3: 29;
     };
     uint32_t val;
 } systimer_int_ena_reg_t;
@@ -251,6 +258,7 @@ typedef union {
          *  interupt2 raw
          */
         uint32_t target2_int_raw: 1;
+        uint32_t reserved3: 29;
     };
     uint32_t val;
 } systimer_int_raw_reg_t;
@@ -272,6 +280,7 @@ typedef union {
          *  interupt2 clear
          */
         uint32_t target2_int_clr: 1;
+        uint32_t reserved3: 29;
     };
     uint32_t val;
 } systimer_int_clr_reg_t;
@@ -293,6 +302,7 @@ typedef union {
          *  reg_target2_int_st
          */
         uint32_t target2_int_st: 1;
+        uint32_t reserved3: 29;
     };
     uint32_t val;
 } systimer_int_st_reg_t;
diff --git a/components/soc/esp32c3/include/soc/twai_struct.h b/components/soc/esp32c3/include/soc/twai_struct.h
index 64cb80e5ed..fafc36393a 100644
--- a/components/soc/esp32c3/include/soc/twai_struct.h
+++ b/components/soc/esp32c3/include/soc/twai_struct.h
@@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
             uint32_t lom: 1;                    /* MOD.1 Listen Only Mode */
             uint32_t stm: 1;                    /* MOD.2 Self Test Mode */
             uint32_t afm: 1;                    /* MOD.3 Acceptance Filter Mode */
-            uint32_t reserved28: 28;            /* Internal Reserved. MOD.4 Sleep Mode not supported */
+            uint32_t reserved4: 28;             /* Internal Reserved. MOD.4 Sleep Mode not supported */
         };
         uint32_t val;
-    } mode_reg;                                 /* Address 0 */
+    } mode_reg;                                 /* Address 0x0000 */
     union {
         struct {
             uint32_t tr: 1;                     /* CMR.0 Transmission Request */
@@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
             uint32_t rrb: 1;                    /* CMR.2 Release Receive Buffer */
             uint32_t cdo: 1;                    /* CMR.3 Clear Data Overrun */
             uint32_t srr: 1;                    /* CMR.4 Self Reception Request */
-            uint32_t reserved27: 27;            /* Internal Reserved */
+            uint32_t reserved5: 27;             /* Internal Reserved */
         };
         uint32_t val;
-    } command_reg;                              /* Address 1 */
+    } command_reg;                              /* Address 0x0004 */
     union {
         struct {
             uint32_t rbs: 1;                    /* SR.0 Receive Buffer Status */
@@ -61,97 +61,99 @@ typedef volatile struct twai_dev_s {
             uint32_t es: 1;                     /* SR.6 Error Status */
             uint32_t bs: 1;                     /* SR.7 Bus Status */
             uint32_t ms: 1;                     /* SR.8 Miss Status */
-            uint32_t reserved23: 23;            /* Internal Reserved */
+            uint32_t reserved9: 23;             /* Internal Reserved */
         };
         uint32_t val;
-    } status_reg;                               /* Address 2 */
+    } status_reg;                               /* Address 0x0008 */
     union {
         struct {
             uint32_t ri: 1;                     /* IR.0 Receive Interrupt */
             uint32_t ti: 1;                     /* IR.1 Transmit Interrupt */
             uint32_t ei: 1;                     /* IR.2 Error Interrupt */
-            uint32_t reserved2: 2;              /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
+            uint32_t doi: 1;                    /* IR.3 Data Overrun Interrupt */
+            uint32_t reserved4: 1;              /* Internal Reserved (Wake-up not supported) */
             uint32_t epi: 1;                    /* IR.5 Error Passive Interrupt */
             uint32_t ali: 1;                    /* IR.6 Arbitration Lost Interrupt */
             uint32_t bei: 1;                    /* IR.7 Bus Error Interrupt */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } interrupt_reg;                           /* Address 3 */
+    } interrupt_reg;                           /* Address 0x000C */
     union {
         struct {
             uint32_t rie: 1;                    /* IER.0 Receive Interrupt Enable */
             uint32_t tie: 1;                    /* IER.1 Transmit Interrupt Enable */
             uint32_t eie: 1;                    /* IER.2 Error Interrupt Enable */
-            uint32_t reserved2: 2;              /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
+            uint32_t doie: 1;                   /* IER.3 Data Overrun Interrupt Enable */
+            uint32_t reserved4: 1;              /* Internal Reserved (Wake-up not supported) */
             uint32_t epie: 1;                   /* IER.5 Error Passive Interrupt Enable */
             uint32_t alie: 1;                   /* IER.6 Arbitration Lost Interrupt Enable */
             uint32_t beie: 1;                   /* IER.7 Bus Error Interrupt Enable */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } interrupt_enable_reg;                     /* Address 4 */
-    uint32_t reserved_05;                       /* Address 5 */
+    } interrupt_enable_reg;                     /* Address 0x0010 */
+    uint32_t reserved_14;
     union {
         struct {
             uint32_t brp: 13;                   /* BTR0[12:0] Baud Rate Prescaler */
-            uint32_t reserved1: 1;              /* Internal Reserved */
+            uint32_t reserved13: 1;             /* Internal Reserved */
             uint32_t sjw: 2;                    /* BTR0[15:14] Synchronization Jump Width*/
             uint32_t reserved16: 16;            /* Internal Reserved */
         };
         uint32_t val;
-    } bus_timing_0_reg;                         /* Address 6 */
+    } bus_timing_0_reg;                         /* Address 0x0018 */
     union {
         struct {
             uint32_t tseg1: 4;                  /* BTR1[3:0] Timing Segment 1 */
             uint32_t tseg2: 3;                  /* BTR1[6:4] Timing Segment 2 */
             uint32_t sam: 1;                    /* BTR1.7 Sampling*/
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } bus_timing_1_reg;                         /* Address 7 */
-    uint32_t reserved_08;                       /* Address 8 (Output control not supported) */
-    uint32_t reserved_09;                       /* Address 9 (Test Register not supported) */
-    uint32_t reserved_10;                       /* Address 10 */
+    } bus_timing_1_reg;                         /* Address 0x001C */
+    uint32_t reserved_20;                       /* Address 0x0020 (Output control not supported) */
+    uint32_t reserved_24;                       /* Address 0x0024 (Test Register not supported) */
+    uint32_t reserved_28;                       /* Address 0x0028 */
 
     //Capture and Counter Registers
     union {
         struct {
             uint32_t alc: 5;                    /* ALC[4:0] Arbitration lost capture */
-            uint32_t reserved27: 27;            /* Internal Reserved */
+            uint32_t reserved5: 27;             /* Internal Reserved */
         };
         uint32_t val;
-    } arbitration_lost_captue_reg;              /* Address 11 */
+    } arbitration_lost_captue_reg;              /* Address 0x002C */
     union {
         struct {
             uint32_t seg: 5;                    /* ECC[4:0] Error Code Segment 0 to 5 */
             uint32_t dir: 1;                    /* ECC.5 Error Direction (TX/RX) */
             uint32_t errc: 2;                   /* ECC[7:6] Error Code */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } error_code_capture_reg;                   /* Address 12 */
+    } error_code_capture_reg;                   /* Address 0x0030 */
     union {
         struct {
             uint32_t ewl: 8;                    /* EWL[7:0] Error Warning Limit */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } error_warning_limit_reg;                  /* EWLR[7:0] Error Warning Limit: Address 13 */
+    } error_warning_limit_reg;                  /* Address 0x0034 */
     union {
         struct {
             uint32_t rxerr: 8;                  /* RXERR[7:0] Receive Error Counter */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } rx_error_counter_reg;                     /* Address 12 */
+    } rx_error_counter_reg;                     /* Address 0x0038 */
     union {
         struct {
             uint32_t txerr: 8;                  /* TXERR[7:0] Receive Error Counter */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } tx_error_counter_reg;                     /* Address 15 */
+    } tx_error_counter_reg;                     /* Address 0x003C */
 
     //Shared Registers (TX Buff/RX Buff/Acc Filter)
     union {
@@ -159,45 +161,49 @@ typedef volatile struct twai_dev_s {
             union {
                 struct {
                     uint32_t byte: 8;           /* ACRx[7:0] Acceptance Code */
-                    uint32_t reserved24: 24;    /* Internal Reserved */
+                    uint32_t reserved8: 24;     /* Internal Reserved */
                 };
                 uint32_t val;
             } acr[4];
             union {
                 struct {
                     uint32_t byte: 8;           /* AMRx[7:0] Acceptance Mask */
-                    uint32_t reserved24: 24;    /* Internal Reserved */
+                    uint32_t reserved8: 24;     /* Internal Reserved */
                 };
                 uint32_t val;
             } amr[4];
-            uint32_t reserved32[5];
+            uint32_t reserved_60;
+            uint32_t reserved_64;
+            uint32_t reserved_68;
+            uint32_t reserved_6c;
+            uint32_t reserved_70;
         } acceptance_filter;
         union {
             struct {
-                uint32_t byte: 8;
-                uint32_t reserved24: 24;
+                uint32_t byte: 8;               /* TX/RX Byte X [7:0] */
+                uint32_t reserved24: 24;        /* Internal Reserved */
             };
             uint32_t val;
         } tx_rx_buffer[13];
-    };                                          /* Address 16-28 TX/RX Buffer and Acc Filter*/;
+    };                                          /* Address 0x0040 - 0x0070 */
 
     //Misc Registers
     union {
         struct {
             uint32_t rmc: 7;                    /* RMC[6:0] RX Message Counter */
-            uint32_t reserved25: 25;            /* Internal Reserved */
+            uint32_t reserved7: 25;             /* Internal Reserved */
         };
         uint32_t val;
-    } rx_message_counter_reg;                   /* Address 29 */
-    uint32_t reserved_30;                       /* Address 30 (RX Buffer Start Address not supported) */
+    } rx_message_counter_reg;                   /* Address 0x0074 */
+    uint32_t reserved_78;                       /* Address 0x0078 (RX Buffer Start Address not supported) */
     union {
         struct {
             uint32_t cd: 8;                     /* CDR[7:0] CLKOUT frequency selector based of fOSC */
             uint32_t co: 1;                     /* CDR.8 CLKOUT enable/disable */
-            uint32_t reserved24: 23;            /* Internal Reserved  */
+            uint32_t reserved9: 23;             /* Internal Reserved  */
         };
         uint32_t val;
-    } clock_divider_reg;                        /* Address 31 */
+    } clock_divider_reg;                        /* Address 0x007C */
 } twai_dev_t;
 
 _Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
diff --git a/components/soc/esp32c3/include/soc/uart_struct.h b/components/soc/esp32c3/include/soc/uart_struct.h
index ad9ca42ff7..82f8ef6686 100644
--- a/components/soc/esp32c3/include/soc/uart_struct.h
+++ b/components/soc/esp32c3/include/soc/uart_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct uart_dev_s {
     union {
         struct {
             uint32_t rw_byte;                 /*a*/
diff --git a/components/soc/esp32c3/include/soc/uhci_struct.h b/components/soc/esp32c3/include/soc/uhci_struct.h
index a89c4d0126..164f1a1334 100644
--- a/components/soc/esp32c3/include/soc/uhci_struct.h
+++ b/components/soc/esp32c3/include/soc/uhci_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct uhci_dev_s {
     union {
         struct {
             uint32_t tx_rst:             1;            /*Write 1  then write 0 to this bit to reset decode state machine.*/
diff --git a/components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h
index 5ae44587a6..c1cfced04b 100644
--- a/components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h
+++ b/components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 #endif
 #include "soc.h"
 
-typedef volatile struct {
+typedef volatile struct usb_serial_jtag_dev_s {
     union {
         struct {
             uint32_t rdwr_byte                     :    32;  /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set  then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */
diff --git a/components/soc/esp32h2/include/soc/apb_ctrl_struct.h b/components/soc/esp32h2/include/soc/apb_ctrl_struct.h
index 53edfec0dd..f97227ca11 100644
--- a/components/soc/esp32h2/include/soc/apb_ctrl_struct.h
+++ b/components/soc/esp32h2/include/soc/apb_ctrl_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct apb_ctrl_dev_s {
     uint32_t reserved_0;
     uint32_t reserved_4;
     uint32_t reserved_8;
diff --git a/components/soc/esp32h2/include/soc/apb_saradc_struct.h b/components/soc/esp32h2/include/soc/apb_saradc_struct.h
index 67242d822d..a286c3c557 100644
--- a/components/soc/esp32h2/include/soc/apb_saradc_struct.h
+++ b/components/soc/esp32h2/include/soc/apb_saradc_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct apb_saradc_dev_s {
     union {
         struct {
             uint32_t start_force:             1;
diff --git a/components/soc/esp32h2/include/soc/efuse_struct.h b/components/soc/esp32h2/include/soc/efuse_struct.h
index 1c51e71475..eed9c2544f 100644
--- a/components/soc/esp32h2/include/soc/efuse_struct.h
+++ b/components/soc/esp32h2/include/soc/efuse_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct efuse_dev_s {
     uint32_t pgm_data0;                                          /*Register 0 that stores data to be programmed.*/
     union {
         struct {
diff --git a/components/soc/esp32h2/include/soc/gdma_struct.h b/components/soc/esp32h2/include/soc/gdma_struct.h
index 446ff4c112..dde520f5ed 100644
--- a/components/soc/esp32h2/include/soc/gdma_struct.h
+++ b/components/soc/esp32h2/include/soc/gdma_struct.h
@@ -19,7 +19,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gdma_dev_s {
     struct {
         union {
             struct {
diff --git a/components/soc/esp32h2/include/soc/gpio_sd_struct.h b/components/soc/esp32h2/include/soc/gpio_sd_struct.h
index cc73cebd03..45e21d58e1 100644
--- a/components/soc/esp32h2/include/soc/gpio_sd_struct.h
+++ b/components/soc/esp32h2/include/soc/gpio_sd_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gpio_sd_dev_s {
     union {
         struct {
             uint32_t duty:         8;
diff --git a/components/soc/esp32h2/include/soc/gpio_struct.h b/components/soc/esp32h2/include/soc/gpio_struct.h
index f260adbd2a..45f5e55412 100644
--- a/components/soc/esp32h2/include/soc/gpio_struct.h
+++ b/components/soc/esp32h2/include/soc/gpio_struct.h
@@ -18,7 +18,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gpio_dev_s {
     uint32_t bt_select;                               /**/
     union {
         struct {
diff --git a/components/soc/esp32h2/include/soc/i2c_struct.h b/components/soc/esp32h2/include/soc/i2c_struct.h
index 22c6c47041..ccd5fdb5b0 100644
--- a/components/soc/esp32h2/include/soc/i2c_struct.h
+++ b/components/soc/esp32h2/include/soc/i2c_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 #endif
 #include "soc.h"
 
-typedef volatile struct {
+typedef volatile struct i2c_dev_s {
     union {
         struct {
             uint32_t period                        :    9;
diff --git a/components/soc/esp32h2/include/soc/i2s_struct.h b/components/soc/esp32h2/include/soc/i2s_struct.h
index 9d3537004c..9ea88c5a12 100644
--- a/components/soc/esp32h2/include/soc/i2s_struct.h
+++ b/components/soc/esp32h2/include/soc/i2s_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct i2s_dev_s {
     uint32_t reserved_0;
     uint32_t reserved_4;
     uint32_t reserved_8;
diff --git a/components/soc/esp32h2/include/soc/ledc_struct.h b/components/soc/esp32h2/include/soc/ledc_struct.h
index 9e5a2a96c1..0eb8c18268 100644
--- a/components/soc/esp32h2/include/soc/ledc_struct.h
+++ b/components/soc/esp32h2/include/soc/ledc_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct ledc_dev_s {
     struct {
         struct {
             union {
diff --git a/components/soc/esp32h2/include/soc/rmt_struct.h b/components/soc/esp32h2/include/soc/rmt_struct.h
index 7fc1890b12..b9b7533b3d 100644
--- a/components/soc/esp32h2/include/soc/rmt_struct.h
+++ b/components/soc/esp32h2/include/soc/rmt_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rmt_dev_s {
     uint32_t data_ch[4];                                   /**/
     union {
         struct {
@@ -291,11 +291,9 @@ typedef struct {
 } rmt_item32_t;
 
 //Allow access to RMT memory using RMTMEM.chan[0].data32[8]
-typedef volatile struct {
+typedef volatile struct rmt_mem_s {
     struct {
-        union {
-            rmt_item32_t data32[48];
-        };
+        rmt_item32_t data32[48];
     } chan[4];
 } rmt_mem_t;
 
diff --git a/components/soc/esp32h2/include/soc/rtc_cntl_struct.h b/components/soc/esp32h2/include/soc/rtc_cntl_struct.h
index 68100c9cee..473f236249 100644
--- a/components/soc/esp32h2/include/soc/rtc_cntl_struct.h
+++ b/components/soc/esp32h2/include/soc/rtc_cntl_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rtc_cntl_dev_s {
     union {
         struct {
             uint32_t sw_stall_appcpu_c0:  2;                 /*{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
diff --git a/components/soc/esp32h2/include/soc/rtc_i2c_struct.h b/components/soc/esp32h2/include/soc/rtc_i2c_struct.h
index 5141eebcd6..9f97a70cad 100644
--- a/components/soc/esp32h2/include/soc/rtc_i2c_struct.h
+++ b/components/soc/esp32h2/include/soc/rtc_i2c_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rtc_i2c_dev_s {
     union {
         struct {
             uint32_t period:        20;             /*time period that scl = 0*/
diff --git a/components/soc/esp32h2/include/soc/sensitive_struct.h b/components/soc/esp32h2/include/soc/sensitive_struct.h
index cf27320a79..8747c8a5e0 100644
--- a/components/soc/esp32h2/include/soc/sensitive_struct.h
+++ b/components/soc/esp32h2/include/soc/sensitive_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 #endif
 #include "soc.h"
 
-typedef volatile struct {
+typedef volatile struct sensitive_dev_s {
     union {
         struct {
             uint32_t reg_rom_table_lock            :    1;  /*rom_table_lock*/
diff --git a/components/soc/esp32h2/include/soc/spi_mem_struct.h b/components/soc/esp32h2/include/soc/spi_mem_struct.h
index e0f62b0d15..cde08c0207 100644
--- a/components/soc/esp32h2/include/soc/spi_mem_struct.h
+++ b/components/soc/esp32h2/include/soc/spi_mem_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct spi_mem_dev_s {
     union {
         struct {
             uint32_t mst_st:         4;                 /*The current status of SPI1 master FSM.*/
diff --git a/components/soc/esp32h2/include/soc/spi_struct.h b/components/soc/esp32h2/include/soc/spi_struct.h
index 867510549d..dcdec116ad 100644
--- a/components/soc/esp32h2/include/soc/spi_struct.h
+++ b/components/soc/esp32h2/include/soc/spi_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 #endif
 #include "soc.h"
 
-typedef volatile struct {
+typedef volatile struct spi_dev_s {
     union {
         struct {
             uint32_t conf_bitlen                   :    18;  /*Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.*/
diff --git a/components/soc/esp32h2/include/soc/syscon_struct.h b/components/soc/esp32h2/include/soc/syscon_struct.h
index e25e44179f..536c28058d 100644
--- a/components/soc/esp32h2/include/soc/syscon_struct.h
+++ b/components/soc/esp32h2/include/soc/syscon_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct syscon_dev_s {
     uint32_t reserved_0;
     uint32_t reserved_4;
     uint32_t reserved_8;
diff --git a/components/soc/esp32h2/include/soc/system_struct.h b/components/soc/esp32h2/include/soc/system_struct.h
index 58c1c6b99f..8b9d4892bb 100644
--- a/components/soc/esp32h2/include/soc/system_struct.h
+++ b/components/soc/esp32h2/include/soc/system_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 #endif
 #include "soc.h"
 
-typedef volatile struct {
+typedef volatile struct system_dev_s {
     union {
         struct {
             uint32_t reserved0                     :    6;  /*reserved*/
diff --git a/components/soc/esp32h2/include/soc/systimer_struct.h b/components/soc/esp32h2/include/soc/systimer_struct.h
index af41b1f3e2..f10bc1f126 100644
--- a/components/soc/esp32h2/include/soc/systimer_struct.h
+++ b/components/soc/esp32h2/include/soc/systimer_struct.h
@@ -88,6 +88,7 @@ typedef union {
          *  update timer_unit0
          */
         uint32_t timer_unit_update: 1;
+        uint32_t reserved31: 1;
     };
     uint32_t val;
 } systimer_unit_op_reg_t;
@@ -102,6 +103,7 @@ typedef struct {
              *  timer unit load high 32 bit
              */
             uint32_t timer_unit_load_hi: 20;
+            uint32_t reserved20: 12;
         };
         uint32_t val;
     } hi;
@@ -126,6 +128,7 @@ typedef struct {
              *  timer target high 32 bit
              */
             uint32_t timer_target_hi: 20;
+            uint32_t reserved20: 12;
         };
         uint32_t val;
     } hi;
@@ -172,6 +175,7 @@ typedef struct {
              *  timer read value high 20bit
              */
             uint32_t timer_unit_value_hi: 20;
+            uint32_t reserved20: 12;
         };
         uint32_t val;
     } hi;
@@ -195,6 +199,7 @@ typedef union {
          *  timer comp load value
          */
         uint32_t timer_comp_load: 1;
+        uint32_t reserved1: 31;
     };
     uint32_t val;
 } systimer_comp_load_reg_t;
@@ -208,6 +213,7 @@ typedef union {
          *  timer unit load value
          */
         uint32_t timer_unit_load: 1;
+        uint32_t reserved1: 31;
     };
     uint32_t val;
 } systimer_unit_load_reg_t;
@@ -230,6 +236,7 @@ typedef union {
          *  interupt2 enable
          */
         uint32_t target2_int_ena: 1;
+        uint32_t reserved3: 29;
     };
     uint32_t val;
 } systimer_int_ena_reg_t;
@@ -251,6 +258,7 @@ typedef union {
          *  interupt2 raw
          */
         uint32_t target2_int_raw: 1;
+        uint32_t reserved3: 29;
     };
     uint32_t val;
 } systimer_int_raw_reg_t;
@@ -272,6 +280,7 @@ typedef union {
          *  interupt2 clear
          */
         uint32_t target2_int_clr: 1;
+        uint32_t reserved3: 29;
     };
     uint32_t val;
 } systimer_int_clr_reg_t;
@@ -293,6 +302,7 @@ typedef union {
          *  reg_target2_int_st
          */
         uint32_t target2_int_st: 1;
+        uint32_t reserved3: 29;
     };
     uint32_t val;
 } systimer_int_st_reg_t;
diff --git a/components/soc/esp32h2/include/soc/twai_struct.h b/components/soc/esp32h2/include/soc/twai_struct.h
index a2c72e5afa..8c9b60059c 100644
--- a/components/soc/esp32h2/include/soc/twai_struct.h
+++ b/components/soc/esp32h2/include/soc/twai_struct.h
@@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
             uint32_t lom: 1;                    /* MOD.1 Listen Only Mode */
             uint32_t stm: 1;                    /* MOD.2 Self Test Mode */
             uint32_t afm: 1;                    /* MOD.3 Acceptance Filter Mode */
-            uint32_t reserved28: 28;            /* Internal Reserved. MOD.4 Sleep Mode not supported */
+            uint32_t reserved4: 28;             /* Internal Reserved. MOD.4 Sleep Mode not supported */
         };
         uint32_t val;
-    } mode_reg;                                 /* Address 0 */
+    } mode_reg;                                 /* Address 0x0000 */
     union {
         struct {
             uint32_t tr: 1;                     /* CMR.0 Transmission Request */
@@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
             uint32_t rrb: 1;                    /* CMR.2 Release Receive Buffer */
             uint32_t cdo: 1;                    /* CMR.3 Clear Data Overrun */
             uint32_t srr: 1;                    /* CMR.4 Self Reception Request */
-            uint32_t reserved27: 27;            /* Internal Reserved */
+            uint32_t reserved5: 27;             /* Internal Reserved */
         };
         uint32_t val;
-    } command_reg;                              /* Address 1 */
+    } command_reg;                              /* Address 0x0004 */
     union {
         struct {
             uint32_t rbs: 1;                    /* SR.0 Receive Buffer Status */
@@ -61,97 +61,99 @@ typedef volatile struct twai_dev_s {
             uint32_t es: 1;                     /* SR.6 Error Status */
             uint32_t bs: 1;                     /* SR.7 Bus Status */
             uint32_t ms: 1;                     /* SR.8 Miss Status */
-            uint32_t reserved23: 23;            /* Internal Reserved */
+            uint32_t reserved9: 23;             /* Internal Reserved */
         };
         uint32_t val;
-    } status_reg;                               /* Address 2 */
+    } status_reg;                               /* Address 0x0008 */
     union {
         struct {
             uint32_t ri: 1;                     /* IR.0 Receive Interrupt */
             uint32_t ti: 1;                     /* IR.1 Transmit Interrupt */
             uint32_t ei: 1;                     /* IR.2 Error Interrupt */
-            uint32_t reserved2: 2;              /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
+            uint32_t doi: 1;                    /* IR.3 Data Overrun Interrupt */
+            uint32_t reserved4: 1;              /* Internal Reserved (Wake-up not supported) */
             uint32_t epi: 1;                    /* IR.5 Error Passive Interrupt */
             uint32_t ali: 1;                    /* IR.6 Arbitration Lost Interrupt */
             uint32_t bei: 1;                    /* IR.7 Bus Error Interrupt */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } interrupt_reg;                           /* Address 3 */
+    } interrupt_reg;                           /* Address 0x000C */
     union {
         struct {
             uint32_t rie: 1;                    /* IER.0 Receive Interrupt Enable */
             uint32_t tie: 1;                    /* IER.1 Transmit Interrupt Enable */
             uint32_t eie: 1;                    /* IER.2 Error Interrupt Enable */
-            uint32_t reserved2: 2;              /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
+            uint32_t doie: 1;                   /* IER.3 Data Overrun Interrupt Enable */
+            uint32_t reserved4: 1;              /* Internal Reserved (Wake-up not supported) */
             uint32_t epie: 1;                   /* IER.5 Error Passive Interrupt Enable */
             uint32_t alie: 1;                   /* IER.6 Arbitration Lost Interrupt Enable */
             uint32_t beie: 1;                   /* IER.7 Bus Error Interrupt Enable */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } interrupt_enable_reg;                     /* Address 4 */
-    uint32_t reserved_05;                       /* Address 5 */
+    } interrupt_enable_reg;                     /* Address 0x0010 */
+    uint32_t reserved_14;
     union {
         struct {
             uint32_t brp: 13;                   /* BTR0[12:0] Baud Rate Prescaler */
-            uint32_t reserved1: 1;              /* Internal Reserved */
+            uint32_t reserved13: 1;             /* Internal Reserved */
             uint32_t sjw: 2;                    /* BTR0[15:14] Synchronization Jump Width*/
             uint32_t reserved16: 16;            /* Internal Reserved */
         };
         uint32_t val;
-    } bus_timing_0_reg;                         /* Address 6 */
+    } bus_timing_0_reg;                         /* Address 0x0018 */
     union {
         struct {
             uint32_t tseg1: 4;                  /* BTR1[3:0] Timing Segment 1 */
             uint32_t tseg2: 3;                  /* BTR1[6:4] Timing Segment 2 */
             uint32_t sam: 1;                    /* BTR1.7 Sampling*/
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } bus_timing_1_reg;                         /* Address 7 */
-    uint32_t reserved_08;                       /* Address 8 (Output control not supported) */
-    uint32_t reserved_09;                       /* Address 9 (Test Register not supported) */
-    uint32_t reserved_10;                       /* Address 10 */
+    } bus_timing_1_reg;                         /* Address 0x001C */
+    uint32_t reserved_20;                       /* Address 0x0020 (Output control not supported) */
+    uint32_t reserved_24;                       /* Address 0x0024 (Test Register not supported) */
+    uint32_t reserved_28;                       /* Address 0x0028 */
 
     //Capture and Counter Registers
     union {
         struct {
             uint32_t alc: 5;                    /* ALC[4:0] Arbitration lost capture */
-            uint32_t reserved27: 27;            /* Internal Reserved */
+            uint32_t reserved5: 27;             /* Internal Reserved */
         };
         uint32_t val;
-    } arbitration_lost_captue_reg;              /* Address 11 */
+    } arbitration_lost_captue_reg;              /* Address 0x002C */
     union {
         struct {
             uint32_t seg: 5;                    /* ECC[4:0] Error Code Segment 0 to 5 */
             uint32_t dir: 1;                    /* ECC.5 Error Direction (TX/RX) */
             uint32_t errc: 2;                   /* ECC[7:6] Error Code */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } error_code_capture_reg;                   /* Address 12 */
+    } error_code_capture_reg;                   /* Address 0x0030 */
     union {
         struct {
             uint32_t ewl: 8;                    /* EWL[7:0] Error Warning Limit */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } error_warning_limit_reg;                  /* EWLR[7:0] Error Warning Limit: Address 13 */
+    } error_warning_limit_reg;                  /* Address 0x0034 */
     union {
         struct {
             uint32_t rxerr: 8;                  /* RXERR[7:0] Receive Error Counter */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } rx_error_counter_reg;                     /* Address 12 */
+    } rx_error_counter_reg;                     /* Address 0x0038 */
     union {
         struct {
             uint32_t txerr: 8;                  /* TXERR[7:0] Receive Error Counter */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } tx_error_counter_reg;                     /* Address 15 */
+    } tx_error_counter_reg;                     /* Address 0x003C */
 
     //Shared Registers (TX Buff/RX Buff/Acc Filter)
     union {
@@ -159,45 +161,49 @@ typedef volatile struct twai_dev_s {
             union {
                 struct {
                     uint32_t byte: 8;           /* ACRx[7:0] Acceptance Code */
-                    uint32_t reserved24: 24;    /* Internal Reserved */
+                    uint32_t reserved8: 24;     /* Internal Reserved */
                 };
                 uint32_t val;
             } acr[4];
             union {
                 struct {
                     uint32_t byte: 8;           /* AMRx[7:0] Acceptance Mask */
-                    uint32_t reserved24: 24;    /* Internal Reserved */
+                    uint32_t reserved8: 24;     /* Internal Reserved */
                 };
                 uint32_t val;
             } amr[4];
-            uint32_t reserved32[5];
+            uint32_t reserved_60;
+            uint32_t reserved_64;
+            uint32_t reserved_68;
+            uint32_t reserved_6c;
+            uint32_t reserved_70;
         } acceptance_filter;
         union {
             struct {
-                uint32_t byte: 8;
-                uint32_t reserved24: 24;
+                uint32_t byte: 8;               /* TX/RX Byte X [7:0] */
+                uint32_t reserved24: 24;        /* Internal Reserved */
             };
             uint32_t val;
         } tx_rx_buffer[13];
-    };                                          /* Address 16-28 TX/RX Buffer and Acc Filter*/;
+    };                                          /* Address 0x0040 - 0x0070 */
 
     //Misc Registers
     union {
         struct {
             uint32_t rmc: 7;                    /* RMC[6:0] RX Message Counter */
-            uint32_t reserved25: 25;            /* Internal Reserved */
+            uint32_t reserved7: 25;             /* Internal Reserved */
         };
         uint32_t val;
-    } rx_message_counter_reg;                   /* Address 29 */
-    uint32_t reserved_30;                       /* Address 30 (RX Buffer Start Address not supported) */
+    } rx_message_counter_reg;                   /* Address 0x0074 */
+    uint32_t reserved_78;                       /* Address 0x0078 (RX Buffer Start Address not supported) */
     union {
         struct {
             uint32_t cd: 8;                     /* CDR[7:0] CLKOUT frequency selector based of fOSC */
             uint32_t co: 1;                     /* CDR.8 CLKOUT enable/disable */
-            uint32_t reserved24: 23;            /* Internal Reserved  */
+            uint32_t reserved9: 23;             /* Internal Reserved  */
         };
         uint32_t val;
-    } clock_divider_reg;                        /* Address 31 */
+    } clock_divider_reg;                        /* Address 0x007C */
 } twai_dev_t;
 
 _Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
diff --git a/components/soc/esp32h2/include/soc/uart_struct.h b/components/soc/esp32h2/include/soc/uart_struct.h
index ad9ca42ff7..82f8ef6686 100644
--- a/components/soc/esp32h2/include/soc/uart_struct.h
+++ b/components/soc/esp32h2/include/soc/uart_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct uart_dev_s {
     union {
         struct {
             uint32_t rw_byte;                 /*a*/
diff --git a/components/soc/esp32h2/include/soc/uhci_struct.h b/components/soc/esp32h2/include/soc/uhci_struct.h
index a89c4d0126..164f1a1334 100644
--- a/components/soc/esp32h2/include/soc/uhci_struct.h
+++ b/components/soc/esp32h2/include/soc/uhci_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct uhci_dev_s {
     union {
         struct {
             uint32_t tx_rst:             1;            /*Write 1  then write 0 to this bit to reset decode state machine.*/
diff --git a/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h
index 72c1005d30..e9e4b8b8ea 100644
--- a/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h
+++ b/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 #endif
 #include "soc.h"
 
-typedef volatile struct {
+typedef volatile struct usb_serial_jtag_dev_s {
     union {
         struct {
             uint32_t rdwr_byte                     :    8;  /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set  then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */
diff --git a/components/soc/esp32s2/include/soc/apb_ctrl_struct.h b/components/soc/esp32s2/include/soc/apb_ctrl_struct.h
index d05c2c9a00..dbf2e4e3ef 100644
--- a/components/soc/esp32s2/include/soc/apb_ctrl_struct.h
+++ b/components/soc/esp32s2/include/soc/apb_ctrl_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct apb_ctrl_dev_s {
     union {
         struct {
             uint32_t pre_div:     10;
diff --git a/components/soc/esp32s2/include/soc/apb_saradc_struct.h b/components/soc/esp32s2/include/soc/apb_saradc_struct.h
index e9811dab60..505596f994 100644
--- a/components/soc/esp32s2/include/soc/apb_saradc_struct.h
+++ b/components/soc/esp32s2/include/soc/apb_saradc_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct apb_saradc_dev_s {
     union {
         struct {
             uint32_t start_force:              1;
diff --git a/components/soc/esp32s2/include/soc/cp_dma_struct.h b/components/soc/esp32s2/include/soc/cp_dma_struct.h
index 208c82939c..15fb42e451 100644
--- a/components/soc/esp32s2/include/soc/cp_dma_struct.h
+++ b/components/soc/esp32s2/include/soc/cp_dma_struct.h
@@ -69,6 +69,7 @@ typedef union {
          *  This is the interrupt raw bit. Triggered when crc calculation is done.
          */
         uint32_t dma_crc_done_int_raw: 1;
+        uint32_t reserved9: 23;
     };
     uint32_t val;
 } cp_dma_int_raw_reg_t;
@@ -123,6 +124,7 @@ typedef union {
          *  cp_crc_done_int_ena is set to 1.
          */
         uint32_t dma_crc_done_int_st: 1;
+        uint32_t reserved9: 23;
     };
     uint32_t val;
 } cp_dma_int_st_reg_t;
@@ -168,6 +170,7 @@ typedef union {
          *  This is the interrupt enable bit for cp_crc_done_int interrupt.
          */
         uint32_t dma_crc_done_int_ena: 1;
+        uint32_t reserved9: 23;
     };
     uint32_t val;
 } cp_dma_int_ena_reg_t;
@@ -213,6 +216,7 @@ typedef union {
          *  Set this bit to clear cp_crc_done_int interrupt.
          */
         uint32_t dma_crc_done_int_clr: 1;
+        uint32_t reserved9: 23;
     };
     uint32_t val;
 } cp_dma_int_clr_reg_t;
@@ -491,6 +495,7 @@ typedef union {
          *  Copy DMA FIFO empty signal.
          */
         uint32_t dma_fifo_empty: 1;
+        uint32_t reserved24: 8;
     };
     uint32_t val;
 } cp_dma_in_st_reg_t;
@@ -516,6 +521,7 @@ typedef union {
          *  Copy DMA FIFO full signal.
          */
         uint32_t dma_fifo_full: 1;
+        uint32_t reserved24: 8;
     };
     uint32_t val;
 } cp_dma_out_st_reg_t;
diff --git a/components/soc/esp32s2/include/soc/dedic_gpio_struct.h b/components/soc/esp32s2/include/soc/dedic_gpio_struct.h
index 3ccd588b97..04aae779ad 100644
--- a/components/soc/esp32s2/include/soc/dedic_gpio_struct.h
+++ b/components/soc/esp32s2/include/soc/dedic_gpio_struct.h
@@ -31,6 +31,7 @@ typedef union {
          *  gpio.
          */
         uint32_t gpio_out_drt_vlaue: 8;
+        uint32_t reserved8: 24;
     };
     uint32_t val;
 } dedic_gpio_out_drt_reg_t;
@@ -49,6 +50,7 @@ typedef union {
          *  channel's output would be masked.
          */
         uint32_t gpio_out_msk: 8;
+        uint32_t reserved16: 16;
     };
     uint32_t val;
 } dedic_gpio_out_msk_reg_t;
@@ -98,6 +100,7 @@ typedef union {
          *  clear output value; 3: inverse output value.
          */
         uint32_t gpio_out_idv_ch7: 2;
+        uint32_t reserved16: 16;
     };
     uint32_t val;
 } dedic_gpio_out_idv_reg_t;
@@ -147,6 +150,7 @@ typedef union {
          *  select CPU instructors.
          */
         uint32_t gpio_out_cpu_sel7: 1;
+        uint32_t reserved8: 24;
     };
     uint32_t val;
 } dedic_gpio_out_cpu_reg_t;
@@ -196,6 +200,7 @@ typedef union {
          *  3: three clock delay.
          */
         uint32_t gpio_in_dly_ch7: 2;
+        uint32_t reserved16: 16;
     };
     uint32_t val;
 } dedic_gpio_in_dly_reg_t;
@@ -285,6 +290,7 @@ typedef union {
          *  6/7: falling and raising edge trigger.
          */
         uint32_t gpio_intr_mode_ch7: 3;
+        uint32_t reserved24: 8;
     };
     uint32_t val;
 } dedic_gpio_intr_rcgn_reg_t;
@@ -301,6 +307,7 @@ typedef union {
          *  DEDIC_GPIO_OUT_IDV_REG.
          */
         uint32_t gpio_out_status: 8;
+        uint32_t reserved8: 24;
     };
     uint32_t val;
 } dedic_gpio_out_scan_reg_t;
@@ -314,6 +321,7 @@ typedef union {
          *  gpio in value after configured by DEDIC_GPIO_IN_DLY_REG.
          */
         uint32_t gpio_in_status: 8;
+        uint32_t reserved8: 24;
     };
     uint32_t val;
 } dedic_gpio_in_scan_reg_t;
@@ -365,6 +373,7 @@ typedef union {
          *  change configured by DEDIC_GPIO_INTR_RCGN_REG.
          */
         uint32_t gpio7_int_raw: 1;
+        uint32_t reserved8: 24;
     };
     uint32_t val;
 } dedic_gpio_intr_raw_reg_t;
@@ -406,6 +415,7 @@ typedef union {
          *  This enable bit for reg_gpio7_int_st register.
          */
         uint32_t gpio7_int_ena: 1;
+        uint32_t reserved8: 24;
     };
     uint32_t val;
 } dedic_gpio_intr_rls_reg_t;
@@ -447,6 +457,7 @@ typedef union {
          *  This is the status bit for reg_gpio7_int_raw when reg_gpio7_int_ena is set to 1.
          */
         uint32_t gpio7_int_st: 1;
+        uint32_t reserved8: 24;
     };
     uint32_t val;
 } dedic_gpio_intr_st_reg_t;
@@ -488,6 +499,7 @@ typedef union {
          *  Set this bit to clear the reg_gpio7_int_raw interrupt.
          */
         uint32_t gpio7_int_clr: 1;
+        uint32_t reserved8: 24;
     };
     uint32_t val;
 } dedic_gpio_intr_clr_reg_t;
diff --git a/components/soc/esp32s2/include/soc/efuse_struct.h b/components/soc/esp32s2/include/soc/efuse_struct.h
index a9679c267c..1ba78a4147 100644
--- a/components/soc/esp32s2/include/soc/efuse_struct.h
+++ b/components/soc/esp32s2/include/soc/efuse_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct efuse_dev_s {
     uint32_t pgm_data0;                                         /**/
     union {
         struct {
diff --git a/components/soc/esp32s2/include/soc/gpio_sd_struct.h b/components/soc/esp32s2/include/soc/gpio_sd_struct.h
index 6c28df52a8..71131ae881 100644
--- a/components/soc/esp32s2/include/soc/gpio_sd_struct.h
+++ b/components/soc/esp32s2/include/soc/gpio_sd_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gpio_sd_dev_s {
     union {
         struct {
             uint32_t duty:         8;
diff --git a/components/soc/esp32s2/include/soc/gpio_struct.h b/components/soc/esp32s2/include/soc/gpio_struct.h
index 70e82ee1fe..0dc1efdfda 100644
--- a/components/soc/esp32s2/include/soc/gpio_struct.h
+++ b/components/soc/esp32s2/include/soc/gpio_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gpio_dev_s {
     uint32_t bt_select;                               /**/
     uint32_t out;                                     /**/
     uint32_t out_w1ts;                                /**/
diff --git a/components/soc/esp32s2/include/soc/i2c_struct.h b/components/soc/esp32s2/include/soc/i2c_struct.h
index e54038aaea..150384992b 100644
--- a/components/soc/esp32s2/include/soc/i2c_struct.h
+++ b/components/soc/esp32s2/include/soc/i2c_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct i2c_dev_s {
     union {
         struct {
             uint32_t period:        14;
diff --git a/components/soc/esp32s2/include/soc/i2s_struct.h b/components/soc/esp32s2/include/soc/i2s_struct.h
index 789f2c21c2..99220407e7 100644
--- a/components/soc/esp32s2/include/soc/i2s_struct.h
+++ b/components/soc/esp32s2/include/soc/i2s_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct i2s_dev_s {
     uint32_t reserved_0;
     uint32_t reserved_4;
     union {
diff --git a/components/soc/esp32s2/include/soc/ledc_struct.h b/components/soc/esp32s2/include/soc/ledc_struct.h
index a6f02a788b..b38edb0d61 100644
--- a/components/soc/esp32s2/include/soc/ledc_struct.h
+++ b/components/soc/esp32s2/include/soc/ledc_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct ledc_dev_s {
     struct {
         struct {
             union {
diff --git a/components/soc/esp32s2/include/soc/rmt_struct.h b/components/soc/esp32s2/include/soc/rmt_struct.h
index b92c42a775..5e43004093 100644
--- a/components/soc/esp32s2/include/soc/rmt_struct.h
+++ b/components/soc/esp32s2/include/soc/rmt_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rmt_dev_s {
     uint32_t data_ch[4]; /* Data FIFO, Can only be accessed by PeriBus2 */
     struct {
         union {
@@ -300,11 +300,9 @@ typedef struct {
 } rmt_item32_t;
 
 //Allow access to RMT memory using RMTMEM.chan[0].data32[8]
-typedef volatile struct {
+typedef volatile struct rmt_mem_s {
     struct {
-        union {
-            rmt_item32_t data32[64];
-        };
+        rmt_item32_t data32[64];
     } chan[4];
 } rmt_mem_t;
 extern rmt_mem_t RMTMEM;
diff --git a/components/soc/esp32s2/include/soc/rtc_cntl_struct.h b/components/soc/esp32s2/include/soc/rtc_cntl_struct.h
index 4a901a3231..695d18c616 100644
--- a/components/soc/esp32s2/include/soc/rtc_cntl_struct.h
+++ b/components/soc/esp32s2/include/soc/rtc_cntl_struct.h
@@ -19,7 +19,7 @@ extern "C" {
 
 #include <stdint.h>
 
-typedef volatile struct {
+typedef volatile struct rtc_cntl_dev_s {
     union {
         struct {
             uint32_t sw_stall_appcpu_c0:  2;             /*{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
diff --git a/components/soc/esp32s2/include/soc/rtc_i2c_struct.h b/components/soc/esp32s2/include/soc/rtc_i2c_struct.h
index 2b9e6532d6..8f46d82fa3 100644
--- a/components/soc/esp32s2/include/soc/rtc_i2c_struct.h
+++ b/components/soc/esp32s2/include/soc/rtc_i2c_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rtc_i2c_dev_s {
     union {
         struct {
             uint32_t period:        20;             /*time period that scl = 0*/
diff --git a/components/soc/esp32s2/include/soc/rtc_io_struct.h b/components/soc/esp32s2/include/soc/rtc_io_struct.h
index c38c9fd4ab..6d4c883ed0 100644
--- a/components/soc/esp32s2/include/soc/rtc_io_struct.h
+++ b/components/soc/esp32s2/include/soc/rtc_io_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rtc_io_dev_s {
     union {
         struct {
             uint32_t reserved0:        10;
diff --git a/components/soc/esp32s2/include/soc/sens_struct.h b/components/soc/esp32s2/include/soc/sens_struct.h
index 5f56714ee6..5a029dd9fe 100644
--- a/components/soc/esp32s2/include/soc/sens_struct.h
+++ b/components/soc/esp32s2/include/soc/sens_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct sens_dev_s {
     union {
         struct {
             uint32_t sar1_clk_div:    8;                    /*clock divider*/
diff --git a/components/soc/esp32s2/include/soc/syscon_struct.h b/components/soc/esp32s2/include/soc/syscon_struct.h
index d40e2dff50..f50baa2f9c 100644
--- a/components/soc/esp32s2/include/soc/syscon_struct.h
+++ b/components/soc/esp32s2/include/soc/syscon_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct syscon_dev_s {
     union {
         struct {
             uint32_t pre_div:     10;
diff --git a/components/soc/esp32s2/include/soc/systimer_struct.h b/components/soc/esp32s2/include/soc/systimer_struct.h
index 48b1d79276..23783b39f4 100644
--- a/components/soc/esp32s2/include/soc/systimer_struct.h
+++ b/components/soc/esp32s2/include/soc/systimer_struct.h
@@ -91,6 +91,7 @@ typedef union {
          *  system timer accumulation step when using PLL
          */
         uint32_t timer_pll_step: 10;
+        uint32_t reserved20: 12;
     };
     uint32_t val;
 } systimer_step_reg_t;
@@ -201,6 +202,7 @@ typedef union {
          *  system timer target2 interrupt enable
          */
         uint32_t systimer_int2_ena: 1;
+        uint32_t reserved3: 29;
     };
     uint32_t val;
 } systimer_int_ena_reg_t;
@@ -222,6 +224,7 @@ typedef union {
          *  system timer target2 interrupt raw
          */
         uint32_t systimer_int2_raw: 1;
+        uint32_t reserved3: 29;
     };
     uint32_t val;
 } systimer_int_raw_reg_t;
@@ -243,6 +246,7 @@ typedef union {
          *  system timer target2 interrupt clear
          */
         uint32_t systimer_int2_clr: 1;
+        uint32_t reserved3: 29;
     };
     uint32_t val;
 } systimer_int_clr_reg_t;
diff --git a/components/soc/esp32s2/include/soc/twai_struct.h b/components/soc/esp32s2/include/soc/twai_struct.h
index 5cba4d409a..00a006501c 100644
--- a/components/soc/esp32s2/include/soc/twai_struct.h
+++ b/components/soc/esp32s2/include/soc/twai_struct.h
@@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
             uint32_t lom: 1;                    /* MOD.1 Listen Only Mode */
             uint32_t stm: 1;                    /* MOD.2 Self Test Mode */
             uint32_t afm: 1;                    /* MOD.3 Acceptance Filter Mode */
-            uint32_t reserved28: 28;            /* Internal Reserved. MOD.4 Sleep Mode not supported */
+            uint32_t reserved4: 28;             /* Internal Reserved. MOD.4 Sleep Mode not supported */
         };
         uint32_t val;
-    } mode_reg;                                 /* Address 0 */
+    } mode_reg;                                 /* Address 0x0000 */
     union {
         struct {
             uint32_t tr: 1;                     /* CMR.0 Transmission Request */
@@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
             uint32_t rrb: 1;                    /* CMR.2 Release Receive Buffer */
             uint32_t cdo: 1;                    /* CMR.3 Clear Data Overrun */
             uint32_t srr: 1;                    /* CMR.4 Self Reception Request */
-            uint32_t reserved27: 27;            /* Internal Reserved */
+            uint32_t reserved5: 27;             /* Internal Reserved */
         };
         uint32_t val;
-    } command_reg;                              /* Address 1 */
+    } command_reg;                              /* Address 0x0004 */
     union {
         struct {
             uint32_t rbs: 1;                    /* SR.0 Receive Buffer Status */
@@ -61,37 +61,39 @@ typedef volatile struct twai_dev_s {
             uint32_t es: 1;                     /* SR.6 Error Status */
             uint32_t bs: 1;                     /* SR.7 Bus Status */
             uint32_t ms: 1;                     /* SR.8 Miss Status */
-            uint32_t reserved23: 23;            /* Internal Reserved */
+            uint32_t reserved9: 23;             /* Internal Reserved */
         };
         uint32_t val;
-    } status_reg;                               /* Address 2 */
+    } status_reg;                               /* Address 0x0008 */
     union {
         struct {
             uint32_t ri: 1;                     /* IR.0 Receive Interrupt */
             uint32_t ti: 1;                     /* IR.1 Transmit Interrupt */
             uint32_t ei: 1;                     /* IR.2 Error Interrupt */
-            uint32_t reserved2: 2;              /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
+            uint32_t doi: 1;                    /* IR.3 Data Overrun Interrupt */
+            uint32_t reserved4: 1;              /* Internal Reserved (Wake-up not supported) */
             uint32_t epi: 1;                    /* IR.5 Error Passive Interrupt */
             uint32_t ali: 1;                    /* IR.6 Arbitration Lost Interrupt */
             uint32_t bei: 1;                    /* IR.7 Bus Error Interrupt */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } interrupt_reg;                           /* Address 3 */
+    } interrupt_reg;                           /* Address 0x000C */
     union {
         struct {
             uint32_t rie: 1;                    /* IER.0 Receive Interrupt Enable */
             uint32_t tie: 1;                    /* IER.1 Transmit Interrupt Enable */
             uint32_t eie: 1;                    /* IER.2 Error Interrupt Enable */
-            uint32_t reserved2: 2;              /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
+            uint32_t doie: 1;                   /* IER.3 Data Overrun Interrupt Enable */
+            uint32_t reserved4: 1;              /* Internal Reserved (Wake-up not supported) */
             uint32_t epie: 1;                   /* IER.5 Error Passive Interrupt Enable */
             uint32_t alie: 1;                   /* IER.6 Arbitration Lost Interrupt Enable */
             uint32_t beie: 1;                   /* IER.7 Bus Error Interrupt Enable */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } interrupt_enable_reg;                     /* Address 4 */
-    uint32_t reserved_05;                       /* Address 5 */
+    } interrupt_enable_reg;                     /* Address 0x0010 */
+    uint32_t reserved_14;
     union {
         struct {
             uint32_t brp: 14;                   /* BTR0[13:0] Baud Rate Prescaler */
@@ -99,58 +101,58 @@ typedef volatile struct twai_dev_s {
             uint32_t reserved16: 16;            /* Internal Reserved */
         };
         uint32_t val;
-    } bus_timing_0_reg;                         /* Address 6 */
+    } bus_timing_0_reg;                         /* Address 0x0018 */
     union {
         struct {
             uint32_t tseg1: 4;                  /* BTR1[3:0] Timing Segment 1 */
             uint32_t tseg2: 3;                  /* BTR1[6:4] Timing Segment 2 */
             uint32_t sam: 1;                    /* BTR1.7 Sampling*/
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } bus_timing_1_reg;                         /* Address 7 */
-    uint32_t reserved_08;                       /* Address 8 (Output control not supported) */
-    uint32_t reserved_09;                       /* Address 9 (Test Register not supported) */
-    uint32_t reserved_10;                       /* Address 10 */
+    } bus_timing_1_reg;                         /* Address 0x001C */
+    uint32_t reserved_20;                       /* Address 0x0020 (Output control not supported) */
+    uint32_t reserved_24;                       /* Address 0x0024 (Test Register not supported) */
+    uint32_t reserved_28;                       /* Address 0x0028 */
 
     //Capture and Counter Registers
     union {
         struct {
             uint32_t alc: 5;                    /* ALC[4:0] Arbitration lost capture */
-            uint32_t reserved27: 27;            /* Internal Reserved */
+            uint32_t reserved5: 27;             /* Internal Reserved */
         };
         uint32_t val;
-    } arbitration_lost_captue_reg;              /* Address 11 */
+    } arbitration_lost_captue_reg;              /* Address 0x002C */
     union {
         struct {
             uint32_t seg: 5;                    /* ECC[4:0] Error Code Segment 0 to 5 */
             uint32_t dir: 1;                    /* ECC.5 Error Direction (TX/RX) */
             uint32_t errc: 2;                   /* ECC[7:6] Error Code */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } error_code_capture_reg;                   /* Address 12 */
+    } error_code_capture_reg;                   /* Address 0x0030 */
     union {
         struct {
             uint32_t ewl: 8;                    /* EWL[7:0] Error Warning Limit */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } error_warning_limit_reg;                  /* EWLR[7:0] Error Warning Limit: Address 13 */
+    } error_warning_limit_reg;                  /* Address 0x0034 */
     union {
         struct {
             uint32_t rxerr: 8;                  /* RXERR[7:0] Receive Error Counter */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } rx_error_counter_reg;                     /* Address 12 */
+    } rx_error_counter_reg;                     /* Address 0x0038 */
     union {
         struct {
             uint32_t txerr: 8;                  /* TXERR[7:0] Receive Error Counter */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } tx_error_counter_reg;                     /* Address 15 */
+    } tx_error_counter_reg;                     /* Address 0x003C */
 
     //Shared Registers (TX Buff/RX Buff/Acc Filter)
     union {
@@ -158,45 +160,49 @@ typedef volatile struct twai_dev_s {
             union {
                 struct {
                     uint32_t byte: 8;           /* ACRx[7:0] Acceptance Code */
-                    uint32_t reserved24: 24;    /* Internal Reserved */
+                    uint32_t reserved8: 24;     /* Internal Reserved */
                 };
                 uint32_t val;
             } acr[4];
             union {
                 struct {
                     uint32_t byte: 8;           /* AMRx[7:0] Acceptance Mask */
-                    uint32_t reserved24: 24;    /* Internal Reserved */
+                    uint32_t reserved8: 24;     /* Internal Reserved */
                 };
                 uint32_t val;
             } amr[4];
-            uint32_t reserved32[5];
+            uint32_t reserved_60;
+            uint32_t reserved_64;
+            uint32_t reserved_68;
+            uint32_t reserved_6c;
+            uint32_t reserved_70;
         } acceptance_filter;
         union {
             struct {
-                uint32_t byte: 8;
-                uint32_t reserved24: 24;
+                uint32_t byte: 8;               /* TX/RX Byte X [7:0] */
+                uint32_t reserved24: 24;        /* Internal Reserved */
             };
             uint32_t val;
         } tx_rx_buffer[13];
-    };                                          /* Address 16-28 TX/RX Buffer and Acc Filter*/;
+    };                                          /* Address 0x0040 - 0x0070 */
 
     //Misc Registers
     union {
         struct {
             uint32_t rmc: 7;                    /* RMC[6:0] RX Message Counter */
-            uint32_t reserved25: 25;            /* Internal Reserved */
+            uint32_t reserved7: 25;             /* Internal Reserved */
         };
         uint32_t val;
-    } rx_message_counter_reg;                   /* Address 29 */
-    uint32_t reserved_30;                       /* Address 30 (RX Buffer Start Address not supported) */
+    } rx_message_counter_reg;                   /* Address 0x0074 */
+    uint32_t reserved_78;                       /* Address 0x0078 (RX Buffer Start Address not supported) */
     union {
         struct {
             uint32_t cd: 8;                     /* CDR[7:0] CLKOUT frequency selector based of fOSC */
             uint32_t co: 1;                     /* CDR.8 CLKOUT enable/disable */
-            uint32_t reserved24: 23;            /* Internal Reserved  */
+            uint32_t reserved9: 23;             /* Internal Reserved  */
         };
         uint32_t val;
-    } clock_divider_reg;                        /* Address 31 */
+    } clock_divider_reg;                        /* Address 0x007C */
 } twai_dev_t;
 
 _Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
diff --git a/components/soc/esp32s2/include/soc/uart_struct.h b/components/soc/esp32s2/include/soc/uart_struct.h
index a470b6b968..5eb977825b 100644
--- a/components/soc/esp32s2/include/soc/uart_struct.h
+++ b/components/soc/esp32s2/include/soc/uart_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct uart_dev_s {
     union {
         struct {
             uint32_t rw_byte;/*note: rw_byte is a uint8_t field, however, ESP32-S2 do not support 8 bits read/write*/
diff --git a/components/soc/esp32s2/include/soc/uhci_struct.h b/components/soc/esp32s2/include/soc/uhci_struct.h
index aadc2a6303..63cc074161 100644
--- a/components/soc/esp32s2/include/soc/uhci_struct.h
+++ b/components/soc/esp32s2/include/soc/uhci_struct.h
@@ -17,7 +17,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct uhci_dev_s {
     union {
         struct {
             uint32_t in_rst:             1;
diff --git a/components/soc/esp32s2/include/soc/usb_wrap_struct.h b/components/soc/esp32s2/include/soc/usb_wrap_struct.h
index 147afc3228..c196743ec0 100644
--- a/components/soc/esp32s2/include/soc/usb_wrap_struct.h
+++ b/components/soc/esp32s2/include/soc/usb_wrap_struct.h
@@ -153,6 +153,7 @@ typedef union {
          *  USB D- rx value in test.
          */
         uint32_t test_rx_dm:1;
+        uint32_t reserved:25;
     };
     uint32_t val;
 } usb_wrap_test_conf_reg_t;
diff --git a/components/soc/esp32s2/include/soc/usbh_struct.h b/components/soc/esp32s2/include/soc/usbh_struct.h
index ace84d7fa9..182a6034d1 100644
--- a/components/soc/esp32s2/include/soc/usbh_struct.h
+++ b/components/soc/esp32s2/include/soc/usbh_struct.h
@@ -830,7 +830,7 @@ typedef union {
         uint32_t bbleerr: 1;
         uint32_t nakintrpt: 1;
         uint32_t nyetintrpt: 1;
-        uint32_t reserved16: 16;
+        uint32_t reserved15: 17;
     };
     uint32_t val;
 } usb_diepint_reg_t;
diff --git a/components/soc/esp32s3/include/soc/apb_ctrl_struct.h b/components/soc/esp32s3/include/soc/apb_ctrl_struct.h
index cf4d08a6c8..b47dff1739 100644
--- a/components/soc/esp32s3/include/soc/apb_ctrl_struct.h
+++ b/components/soc/esp32s3/include/soc/apb_ctrl_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct apb_ctrl_dev_s {
     union {
         struct {
             uint32_t pre_div                       :    10;
diff --git a/components/soc/esp32s3/include/soc/apb_saradc_struct.h b/components/soc/esp32s3/include/soc/apb_saradc_struct.h
index 9c4637e31a..d6684c5387 100644
--- a/components/soc/esp32s3/include/soc/apb_saradc_struct.h
+++ b/components/soc/esp32s3/include/soc/apb_saradc_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct apb_saradc_dev_s {
     union {
         struct {
             uint32_t start_force                   :    1;
diff --git a/components/soc/esp32s3/include/soc/assist_debug_struct.h b/components/soc/esp32s3/include/soc/assist_debug_struct.h
index a9cedd804c..a6152af468 100644
--- a/components/soc/esp32s3/include/soc/assist_debug_struct.h
+++ b/components/soc/esp32s3/include/soc/assist_debug_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct assist_debug_dev_s {
     union {
         struct {
             uint32_t core_0_area_dram0_0_rd        :    1;
diff --git a/components/soc/esp32s3/include/soc/efuse_struct.h b/components/soc/esp32s3/include/soc/efuse_struct.h
index 908f07ea64..7002e4ae15 100644
--- a/components/soc/esp32s3/include/soc/efuse_struct.h
+++ b/components/soc/esp32s3/include/soc/efuse_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct efuse_dev_s {
     uint32_t pgm_data0;
     uint32_t pgm_data1;
     uint32_t pgm_data2;
diff --git a/components/soc/esp32s3/include/soc/extmem_struct.h b/components/soc/esp32s3/include/soc/extmem_struct.h
index e27283b702..58ca646294 100644
--- a/components/soc/esp32s3/include/soc/extmem_struct.h
+++ b/components/soc/esp32s3/include/soc/extmem_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct extmem_dev_s {
     union {
         struct {
             uint32_t dcache_enable                 :    1;  /*The bit is used to activate the data cache. 0: disable, 1: enable*/
diff --git a/components/soc/esp32s3/include/soc/gdma_struct.h b/components/soc/esp32s3/include/soc/gdma_struct.h
index ebb2b79e1d..730333e67d 100644
--- a/components/soc/esp32s3/include/soc/gdma_struct.h
+++ b/components/soc/esp32s3/include/soc/gdma_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gdma_dev_s {
     struct {
         struct {
             union {
diff --git a/components/soc/esp32s3/include/soc/gpio_sd_struct.h b/components/soc/esp32s3/include/soc/gpio_sd_struct.h
index bb71322294..7bb05aafb5 100644
--- a/components/soc/esp32s3/include/soc/gpio_sd_struct.h
+++ b/components/soc/esp32s3/include/soc/gpio_sd_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gpio_sd_dev_s {
     union {
         struct {
             uint32_t duty                          :    8;
diff --git a/components/soc/esp32s3/include/soc/gpio_struct.h b/components/soc/esp32s3/include/soc/gpio_struct.h
index cd2711531c..be1c3223dd 100644
--- a/components/soc/esp32s3/include/soc/gpio_struct.h
+++ b/components/soc/esp32s3/include/soc/gpio_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gpio_dev_s {
     uint32_t bt_select;
     uint32_t out;
     uint32_t out_w1ts;
diff --git a/components/soc/esp32s3/include/soc/hinf_struct.h b/components/soc/esp32s3/include/soc/hinf_struct.h
index 7accb59330..965f8bd43c 100644
--- a/components/soc/esp32s3/include/soc/hinf_struct.h
+++ b/components/soc/esp32s3/include/soc/hinf_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 
 #include <stdint.h>
 
-typedef volatile struct {
+typedef volatile struct hinf_dev_s {
     union {
         struct {
             uint32_t user_id_fn1:  16;
diff --git a/components/soc/esp32s3/include/soc/host_struct.h b/components/soc/esp32s3/include/soc/host_struct.h
index b6dad107a5..1a6b89e281 100644
--- a/components/soc/esp32s3/include/soc/host_struct.h
+++ b/components/soc/esp32s3/include/soc/host_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct host_dev_s {
     uint32_t reserved_0;
     uint32_t reserved_4;
     uint32_t reserved_8;
diff --git a/components/soc/esp32s3/include/soc/i2s_struct.h b/components/soc/esp32s3/include/soc/i2s_struct.h
index fc02adc0b8..553580d32c 100644
--- a/components/soc/esp32s3/include/soc/i2s_struct.h
+++ b/components/soc/esp32s3/include/soc/i2s_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct i2s_dev_s {
     uint32_t reserved_0;
     uint32_t reserved_4;
     uint32_t reserved_8;
diff --git a/components/soc/esp32s3/include/soc/interrupt_core0_struct.h b/components/soc/esp32s3/include/soc/interrupt_core0_struct.h
index 54ff95b47b..aa27462fb0 100644
--- a/components/soc/esp32s3/include/soc/interrupt_core0_struct.h
+++ b/components/soc/esp32s3/include/soc/interrupt_core0_struct.h
@@ -18,7 +18,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct interrupt_core0_dev_s {
     union {
         struct {
             uint32_t core0_mac_intr_map: 5;
diff --git a/components/soc/esp32s3/include/soc/interrupt_core1_struct.h b/components/soc/esp32s3/include/soc/interrupt_core1_struct.h
index ba60403aa8..d4dee29ae5 100644
--- a/components/soc/esp32s3/include/soc/interrupt_core1_struct.h
+++ b/components/soc/esp32s3/include/soc/interrupt_core1_struct.h
@@ -18,7 +18,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct interrupt_core1_dev_s {
     uint32_t reserved_0;
     uint32_t reserved_4;
     uint32_t reserved_8;
diff --git a/components/soc/esp32s3/include/soc/interrupt_struct.h b/components/soc/esp32s3/include/soc/interrupt_struct.h
index 48a595047f..03bf5df953 100644
--- a/components/soc/esp32s3/include/soc/interrupt_struct.h
+++ b/components/soc/esp32s3/include/soc/interrupt_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct interrupt_dev_s {
 } interrupt_dev_t;
 extern interrupt_dev_t INTERRUPT;
 #ifdef __cplusplus
diff --git a/components/soc/esp32s3/include/soc/ledc_struct.h b/components/soc/esp32s3/include/soc/ledc_struct.h
index 5713035056..85cea78e58 100644
--- a/components/soc/esp32s3/include/soc/ledc_struct.h
+++ b/components/soc/esp32s3/include/soc/ledc_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 
 #include <stdint.h>
 
-typedef volatile struct {
+typedef volatile struct ledc_dev_s {
     struct {
         struct {
             union {
diff --git a/components/soc/esp32s3/include/soc/peri_backup_struct.h b/components/soc/esp32s3/include/soc/peri_backup_struct.h
index 0561bd4c23..20d6673f2e 100644
--- a/components/soc/esp32s3/include/soc/peri_backup_struct.h
+++ b/components/soc/esp32s3/include/soc/peri_backup_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct peri_backup_dev_s {
     union {
         struct {
             uint32_t reg_peri_backup_flow_err      :    3;
diff --git a/components/soc/esp32s3/include/soc/rmt_struct.h b/components/soc/esp32s3/include/soc/rmt_struct.h
index bfdcf33546..275bfebce6 100644
--- a/components/soc/esp32s3/include/soc/rmt_struct.h
+++ b/components/soc/esp32s3/include/soc/rmt_struct.h
@@ -1103,9 +1103,7 @@ typedef struct {
 
 typedef struct {
     struct {
-        union {
-            volatile rmt_item32_t data32[48];
-        };
+        volatile rmt_item32_t data32[48];
     } chan[8];
 } rmt_mem_t;
 
diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h b/components/soc/esp32s3/include/soc/rtc_cntl_struct.h
index 32493d8359..d3366dd0f9 100644
--- a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h
+++ b/components/soc/esp32s3/include/soc/rtc_cntl_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rtc_cntl_dev_s {
     union {
         struct {
             uint32_t sw_stall_appcpu_c0            :    2;  /*{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
diff --git a/components/soc/esp32s3/include/soc/rtc_io_struct.h b/components/soc/esp32s3/include/soc/rtc_io_struct.h
index c366c65cf2..1154be038b 100644
--- a/components/soc/esp32s3/include/soc/rtc_io_struct.h
+++ b/components/soc/esp32s3/include/soc/rtc_io_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rtc_io_dev_s {
     union {
         struct {
             uint32_t reserved0                     :    10;
diff --git a/components/soc/esp32s3/include/soc/sdmmc_struct.h b/components/soc/esp32s3/include/soc/sdmmc_struct.h
index 78b21aa156..599528a34a 100644
--- a/components/soc/esp32s3/include/soc/sdmmc_struct.h
+++ b/components/soc/esp32s3/include/soc/sdmmc_struct.h
@@ -21,18 +21,22 @@ extern "C" {
 #endif
 
 typedef struct sdmmc_desc_s {
-    uint32_t reserved1: 1;
-    uint32_t disable_int_on_completion: 1;
-    uint32_t last_descriptor: 1;
-    uint32_t first_descriptor: 1;
-    uint32_t second_address_chained: 1;
-    uint32_t end_of_ring: 1;
-    uint32_t reserved2: 24;
-    uint32_t card_error_summary: 1;
-    uint32_t owned_by_idmac: 1;
-    uint32_t buffer1_size: 13;
-    uint32_t buffer2_size: 13;
-    uint32_t reserved3: 6;
+    struct {
+        uint32_t reserved1: 1;
+        uint32_t disable_int_on_completion: 1;
+        uint32_t last_descriptor: 1;
+        uint32_t first_descriptor: 1;
+        uint32_t second_address_chained: 1;
+        uint32_t end_of_ring: 1;
+        uint32_t reserved2: 24;
+        uint32_t card_error_summary: 1;
+        uint32_t owned_by_idmac: 1;
+    };
+    struct {
+        uint32_t buffer1_size: 13;
+        uint32_t buffer2_size: 13;
+        uint32_t reserved3: 6;
+    };
     void* buffer1_ptr;
     union {
         void* buffer2_ptr;
@@ -144,8 +148,10 @@ typedef volatile struct sdmmc_dev_s {
         uint32_t val;
     } ctype;
 
-    uint32_t blksiz: 16;        ///< block size, default 0x200
-    uint32_t : 16;
+    struct {
+        uint32_t blksiz: 16;        ///< block size, default 0x200
+        uint32_t reserved: 16;
+    };
 
     uint32_t bytcnt;            ///< number of bytes to be transferred
 
@@ -324,6 +330,7 @@ typedef volatile struct sdmmc_dev_s {
             uint32_t ces: 1;        ///< card error summary
             uint32_t reserved2: 2;
             uint32_t nis: 1;        ///< normal interrupt summary
+            uint32_t ais: 1;        ///< abnormal interrupt summary
             uint32_t fbe_code: 3;   ///< code of fatal bus error
             uint32_t fsm: 4;        ///< DMAC FSM state
             uint32_t reserved3: 15;
@@ -359,7 +366,7 @@ typedef volatile struct sdmmc_dev_s {
             uint32_t busy_clr_int_en : 1;   ///< enable generation of busy clear interrupts
             uint32_t write_thr_en : 1;      ///< equivalent of read_thr_en for writes
             uint32_t reserved1 : 13;
-            uint32_t card_threshold : 12;   ///< threshold value for reads/writes, in bytes
+            uint32_t card_threshold : 16;   ///< threshold value for reads/writes, in bytes
         };
         uint32_t val;
     } cardthrctl;
@@ -378,6 +385,7 @@ typedef volatile struct sdmmc_dev_s {
             uint32_t div_factor_m: 4;       ///< should be equal to div_factor_p
             uint32_t reserved1 : 2;
             uint32_t clk_sel : 1;           ///< clock source select (0: XTAL, 1: 160 MHz from PLL)
+            uint32_t reserved24: 8;
         };
         uint32_t val;
     } clock;
diff --git a/components/soc/esp32s3/include/soc/sens_struct.h b/components/soc/esp32s3/include/soc/sens_struct.h
index 915675bf71..3fee23099d 100644
--- a/components/soc/esp32s3/include/soc/sens_struct.h
+++ b/components/soc/esp32s3/include/soc/sens_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct sens_dev_s {
     union {
         struct {
             uint32_t sar1_clk_div                  :    8;  /*clock divider*/
diff --git a/components/soc/esp32s3/include/soc/sensitive_struct.h b/components/soc/esp32s3/include/soc/sensitive_struct.h
index 69feaf37b2..e9919cb0a6 100644
--- a/components/soc/esp32s3/include/soc/sensitive_struct.h
+++ b/components/soc/esp32s3/include/soc/sensitive_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct sensitive_dev_s {
     union {
         struct {
             uint32_t cache_dataarray_connect_lock  :    1;
diff --git a/components/soc/esp32s3/include/soc/slc_reg.h b/components/soc/esp32s3/include/soc/slc_reg.h
deleted file mode 100644
index 31b1a55e59..0000000000
--- a/components/soc/esp32s3/include/soc/slc_reg.h
+++ /dev/null
@@ -1,1912 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SLC_REG_H_
-#define _SOC_SLC_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SLC_SLCCONF0_REG          (DR_REG_SLC_BASE + 0x0)
-/* SLC_SLC0_WR_RETRY_MASK_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_WR_RETRY_MASK_EN    (BIT(18))
-#define SLC_SLC0_WR_RETRY_MASK_EN_M  (BIT(18))
-#define SLC_SLC0_WR_RETRY_MASK_EN_V  0x1
-#define SLC_SLC0_WR_RETRY_MASK_EN_S  18
-/* SLC_SLC0_TOKEN_SEL : R/W ;bitpos:[15] ;default: 1'h1 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN_SEL    (BIT(15))
-#define SLC_SLC0_TOKEN_SEL_M  (BIT(15))
-#define SLC_SLC0_TOKEN_SEL_V  0x1
-#define SLC_SLC0_TOKEN_SEL_S  15
-/* SLC_SLC0_TOKEN_AUTO_CLR : R/W ;bitpos:[14] ;default: 1'h1 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN_AUTO_CLR    (BIT(14))
-#define SLC_SLC0_TOKEN_AUTO_CLR_M  (BIT(14))
-#define SLC_SLC0_TOKEN_AUTO_CLR_V  0x1
-#define SLC_SLC0_TOKEN_AUTO_CLR_S  14
-/* SLC_SLC0_TXDATA_BURST_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_TXDATA_BURST_EN    (BIT(13))
-#define SLC_SLC0_TXDATA_BURST_EN_M  (BIT(13))
-#define SLC_SLC0_TXDATA_BURST_EN_V  0x1
-#define SLC_SLC0_TXDATA_BURST_EN_S  13
-/* SLC_SLC0_TXDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_TXDSCR_BURST_EN    (BIT(12))
-#define SLC_SLC0_TXDSCR_BURST_EN_M  (BIT(12))
-#define SLC_SLC0_TXDSCR_BURST_EN_V  0x1
-#define SLC_SLC0_TXDSCR_BURST_EN_S  12
-/* SLC_SLC0_TXLINK_AUTO_RET : R/W ;bitpos:[11] ;default: 1'h1 ; */
-/*description: .*/
-#define SLC_SLC0_TXLINK_AUTO_RET    (BIT(11))
-#define SLC_SLC0_TXLINK_AUTO_RET_M  (BIT(11))
-#define SLC_SLC0_TXLINK_AUTO_RET_V  0x1
-#define SLC_SLC0_TXLINK_AUTO_RET_S  11
-/* SLC_SLC0_RXLINK_AUTO_RET : R/W ;bitpos:[10] ;default: 1'h1 ; */
-/*description: .*/
-#define SLC_SLC0_RXLINK_AUTO_RET    (BIT(10))
-#define SLC_SLC0_RXLINK_AUTO_RET_M  (BIT(10))
-#define SLC_SLC0_RXLINK_AUTO_RET_V  0x1
-#define SLC_SLC0_RXLINK_AUTO_RET_S  10
-/* SLC_SLC0_RXDATA_BURST_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_RXDATA_BURST_EN    (BIT(9))
-#define SLC_SLC0_RXDATA_BURST_EN_M  (BIT(9))
-#define SLC_SLC0_RXDATA_BURST_EN_V  0x1
-#define SLC_SLC0_RXDATA_BURST_EN_S  9
-/* SLC_SLC0_RXDSCR_BURST_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_RXDSCR_BURST_EN    (BIT(8))
-#define SLC_SLC0_RXDSCR_BURST_EN_M  (BIT(8))
-#define SLC_SLC0_RXDSCR_BURST_EN_V  0x1
-#define SLC_SLC0_RXDSCR_BURST_EN_S  8
-/* SLC_SLC0_RX_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_NO_RESTART_CLR    (BIT(7))
-#define SLC_SLC0_RX_NO_RESTART_CLR_M  (BIT(7))
-#define SLC_SLC0_RX_NO_RESTART_CLR_V  0x1
-#define SLC_SLC0_RX_NO_RESTART_CLR_S  7
-/* SLC_SLC0_RX_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_AUTO_WRBACK    (BIT(6))
-#define SLC_SLC0_RX_AUTO_WRBACK_M  (BIT(6))
-#define SLC_SLC0_RX_AUTO_WRBACK_V  0x1
-#define SLC_SLC0_RX_AUTO_WRBACK_S  6
-/* SLC_SLC0_RX_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_RX_LOOP_TEST    (BIT(5))
-#define SLC_SLC0_RX_LOOP_TEST_M  (BIT(5))
-#define SLC_SLC0_RX_LOOP_TEST_V  0x1
-#define SLC_SLC0_RX_LOOP_TEST_S  5
-/* SLC_SLC0_TX_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_TX_LOOP_TEST    (BIT(4))
-#define SLC_SLC0_TX_LOOP_TEST_M  (BIT(4))
-#define SLC_SLC0_TX_LOOP_TEST_V  0x1
-#define SLC_SLC0_TX_LOOP_TEST_S  4
-/* SLC_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_AHBM_RST    (BIT(3))
-#define SLC_AHBM_RST_M  (BIT(3))
-#define SLC_AHBM_RST_V  0x1
-#define SLC_AHBM_RST_S  3
-/* SLC_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_AHBM_FIFO_RST    (BIT(2))
-#define SLC_AHBM_FIFO_RST_M  (BIT(2))
-#define SLC_AHBM_FIFO_RST_V  0x1
-#define SLC_AHBM_FIFO_RST_S  2
-/* SLC_SLC0_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_RST    (BIT(1))
-#define SLC_SLC0_RX_RST_M  (BIT(1))
-#define SLC_SLC0_RX_RST_V  0x1
-#define SLC_SLC0_RX_RST_S  1
-/* SLC_SLC0_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_RST    (BIT(0))
-#define SLC_SLC0_TX_RST_M  (BIT(0))
-#define SLC_SLC0_TX_RST_V  0x1
-#define SLC_SLC0_TX_RST_S  0
-
-#define SLC_INT_RAW_REG          (DR_REG_SLC_BASE + 0x4)
-/* SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW    (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_M  (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_V  0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_S  27
-/* SLC_SLC0_RX_QUICK_EOF_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW    (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_S  26
-/* SLC_CMD_DTC_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_CMD_DTC_INT_RAW    (BIT(25))
-#define SLC_CMD_DTC_INT_RAW_M  (BIT(25))
-#define SLC_CMD_DTC_INT_RAW_V  0x1
-#define SLC_CMD_DTC_INT_RAW_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW    (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW    (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW    (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW    (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW    (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW    (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_S  19
-/* SLC_SLC0_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOHOST_INT_RAW    (BIT(18))
-#define SLC_SLC0_TOHOST_INT_RAW_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_RAW_V  0x1
-#define SLC_SLC0_TOHOST_INT_RAW_S  18
-/* SLC_SLC0_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_EOF_INT_RAW    (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_RAW_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_RAW_V  0x1
-#define SLC_SLC0_RX_EOF_INT_RAW_S  17
-/* SLC_SLC0_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DONE_INT_RAW    (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_RAW_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_RAW_V  0x1
-#define SLC_SLC0_RX_DONE_INT_RAW_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW    (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW_S  15
-/* SLC_SLC0_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DONE_INT_RAW    (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_RAW_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_RAW_V  0x1
-#define SLC_SLC0_TX_DONE_INT_RAW_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW    (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW    (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_S  12
-/* SLC_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_OVF_INT_RAW    (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_RAW_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_RAW_V  0x1
-#define SLC_SLC0_TX_OVF_INT_RAW_S  11
-/* SLC_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_UDF_INT_RAW    (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_RAW_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_RAW_V  0x1
-#define SLC_SLC0_RX_UDF_INT_RAW_S  10
-/* SLC_SLC0_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_START_INT_RAW    (BIT(9))
-#define SLC_SLC0_TX_START_INT_RAW_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_RAW_V  0x1
-#define SLC_SLC0_TX_START_INT_RAW_S  9
-/* SLC_SLC0_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_START_INT_RAW    (BIT(8))
-#define SLC_SLC0_RX_START_INT_RAW_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_RAW_V  0x1
-#define SLC_SLC0_RX_START_INT_RAW_S  8
-/* SLC_FRHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT7_INT_RAW    (BIT(7))
-#define SLC_FRHOST_BIT7_INT_RAW_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT7_INT_RAW_S  7
-/* SLC_FRHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT6_INT_RAW    (BIT(6))
-#define SLC_FRHOST_BIT6_INT_RAW_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT6_INT_RAW_S  6
-/* SLC_FRHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT5_INT_RAW    (BIT(5))
-#define SLC_FRHOST_BIT5_INT_RAW_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT5_INT_RAW_S  5
-/* SLC_FRHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT4_INT_RAW    (BIT(4))
-#define SLC_FRHOST_BIT4_INT_RAW_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT4_INT_RAW_S  4
-/* SLC_FRHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT3_INT_RAW    (BIT(3))
-#define SLC_FRHOST_BIT3_INT_RAW_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT3_INT_RAW_S  3
-/* SLC_FRHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT2_INT_RAW    (BIT(2))
-#define SLC_FRHOST_BIT2_INT_RAW_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT2_INT_RAW_S  2
-/* SLC_FRHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT1_INT_RAW    (BIT(1))
-#define SLC_FRHOST_BIT1_INT_RAW_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT1_INT_RAW_S  1
-/* SLC_FRHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT0_INT_RAW    (BIT(0))
-#define SLC_FRHOST_BIT0_INT_RAW_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT0_INT_RAW_S  0
-
-#define SLC_INT_ST_REG          (DR_REG_SLC_BASE + 0x8)
-/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST    (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_M  (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_V  0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_S  27
-/* SLC_SLC0_RX_QUICK_EOF_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST    (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST_S  26
-/* SLC_CMD_DTC_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_CMD_DTC_INT_ST    (BIT(25))
-#define SLC_CMD_DTC_INT_ST_M  (BIT(25))
-#define SLC_CMD_DTC_INT_ST_V  0x1
-#define SLC_CMD_DTC_INT_ST_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_ERR_EOF_INT_ST    (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ST_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST    (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_RD_ACK_INT_ST    (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ST_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST    (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST    (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST    (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST_S  19
-/* SLC_SLC0_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOHOST_INT_ST    (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST_V  0x1
-#define SLC_SLC0_TOHOST_INT_ST_S  18
-/* SLC_SLC0_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_EOF_INT_ST    (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST_V  0x1
-#define SLC_SLC0_RX_EOF_INT_ST_S  17
-/* SLC_SLC0_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DONE_INT_ST    (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST_V  0x1
-#define SLC_SLC0_RX_DONE_INT_ST_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_SUC_EOF_INT_ST    (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ST_S  15
-/* SLC_SLC0_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DONE_INT_ST    (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST_V  0x1
-#define SLC_SLC0_TX_DONE_INT_ST_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST    (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST    (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST_S  12
-/* SLC_SLC0_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_OVF_INT_ST    (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST_V  0x1
-#define SLC_SLC0_TX_OVF_INT_ST_S  11
-/* SLC_SLC0_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_UDF_INT_ST    (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST_V  0x1
-#define SLC_SLC0_RX_UDF_INT_ST_S  10
-/* SLC_SLC0_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_START_INT_ST    (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST_V  0x1
-#define SLC_SLC0_TX_START_INT_ST_S  9
-/* SLC_SLC0_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_START_INT_ST    (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST_V  0x1
-#define SLC_SLC0_RX_START_INT_ST_S  8
-/* SLC_FRHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT7_INT_ST    (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST_V  0x1
-#define SLC_FRHOST_BIT7_INT_ST_S  7
-/* SLC_FRHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT6_INT_ST    (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST_V  0x1
-#define SLC_FRHOST_BIT6_INT_ST_S  6
-/* SLC_FRHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT5_INT_ST    (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST_V  0x1
-#define SLC_FRHOST_BIT5_INT_ST_S  5
-/* SLC_FRHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT4_INT_ST    (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST_V  0x1
-#define SLC_FRHOST_BIT4_INT_ST_S  4
-/* SLC_FRHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT3_INT_ST    (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST_V  0x1
-#define SLC_FRHOST_BIT3_INT_ST_S  3
-/* SLC_FRHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT2_INT_ST    (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST_V  0x1
-#define SLC_FRHOST_BIT2_INT_ST_S  2
-/* SLC_FRHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT1_INT_ST    (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST_V  0x1
-#define SLC_FRHOST_BIT1_INT_ST_S  1
-/* SLC_FRHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT0_INT_ST    (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST_V  0x1
-#define SLC_FRHOST_BIT0_INT_ST_S  0
-
-#define SLC_INT_ENA_REG          (DR_REG_SLC_BASE + 0xC)
-/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA    (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_M  (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_V  0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_S  27
-/* SLC_SLC0_RX_QUICK_EOF_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA    (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_S  26
-/* SLC_CMD_DTC_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_CMD_DTC_INT_ENA    (BIT(25))
-#define SLC_CMD_DTC_INT_ENA_M  (BIT(25))
-#define SLC_CMD_DTC_INT_ENA_V  0x1
-#define SLC_CMD_DTC_INT_ENA_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA    (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA    (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA    (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA    (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA    (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA    (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_S  19
-/* SLC_SLC0_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOHOST_INT_ENA    (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA_V  0x1
-#define SLC_SLC0_TOHOST_INT_ENA_S  18
-/* SLC_SLC0_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_EOF_INT_ENA    (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA_V  0x1
-#define SLC_SLC0_RX_EOF_INT_ENA_S  17
-/* SLC_SLC0_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DONE_INT_ENA    (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA_V  0x1
-#define SLC_SLC0_RX_DONE_INT_ENA_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA    (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA_S  15
-/* SLC_SLC0_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DONE_INT_ENA    (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA_V  0x1
-#define SLC_SLC0_TX_DONE_INT_ENA_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_S  12
-/* SLC_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_OVF_INT_ENA    (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA_V  0x1
-#define SLC_SLC0_TX_OVF_INT_ENA_S  11
-/* SLC_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_UDF_INT_ENA    (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA_V  0x1
-#define SLC_SLC0_RX_UDF_INT_ENA_S  10
-/* SLC_SLC0_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_START_INT_ENA    (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA_V  0x1
-#define SLC_SLC0_TX_START_INT_ENA_S  9
-/* SLC_SLC0_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_START_INT_ENA    (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA_V  0x1
-#define SLC_SLC0_RX_START_INT_ENA_S  8
-/* SLC_FRHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT7_INT_ENA    (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT7_INT_ENA_S  7
-/* SLC_FRHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT6_INT_ENA    (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT6_INT_ENA_S  6
-/* SLC_FRHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT5_INT_ENA    (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT5_INT_ENA_S  5
-/* SLC_FRHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT4_INT_ENA    (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT4_INT_ENA_S  4
-/* SLC_FRHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT3_INT_ENA    (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT3_INT_ENA_S  3
-/* SLC_FRHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT2_INT_ENA    (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT2_INT_ENA_S  2
-/* SLC_FRHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT1_INT_ENA    (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT1_INT_ENA_S  1
-/* SLC_FRHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT0_INT_ENA    (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT0_INT_ENA_S  0
-
-#define SLC_INT_CLR_REG          (DR_REG_SLC_BASE + 0x10)
-/* SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR    (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_M  (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_V  0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_S  27
-/* SLC_SLC0_RX_QUICK_EOF_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR    (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_S  26
-/* SLC_CMD_DTC_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_CMD_DTC_INT_CLR    (BIT(25))
-#define SLC_CMD_DTC_INT_CLR_M  (BIT(25))
-#define SLC_CMD_DTC_INT_CLR_V  0x1
-#define SLC_CMD_DTC_INT_CLR_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR    (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR    (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR    (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR    (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR    (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR    (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_S  19
-/* SLC_SLC0_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOHOST_INT_CLR    (BIT(18))
-#define SLC_SLC0_TOHOST_INT_CLR_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_CLR_V  0x1
-#define SLC_SLC0_TOHOST_INT_CLR_S  18
-/* SLC_SLC0_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_EOF_INT_CLR    (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_CLR_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_CLR_V  0x1
-#define SLC_SLC0_RX_EOF_INT_CLR_S  17
-/* SLC_SLC0_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DONE_INT_CLR    (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_CLR_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_CLR_V  0x1
-#define SLC_SLC0_RX_DONE_INT_CLR_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR    (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR_S  15
-/* SLC_SLC0_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DONE_INT_CLR    (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_CLR_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_CLR_V  0x1
-#define SLC_SLC0_TX_DONE_INT_CLR_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR    (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR    (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_S  12
-/* SLC_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_OVF_INT_CLR    (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_CLR_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_CLR_V  0x1
-#define SLC_SLC0_TX_OVF_INT_CLR_S  11
-/* SLC_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_UDF_INT_CLR    (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_CLR_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_CLR_V  0x1
-#define SLC_SLC0_RX_UDF_INT_CLR_S  10
-/* SLC_SLC0_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_START_INT_CLR    (BIT(9))
-#define SLC_SLC0_TX_START_INT_CLR_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_CLR_V  0x1
-#define SLC_SLC0_TX_START_INT_CLR_S  9
-/* SLC_SLC0_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_START_INT_CLR    (BIT(8))
-#define SLC_SLC0_RX_START_INT_CLR_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_CLR_V  0x1
-#define SLC_SLC0_RX_START_INT_CLR_S  8
-/* SLC_FRHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT7_INT_CLR    (BIT(7))
-#define SLC_FRHOST_BIT7_INT_CLR_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT7_INT_CLR_S  7
-/* SLC_FRHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT6_INT_CLR    (BIT(6))
-#define SLC_FRHOST_BIT6_INT_CLR_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT6_INT_CLR_S  6
-/* SLC_FRHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT5_INT_CLR    (BIT(5))
-#define SLC_FRHOST_BIT5_INT_CLR_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT5_INT_CLR_S  5
-/* SLC_FRHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT4_INT_CLR    (BIT(4))
-#define SLC_FRHOST_BIT4_INT_CLR_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT4_INT_CLR_S  4
-/* SLC_FRHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT3_INT_CLR    (BIT(3))
-#define SLC_FRHOST_BIT3_INT_CLR_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT3_INT_CLR_S  3
-/* SLC_FRHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT2_INT_CLR    (BIT(2))
-#define SLC_FRHOST_BIT2_INT_CLR_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT2_INT_CLR_S  2
-/* SLC_FRHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT1_INT_CLR    (BIT(1))
-#define SLC_FRHOST_BIT1_INT_CLR_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT1_INT_CLR_S  1
-/* SLC_FRHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT0_INT_CLR    (BIT(0))
-#define SLC_FRHOST_BIT0_INT_CLR_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT0_INT_CLR_S  0
-
-#define SLC_SLCRX_STATUS_REG          (DR_REG_SLC_BASE + 0x24)
-/* SLC_SLC0_RX_BUF_LEN : RO ;bitpos:[13:2] ;default: 12'h0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_BUF_LEN    0x00000FFF
-#define SLC_SLC0_RX_BUF_LEN_M  ((SLC_SLC0_RX_BUF_LEN_V)<<(SLC_SLC0_RX_BUF_LEN_S))
-#define SLC_SLC0_RX_BUF_LEN_V  0xFFF
-#define SLC_SLC0_RX_BUF_LEN_S  2
-/* SLC_SLC0_RX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_RX_EMPTY    (BIT(1))
-#define SLC_SLC0_RX_EMPTY_M  (BIT(1))
-#define SLC_SLC0_RX_EMPTY_V  0x1
-#define SLC_SLC0_RX_EMPTY_S  1
-/* SLC_SLC0_RX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_FULL    (BIT(0))
-#define SLC_SLC0_RX_FULL_M  (BIT(0))
-#define SLC_SLC0_RX_FULL_V  0x1
-#define SLC_SLC0_RX_FULL_S  0
-
-#define SLC_RXFIFO_PUSH_REG          (DR_REG_SLC_BASE + 0x28)
-/* SLC_SLC0_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: .*/
-#define SLC_SLC0_RXFIFO_PUSH    (BIT(16))
-#define SLC_SLC0_RXFIFO_PUSH_M  (BIT(16))
-#define SLC_SLC0_RXFIFO_PUSH_V  0x1
-#define SLC_SLC0_RXFIFO_PUSH_S  16
-/* SLC_SLC0_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: .*/
-#define SLC_SLC0_RXFIFO_WDATA    0x000001FF
-#define SLC_SLC0_RXFIFO_WDATA_M  ((SLC_SLC0_RXFIFO_WDATA_V)<<(SLC_SLC0_RXFIFO_WDATA_S))
-#define SLC_SLC0_RXFIFO_WDATA_V  0x1FF
-#define SLC_SLC0_RXFIFO_WDATA_S  0
-
-#define SLC_SLCTX_STATUS_REG          (DR_REG_SLC_BASE + 0x30)
-/* SLC_SLC0_TX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_TX_EMPTY    (BIT(1))
-#define SLC_SLC0_TX_EMPTY_M  (BIT(1))
-#define SLC_SLC0_TX_EMPTY_V  0x1
-#define SLC_SLC0_TX_EMPTY_S  1
-/* SLC_SLC0_TX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_FULL    (BIT(0))
-#define SLC_SLC0_TX_FULL_M  (BIT(0))
-#define SLC_SLC0_TX_FULL_V  0x1
-#define SLC_SLC0_TX_FULL_S  0
-
-#define SLC_TXFIFO_POP_REG          (DR_REG_SLC_BASE + 0x34)
-/* SLC_SLC0_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TXFIFO_POP    (BIT(16))
-#define SLC_SLC0_TXFIFO_POP_M  (BIT(16))
-#define SLC_SLC0_TXFIFO_POP_V  0x1
-#define SLC_SLC0_TXFIFO_POP_S  16
-/* SLC_SLC0_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TXFIFO_RDATA    0x000007FF
-#define SLC_SLC0_TXFIFO_RDATA_M  ((SLC_SLC0_TXFIFO_RDATA_V)<<(SLC_SLC0_TXFIFO_RDATA_S))
-#define SLC_SLC0_TXFIFO_RDATA_V  0x7FF
-#define SLC_SLC0_TXFIFO_RDATA_S  0
-
-#define SLC_RX_LINK_REG          (DR_REG_SLC_BASE + 0x3C)
-/* SLC_SLC0_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: .*/
-#define SLC_SLC0_RXLINK_PARK    (BIT(31))
-#define SLC_SLC0_RXLINK_PARK_M  (BIT(31))
-#define SLC_SLC0_RXLINK_PARK_V  0x1
-#define SLC_SLC0_RXLINK_PARK_S  31
-/* SLC_SLC0_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RXLINK_RESTART    (BIT(30))
-#define SLC_SLC0_RXLINK_RESTART_M  (BIT(30))
-#define SLC_SLC0_RXLINK_RESTART_V  0x1
-#define SLC_SLC0_RXLINK_RESTART_S  30
-/* SLC_SLC0_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RXLINK_START    (BIT(29))
-#define SLC_SLC0_RXLINK_START_M  (BIT(29))
-#define SLC_SLC0_RXLINK_START_V  0x1
-#define SLC_SLC0_RXLINK_START_S  29
-/* SLC_SLC0_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RXLINK_STOP    (BIT(28))
-#define SLC_SLC0_RXLINK_STOP_M  (BIT(28))
-#define SLC_SLC0_RXLINK_STOP_V  0x1
-#define SLC_SLC0_RXLINK_STOP_S  28
-/* SLC_SLC0_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: .*/
-#define SLC_SLC0_RXLINK_ADDR    0x000FFFFF
-#define SLC_SLC0_RXLINK_ADDR_M  ((SLC_SLC0_RXLINK_ADDR_V)<<(SLC_SLC0_RXLINK_ADDR_S))
-#define SLC_SLC0_RXLINK_ADDR_V  0xFFFFF
-#define SLC_SLC0_RXLINK_ADDR_S  0
-
-#define SLC_TX_LINK_REG          (DR_REG_SLC_BASE + 0x40)
-/* SLC_SLC0_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TXLINK_PARK    (BIT(31))
-#define SLC_SLC0_TXLINK_PARK_M  (BIT(31))
-#define SLC_SLC0_TXLINK_PARK_V  0x1
-#define SLC_SLC0_TXLINK_PARK_S  31
-/* SLC_SLC0_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TXLINK_RESTART    (BIT(30))
-#define SLC_SLC0_TXLINK_RESTART_M  (BIT(30))
-#define SLC_SLC0_TXLINK_RESTART_V  0x1
-#define SLC_SLC0_TXLINK_RESTART_S  30
-/* SLC_SLC0_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TXLINK_START    (BIT(29))
-#define SLC_SLC0_TXLINK_START_M  (BIT(29))
-#define SLC_SLC0_TXLINK_START_V  0x1
-#define SLC_SLC0_TXLINK_START_S  29
-/* SLC_SLC0_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TXLINK_STOP    (BIT(28))
-#define SLC_SLC0_TXLINK_STOP_M  (BIT(28))
-#define SLC_SLC0_TXLINK_STOP_V  0x1
-#define SLC_SLC0_TXLINK_STOP_S  28
-/* SLC_SLC0_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TXLINK_ADDR    0x000FFFFF
-#define SLC_SLC0_TXLINK_ADDR_M  ((SLC_SLC0_TXLINK_ADDR_V)<<(SLC_SLC0_TXLINK_ADDR_S))
-#define SLC_SLC0_TXLINK_ADDR_V  0xFFFFF
-#define SLC_SLC0_TXLINK_ADDR_S  0
-
-#define SLC_SLCINTVEC_TOHOST_REG          (DR_REG_SLC_BASE + 0x4C)
-/* SLC_SLC0_TOHOST_INTVEC : WO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TOHOST_INTVEC    0x000000FF
-#define SLC_SLC0_TOHOST_INTVEC_M  ((SLC_SLC0_TOHOST_INTVEC_V)<<(SLC_SLC0_TOHOST_INTVEC_S))
-#define SLC_SLC0_TOHOST_INTVEC_V  0xFF
-#define SLC_SLC0_TOHOST_INTVEC_S  0
-
-#define SLC_TOKEN0_REG          (DR_REG_SLC_BASE + 0x50)
-/* SLC_SLC0_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN0    0x00000FFF
-#define SLC_SLC0_TOKEN0_M  ((SLC_SLC0_TOKEN0_V)<<(SLC_SLC0_TOKEN0_S))
-#define SLC_SLC0_TOKEN0_V  0xFFF
-#define SLC_SLC0_TOKEN0_S  16
-/* SLC_SLC0_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN0_INC_MORE    (BIT(14))
-#define SLC_SLC0_TOKEN0_INC_MORE_M  (BIT(14))
-#define SLC_SLC0_TOKEN0_INC_MORE_V  0x1
-#define SLC_SLC0_TOKEN0_INC_MORE_S  14
-/* SLC_SLC0_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN0_INC    (BIT(13))
-#define SLC_SLC0_TOKEN0_INC_M  (BIT(13))
-#define SLC_SLC0_TOKEN0_INC_V  0x1
-#define SLC_SLC0_TOKEN0_INC_S  13
-/* SLC_SLC0_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN0_WR    (BIT(12))
-#define SLC_SLC0_TOKEN0_WR_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_WR_V  0x1
-#define SLC_SLC0_TOKEN0_WR_S  12
-/* SLC_SLC0_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN0_WDATA    0x00000FFF
-#define SLC_SLC0_TOKEN0_WDATA_M  ((SLC_SLC0_TOKEN0_WDATA_V)<<(SLC_SLC0_TOKEN0_WDATA_S))
-#define SLC_SLC0_TOKEN0_WDATA_V  0xFFF
-#define SLC_SLC0_TOKEN0_WDATA_S  0
-
-#define SLC_TOKEN1_REG          (DR_REG_SLC_BASE + 0x54)
-/* SLC_SLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN1    0x00000FFF
-#define SLC_SLC0_TOKEN1_M  ((SLC_SLC0_TOKEN1_V)<<(SLC_SLC0_TOKEN1_S))
-#define SLC_SLC0_TOKEN1_V  0xFFF
-#define SLC_SLC0_TOKEN1_S  16
-/* SLC_SLC0_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN1_INC_MORE    (BIT(14))
-#define SLC_SLC0_TOKEN1_INC_MORE_M  (BIT(14))
-#define SLC_SLC0_TOKEN1_INC_MORE_V  0x1
-#define SLC_SLC0_TOKEN1_INC_MORE_S  14
-/* SLC_SLC0_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN1_INC    (BIT(13))
-#define SLC_SLC0_TOKEN1_INC_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_INC_V  0x1
-#define SLC_SLC0_TOKEN1_INC_S  13
-/* SLC_SLC0_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN1_WR    (BIT(12))
-#define SLC_SLC0_TOKEN1_WR_M  (BIT(12))
-#define SLC_SLC0_TOKEN1_WR_V  0x1
-#define SLC_SLC0_TOKEN1_WR_S  12
-/* SLC_SLC0_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN1_WDATA    0x00000FFF
-#define SLC_SLC0_TOKEN1_WDATA_M  ((SLC_SLC0_TOKEN1_WDATA_V)<<(SLC_SLC0_TOKEN1_WDATA_S))
-#define SLC_SLC0_TOKEN1_WDATA_V  0xFFF
-#define SLC_SLC0_TOKEN1_WDATA_S  0
-
-#define SLC_SLCCONF1_REG          (DR_REG_SLC_BASE + 0x60)
-/* SLC_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_CLK_EN    (BIT(22))
-#define SLC_CLK_EN_M  (BIT(22))
-#define SLC_CLK_EN_V  0x1
-#define SLC_CLK_EN_S  22
-/* SLC_HOST_INT_LEVEL_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_HOST_INT_LEVEL_SEL    (BIT(19))
-#define SLC_HOST_INT_LEVEL_SEL_M  (BIT(19))
-#define SLC_HOST_INT_LEVEL_SEL_V  0x1
-#define SLC_HOST_INT_LEVEL_SEL_S  19
-/* SLC_SLC0_RX_STITCH_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_RX_STITCH_EN    (BIT(6))
-#define SLC_SLC0_RX_STITCH_EN_M  (BIT(6))
-#define SLC_SLC0_RX_STITCH_EN_V  0x1
-#define SLC_SLC0_RX_STITCH_EN_S  6
-/* SLC_SLC0_TX_STITCH_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_TX_STITCH_EN    (BIT(5))
-#define SLC_SLC0_TX_STITCH_EN_M  (BIT(5))
-#define SLC_SLC0_TX_STITCH_EN_V  0x1
-#define SLC_SLC0_TX_STITCH_EN_S  5
-/* SLC_SLC0_LEN_AUTO_CLR : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_LEN_AUTO_CLR    (BIT(4))
-#define SLC_SLC0_LEN_AUTO_CLR_M  (BIT(4))
-#define SLC_SLC0_LEN_AUTO_CLR_V  0x1
-#define SLC_SLC0_LEN_AUTO_CLR_S  4
-/* SLC_CMD_HOLD_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_CMD_HOLD_EN    (BIT(3))
-#define SLC_CMD_HOLD_EN_M  (BIT(3))
-#define SLC_CMD_HOLD_EN_V  0x1
-#define SLC_CMD_HOLD_EN_S  3
-/* SLC_SLC0_RX_CHECK_SUM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_CHECK_SUM_EN    (BIT(2))
-#define SLC_SLC0_RX_CHECK_SUM_EN_M  (BIT(2))
-#define SLC_SLC0_RX_CHECK_SUM_EN_V  0x1
-#define SLC_SLC0_RX_CHECK_SUM_EN_S  2
-/* SLC_SLC0_TX_CHECK_SUM_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_CHECK_SUM_EN    (BIT(1))
-#define SLC_SLC0_TX_CHECK_SUM_EN_M  (BIT(1))
-#define SLC_SLC0_TX_CHECK_SUM_EN_V  0x1
-#define SLC_SLC0_TX_CHECK_SUM_EN_S  1
-/* SLC_SLC0_CHECK_OWNER : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_CHECK_OWNER    (BIT(0))
-#define SLC_SLC0_CHECK_OWNER_M  (BIT(0))
-#define SLC_SLC0_CHECK_OWNER_V  0x1
-#define SLC_SLC0_CHECK_OWNER_S  0
-
-#define SLC_STATE0_REG          (DR_REG_SLC_BASE + 0x64)
-/* SLC_SLC0_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_STATE0    0xFFFFFFFF
-#define SLC_SLC0_STATE0_M  ((SLC_SLC0_STATE0_V)<<(SLC_SLC0_STATE0_S))
-#define SLC_SLC0_STATE0_V  0xFFFFFFFF
-#define SLC_SLC0_STATE0_S  0
-
-#define SLC_STATE1_REG          (DR_REG_SLC_BASE + 0x68)
-/* SLC_SLC0_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_STATE1    0xFFFFFFFF
-#define SLC_SLC0_STATE1_M  ((SLC_SLC0_STATE1_V)<<(SLC_SLC0_STATE1_S))
-#define SLC_SLC0_STATE1_V  0xFFFFFFFF
-#define SLC_SLC0_STATE1_S  0
-
-#define SLC_SLCBRIDGE_CONF_REG          (DR_REG_SLC_BASE + 0x74)
-/* SLC_TX_PUSH_IDLE_NUM : R/W ;bitpos:[31:16] ;default: 16'ha ; */
-/*description: .*/
-#define SLC_TX_PUSH_IDLE_NUM    0x0000FFFF
-#define SLC_TX_PUSH_IDLE_NUM_M  ((SLC_TX_PUSH_IDLE_NUM_V)<<(SLC_TX_PUSH_IDLE_NUM_S))
-#define SLC_TX_PUSH_IDLE_NUM_V  0xFFFF
-#define SLC_TX_PUSH_IDLE_NUM_S  16
-/* SLC_HDA_MAP_128K : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: .*/
-#define SLC_HDA_MAP_128K    (BIT(13))
-#define SLC_HDA_MAP_128K_M  (BIT(13))
-#define SLC_HDA_MAP_128K_V  0x1
-#define SLC_HDA_MAP_128K_S  13
-/* SLC_SLC0_TX_DUMMY_MODE : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DUMMY_MODE    (BIT(12))
-#define SLC_SLC0_TX_DUMMY_MODE_M  (BIT(12))
-#define SLC_SLC0_TX_DUMMY_MODE_V  0x1
-#define SLC_SLC0_TX_DUMMY_MODE_S  12
-/* SLC_FIFO_MAP_ENA : R/W ;bitpos:[11:8] ;default: 4'h7 ; */
-/*description: .*/
-#define SLC_FIFO_MAP_ENA    0x0000000F
-#define SLC_FIFO_MAP_ENA_M  ((SLC_FIFO_MAP_ENA_V)<<(SLC_FIFO_MAP_ENA_S))
-#define SLC_FIFO_MAP_ENA_V  0xF
-#define SLC_FIFO_MAP_ENA_S  8
-/* SLC_TXEOF_ENA : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
-/*description: .*/
-#define SLC_TXEOF_ENA    0x0000003F
-#define SLC_TXEOF_ENA_M  ((SLC_TXEOF_ENA_V)<<(SLC_TXEOF_ENA_S))
-#define SLC_TXEOF_ENA_V  0x3F
-#define SLC_TXEOF_ENA_S  0
-
-#define SLC_TO_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x78)
-/* SLC_SLC0_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TO_EOF_DES_ADDR    0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_DES_ADDR_M  ((SLC_SLC0_TO_EOF_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_DES_ADDR_S))
-#define SLC_SLC0_TO_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_DES_ADDR_S  0
-
-#define SLC_TX_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x7C)
-/* SLC_SLC0_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR    0xFFFFFFFF
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_M  ((SLC_SLC0_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_SUC_EOF_DES_ADDR_S))
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_S  0
-
-#define SLC_TO_EOF_BFR_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x80)
-/* SLC_SLC0_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR    0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_M  ((SLC_SLC0_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_BFR_DES_ADDR_S))
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_S  0
-
-#define SLC_AHB_TEST_REG          (DR_REG_SLC_BASE + 0x90)
-/* SLC_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: .*/
-#define SLC_AHB_TESTADDR    0x00000003
-#define SLC_AHB_TESTADDR_M  ((SLC_AHB_TESTADDR_V)<<(SLC_AHB_TESTADDR_S))
-#define SLC_AHB_TESTADDR_V  0x3
-#define SLC_AHB_TESTADDR_S  4
-/* SLC_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: .*/
-#define SLC_AHB_TESTMODE    0x00000007
-#define SLC_AHB_TESTMODE_M  ((SLC_AHB_TESTMODE_V)<<(SLC_AHB_TESTMODE_S))
-#define SLC_AHB_TESTMODE_V  0x7
-#define SLC_AHB_TESTMODE_S  0
-
-#define SLC_SDIO_ST_REG          (DR_REG_SLC_BASE + 0x94)
-/* SLC_FUNC1_ACC_STATE : RO ;bitpos:[20:16] ;default: 5'b0 ; */
-/*description: .*/
-#define SLC_FUNC1_ACC_STATE    0x0000001F
-#define SLC_FUNC1_ACC_STATE_M  ((SLC_FUNC1_ACC_STATE_V)<<(SLC_FUNC1_ACC_STATE_S))
-#define SLC_FUNC1_ACC_STATE_V  0x1F
-#define SLC_FUNC1_ACC_STATE_S  16
-/* SLC_BUS_ST : RO ;bitpos:[14:12] ;default: 3'b0 ; */
-/*description: .*/
-#define SLC_BUS_ST    0x00000007
-#define SLC_BUS_ST_M  ((SLC_BUS_ST_V)<<(SLC_BUS_ST_S))
-#define SLC_BUS_ST_V  0x7
-#define SLC_BUS_ST_S  12
-/* SLC_SDIO_WAKEUP : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SDIO_WAKEUP    (BIT(8))
-#define SLC_SDIO_WAKEUP_M  (BIT(8))
-#define SLC_SDIO_WAKEUP_V  0x1
-#define SLC_SDIO_WAKEUP_S  8
-/* SLC_FUNC_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: .*/
-#define SLC_FUNC_ST    0x0000000F
-#define SLC_FUNC_ST_M  ((SLC_FUNC_ST_V)<<(SLC_FUNC_ST_S))
-#define SLC_FUNC_ST_V  0xF
-#define SLC_FUNC_ST_S  4
-/* SLC_CMD_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: .*/
-#define SLC_CMD_ST    0x00000007
-#define SLC_CMD_ST_M  ((SLC_CMD_ST_V)<<(SLC_CMD_ST_S))
-#define SLC_CMD_ST_V  0x7
-#define SLC_CMD_ST_S  0
-
-#define SLC_RX_DSCR_CONF_REG          (DR_REG_SLC_BASE + 0x98)
-/* SLC_SLC0_RD_RETRY_THRESHOLD : R/W ;bitpos:[15:5] ;default: 11'h80 ; */
-/*description: .*/
-#define SLC_SLC0_RD_RETRY_THRESHOLD    0x000007FF
-#define SLC_SLC0_RD_RETRY_THRESHOLD_M  ((SLC_SLC0_RD_RETRY_THRESHOLD_V)<<(SLC_SLC0_RD_RETRY_THRESHOLD_S))
-#define SLC_SLC0_RD_RETRY_THRESHOLD_V  0x7FF
-#define SLC_SLC0_RD_RETRY_THRESHOLD_S  5
-/* SLC_SLC0_RX_FILL_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_RX_FILL_EN    (BIT(4))
-#define SLC_SLC0_RX_FILL_EN_M  (BIT(4))
-#define SLC_SLC0_RX_FILL_EN_V  0x1
-#define SLC_SLC0_RX_FILL_EN_S  4
-/* SLC_SLC0_RX_EOF_MODE : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_RX_EOF_MODE    (BIT(3))
-#define SLC_SLC0_RX_EOF_MODE_M  (BIT(3))
-#define SLC_SLC0_RX_EOF_MODE_V  0x1
-#define SLC_SLC0_RX_EOF_MODE_S  3
-/* SLC_SLC0_RX_FILL_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_FILL_MODE    (BIT(2))
-#define SLC_SLC0_RX_FILL_MODE_M  (BIT(2))
-#define SLC_SLC0_RX_FILL_MODE_V  0x1
-#define SLC_SLC0_RX_FILL_MODE_S  2
-/* SLC_SLC0_INFOR_NO_REPLACE : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SLC_SLC0_INFOR_NO_REPLACE    (BIT(1))
-#define SLC_SLC0_INFOR_NO_REPLACE_M  (BIT(1))
-#define SLC_SLC0_INFOR_NO_REPLACE_V  0x1
-#define SLC_SLC0_INFOR_NO_REPLACE_S  1
-/* SLC_SLC0_TOKEN_NO_REPLACE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN_NO_REPLACE    (BIT(0))
-#define SLC_SLC0_TOKEN_NO_REPLACE_M  (BIT(0))
-#define SLC_SLC0_TOKEN_NO_REPLACE_V  0x1
-#define SLC_SLC0_TOKEN_NO_REPLACE_S  0
-
-#define SLC_TXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0x9C)
-/* SLC_SLC0_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TXLINK_DSCR    0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_M  ((SLC_SLC0_TXLINK_DSCR_V)<<(SLC_SLC0_TXLINK_DSCR_S))
-#define SLC_SLC0_TXLINK_DSCR_V  0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_S  0
-
-#define SLC_TXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xA0)
-/* SLC_SLC0_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TXLINK_DSCR_BF0    0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF0_M  ((SLC_SLC0_TXLINK_DSCR_BF0_V)<<(SLC_SLC0_TXLINK_DSCR_BF0_S))
-#define SLC_SLC0_TXLINK_DSCR_BF0_V  0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF0_S  0
-
-#define SLC_TXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xA4)
-/* SLC_SLC0_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TXLINK_DSCR_BF1    0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF1_M  ((SLC_SLC0_TXLINK_DSCR_BF1_V)<<(SLC_SLC0_TXLINK_DSCR_BF1_S))
-#define SLC_SLC0_TXLINK_DSCR_BF1_V  0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF1_S  0
-
-#define SLC_RXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0xA8)
-/* SLC_SLC0_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RXLINK_DSCR    0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_M  ((SLC_SLC0_RXLINK_DSCR_V)<<(SLC_SLC0_RXLINK_DSCR_S))
-#define SLC_SLC0_RXLINK_DSCR_V  0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_S  0
-
-#define SLC_RXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xAC)
-/* SLC_SLC0_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RXLINK_DSCR_BF0    0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF0_M  ((SLC_SLC0_RXLINK_DSCR_BF0_V)<<(SLC_SLC0_RXLINK_DSCR_BF0_S))
-#define SLC_SLC0_RXLINK_DSCR_BF0_V  0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF0_S  0
-
-#define SLC_RXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xB0)
-/* SLC_SLC0_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RXLINK_DSCR_BF1    0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF1_M  ((SLC_SLC0_RXLINK_DSCR_BF1_V)<<(SLC_SLC0_RXLINK_DSCR_BF1_S))
-#define SLC_SLC0_RXLINK_DSCR_BF1_V  0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF1_S  0
-
-#define SLC_TX_ERREOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0xCC)
-/* SLC_SLC0_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR    0xFFFFFFFF
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_M  ((SLC_SLC0_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_ERR_EOF_DES_ADDR_S))
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_S  0
-
-#define SLC_TOKEN_LAT_REG          (DR_REG_SLC_BASE + 0xD4)
-/* SLC_SLC0_TOKEN : RO ;bitpos:[11:0] ;default: 12'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN    0x00000FFF
-#define SLC_SLC0_TOKEN_M  ((SLC_SLC0_TOKEN_V)<<(SLC_SLC0_TOKEN_S))
-#define SLC_SLC0_TOKEN_V  0xFFF
-#define SLC_SLC0_TOKEN_S  0
-
-#define SLC_TX_DSCR_CONF_REG          (DR_REG_SLC_BASE + 0xD8)
-/* SLC_WR_RETRY_THRESHOLD : R/W ;bitpos:[10:0] ;default: 11'h80 ; */
-/*description: .*/
-#define SLC_WR_RETRY_THRESHOLD    0x000007FF
-#define SLC_WR_RETRY_THRESHOLD_M  ((SLC_WR_RETRY_THRESHOLD_V)<<(SLC_WR_RETRY_THRESHOLD_S))
-#define SLC_WR_RETRY_THRESHOLD_V  0x7FF
-#define SLC_WR_RETRY_THRESHOLD_S  0
-
-#define SLC_CMD_INFOR0_REG          (DR_REG_SLC_BASE + 0xDC)
-/* SLC_CMD_CONTENT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_CMD_CONTENT0    0xFFFFFFFF
-#define SLC_CMD_CONTENT0_M  ((SLC_CMD_CONTENT0_V)<<(SLC_CMD_CONTENT0_S))
-#define SLC_CMD_CONTENT0_V  0xFFFFFFFF
-#define SLC_CMD_CONTENT0_S  0
-
-#define SLC_CMD_INFOR1_REG          (DR_REG_SLC_BASE + 0xE0)
-/* SLC_CMD_CONTENT1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_CMD_CONTENT1    0xFFFFFFFF
-#define SLC_CMD_CONTENT1_M  ((SLC_CMD_CONTENT1_V)<<(SLC_CMD_CONTENT1_S))
-#define SLC_CMD_CONTENT1_V  0xFFFFFFFF
-#define SLC_CMD_CONTENT1_S  0
-
-#define SLC_LEN_CONF_REG          (DR_REG_SLC_BASE + 0xE4)
-/* SLC_SLC0_TX_NEW_PKT_IND : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_NEW_PKT_IND    (BIT(28))
-#define SLC_SLC0_TX_NEW_PKT_IND_M  (BIT(28))
-#define SLC_SLC0_TX_NEW_PKT_IND_V  0x1
-#define SLC_SLC0_TX_NEW_PKT_IND_S  28
-/* SLC_SLC0_RX_NEW_PKT_IND : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_NEW_PKT_IND    (BIT(27))
-#define SLC_SLC0_RX_NEW_PKT_IND_M  (BIT(27))
-#define SLC_SLC0_RX_NEW_PKT_IND_V  0x1
-#define SLC_SLC0_RX_NEW_PKT_IND_S  27
-/* SLC_SLC0_TX_GET_USED_DSCR : WO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_GET_USED_DSCR    (BIT(26))
-#define SLC_SLC0_TX_GET_USED_DSCR_M  (BIT(26))
-#define SLC_SLC0_TX_GET_USED_DSCR_V  0x1
-#define SLC_SLC0_TX_GET_USED_DSCR_S  26
-/* SLC_SLC0_RX_GET_USED_DSCR : WO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_GET_USED_DSCR    (BIT(25))
-#define SLC_SLC0_RX_GET_USED_DSCR_M  (BIT(25))
-#define SLC_SLC0_RX_GET_USED_DSCR_V  0x1
-#define SLC_SLC0_RX_GET_USED_DSCR_S  25
-/* SLC_SLC0_TX_PACKET_LOAD_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_PACKET_LOAD_EN    (BIT(24))
-#define SLC_SLC0_TX_PACKET_LOAD_EN_M  (BIT(24))
-#define SLC_SLC0_TX_PACKET_LOAD_EN_V  0x1
-#define SLC_SLC0_TX_PACKET_LOAD_EN_S  24
-/* SLC_SLC0_RX_PACKET_LOAD_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_PACKET_LOAD_EN    (BIT(23))
-#define SLC_SLC0_RX_PACKET_LOAD_EN_M  (BIT(23))
-#define SLC_SLC0_RX_PACKET_LOAD_EN_V  0x1
-#define SLC_SLC0_RX_PACKET_LOAD_EN_S  23
-/* SLC_SLC0_LEN_INC_MORE : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_LEN_INC_MORE    (BIT(22))
-#define SLC_SLC0_LEN_INC_MORE_M  (BIT(22))
-#define SLC_SLC0_LEN_INC_MORE_V  0x1
-#define SLC_SLC0_LEN_INC_MORE_S  22
-/* SLC_SLC0_LEN_INC : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_LEN_INC    (BIT(21))
-#define SLC_SLC0_LEN_INC_M  (BIT(21))
-#define SLC_SLC0_LEN_INC_V  0x1
-#define SLC_SLC0_LEN_INC_S  21
-/* SLC_SLC0_LEN_WR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_LEN_WR    (BIT(20))
-#define SLC_SLC0_LEN_WR_M  (BIT(20))
-#define SLC_SLC0_LEN_WR_V  0x1
-#define SLC_SLC0_LEN_WR_S  20
-/* SLC_SLC0_LEN_WDATA : WO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: .*/
-#define SLC_SLC0_LEN_WDATA    0x000FFFFF
-#define SLC_SLC0_LEN_WDATA_M  ((SLC_SLC0_LEN_WDATA_V)<<(SLC_SLC0_LEN_WDATA_S))
-#define SLC_SLC0_LEN_WDATA_V  0xFFFFF
-#define SLC_SLC0_LEN_WDATA_S  0
-
-#define SLC_LENGTH_REG          (DR_REG_SLC_BASE + 0xE8)
-/* SLC_SLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: .*/
-#define SLC_SLC0_LEN    0x000FFFFF
-#define SLC_SLC0_LEN_M  ((SLC_SLC0_LEN_V)<<(SLC_SLC0_LEN_S))
-#define SLC_SLC0_LEN_V  0xFFFFF
-#define SLC_SLC0_LEN_S  0
-
-#define SLC_TXPKT_H_DSCR_REG          (DR_REG_SLC_BASE + 0xEC)
-/* SLC_SLC0_TX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR    0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_H_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_S  0
-
-#define SLC_TXPKT_E_DSCR_REG          (DR_REG_SLC_BASE + 0xF0)
-/* SLC_SLC0_TX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR    0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_E_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_S  0
-
-#define SLC_RXPKT_H_DSCR_REG          (DR_REG_SLC_BASE + 0xF4)
-/* SLC_SLC0_RX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR    0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_H_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_S  0
-
-#define SLC_RXPKT_E_DSCR_REG          (DR_REG_SLC_BASE + 0xF8)
-/* SLC_SLC0_RX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR    0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_E_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_S  0
-
-#define SLC_TXPKTU_H_DSCR_REG          (DR_REG_SLC_BASE + 0xFC)
-/* SLC_SLC0_TX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR    0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_START_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_S  0
-
-#define SLC_TXPKTU_E_DSCR_REG          (DR_REG_SLC_BASE + 0x100)
-/* SLC_SLC0_TX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR    0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_END_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_S  0
-
-#define SLC_RXPKTU_H_DSCR_REG          (DR_REG_SLC_BASE + 0x104)
-/* SLC_SLC0_RX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR    0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_START_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_S  0
-
-#define SLC_RXPKTU_E_DSCR_REG          (DR_REG_SLC_BASE + 0x108)
-/* SLC_SLC0_RX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR    0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_END_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_S  0
-
-#define SLC_SEQ_POSITION_REG          (DR_REG_SLC_BASE + 0x114)
-/* SLC_SLC0_SEQ_POSITION : R/W ;bitpos:[7:0] ;default: 8'h9 ; */
-/*description: .*/
-#define SLC_SLC0_SEQ_POSITION    0x000000FF
-#define SLC_SLC0_SEQ_POSITION_M  ((SLC_SLC0_SEQ_POSITION_V)<<(SLC_SLC0_SEQ_POSITION_S))
-#define SLC_SLC0_SEQ_POSITION_V  0xFF
-#define SLC_SLC0_SEQ_POSITION_S  0
-
-#define SLC_DSCR_REC_CONF_REG          (DR_REG_SLC_BASE + 0x118)
-/* SLC_SLC0_RX_DSCR_REC_LIM : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */
-/*description: .*/
-#define SLC_SLC0_RX_DSCR_REC_LIM    0x000003FF
-#define SLC_SLC0_RX_DSCR_REC_LIM_M  ((SLC_SLC0_RX_DSCR_REC_LIM_V)<<(SLC_SLC0_RX_DSCR_REC_LIM_S))
-#define SLC_SLC0_RX_DSCR_REC_LIM_V  0x3FF
-#define SLC_SLC0_RX_DSCR_REC_LIM_S  0
-
-#define SLC_SDIO_CRC_ST0_REG          (DR_REG_SLC_BASE + 0x11C)
-/* SLC_DAT3_CRC_ERR_CNT : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: .*/
-#define SLC_DAT3_CRC_ERR_CNT    0x000000FF
-#define SLC_DAT3_CRC_ERR_CNT_M  ((SLC_DAT3_CRC_ERR_CNT_V)<<(SLC_DAT3_CRC_ERR_CNT_S))
-#define SLC_DAT3_CRC_ERR_CNT_V  0xFF
-#define SLC_DAT3_CRC_ERR_CNT_S  24
-/* SLC_DAT2_CRC_ERR_CNT : RO ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: .*/
-#define SLC_DAT2_CRC_ERR_CNT    0x000000FF
-#define SLC_DAT2_CRC_ERR_CNT_M  ((SLC_DAT2_CRC_ERR_CNT_V)<<(SLC_DAT2_CRC_ERR_CNT_S))
-#define SLC_DAT2_CRC_ERR_CNT_V  0xFF
-#define SLC_DAT2_CRC_ERR_CNT_S  16
-/* SLC_DAT1_CRC_ERR_CNT : RO ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: .*/
-#define SLC_DAT1_CRC_ERR_CNT    0x000000FF
-#define SLC_DAT1_CRC_ERR_CNT_M  ((SLC_DAT1_CRC_ERR_CNT_V)<<(SLC_DAT1_CRC_ERR_CNT_S))
-#define SLC_DAT1_CRC_ERR_CNT_V  0xFF
-#define SLC_DAT1_CRC_ERR_CNT_S  8
-/* SLC_DAT0_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define SLC_DAT0_CRC_ERR_CNT    0x000000FF
-#define SLC_DAT0_CRC_ERR_CNT_M  ((SLC_DAT0_CRC_ERR_CNT_V)<<(SLC_DAT0_CRC_ERR_CNT_S))
-#define SLC_DAT0_CRC_ERR_CNT_V  0xFF
-#define SLC_DAT0_CRC_ERR_CNT_S  0
-
-#define SLC_SDIO_CRC_ST1_REG          (DR_REG_SLC_BASE + 0x120)
-/* SLC_ERR_CNT_CLR : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_ERR_CNT_CLR    (BIT(31))
-#define SLC_ERR_CNT_CLR_M  (BIT(31))
-#define SLC_ERR_CNT_CLR_V  0x1
-#define SLC_ERR_CNT_CLR_S  31
-/* SLC_CMD_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define SLC_CMD_CRC_ERR_CNT    0x000000FF
-#define SLC_CMD_CRC_ERR_CNT_M  ((SLC_CMD_CRC_ERR_CNT_V)<<(SLC_CMD_CRC_ERR_CNT_S))
-#define SLC_CMD_CRC_ERR_CNT_V  0xFF
-#define SLC_CMD_CRC_ERR_CNT_S  0
-
-#define SLC_EOF_START_DES_REG          (DR_REG_SLC_BASE + 0x124)
-/* SLC_SLC0_EOF_START_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_SLC0_EOF_START_DES_ADDR    0xFFFFFFFF
-#define SLC_SLC0_EOF_START_DES_ADDR_M  ((SLC_SLC0_EOF_START_DES_ADDR_V)<<(SLC_SLC0_EOF_START_DES_ADDR_S))
-#define SLC_SLC0_EOF_START_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_EOF_START_DES_ADDR_S  0
-
-#define SLC_PUSH_DSCR_ADDR_REG          (DR_REG_SLC_BASE + 0x128)
-/* SLC_SLC0_RX_PUSH_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR    0xFFFFFFFF
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR_M  ((SLC_SLC0_RX_PUSH_DSCR_ADDR_V)<<(SLC_SLC0_RX_PUSH_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR_S  0
-
-#define SLC_DONE_DSCR_ADDR_REG          (DR_REG_SLC_BASE + 0x12C)
-/* SLC_SLC0_RX_DONE_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DONE_DSCR_ADDR    0xFFFFFFFF
-#define SLC_SLC0_RX_DONE_DSCR_ADDR_M  ((SLC_SLC0_RX_DONE_DSCR_ADDR_V)<<(SLC_SLC0_RX_DONE_DSCR_ADDR_S))
-#define SLC_SLC0_RX_DONE_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_DONE_DSCR_ADDR_S  0
-
-#define SLC_SUB_START_DES_REG          (DR_REG_SLC_BASE + 0x130)
-/* SLC_SLC0_SUB_PAC_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR    0xFFFFFFFF
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_M  ((SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V)<<(SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S))
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S  0
-
-#define SLC_DSCR_CNT_REG          (DR_REG_SLC_BASE + 0x134)
-/* SLC_SLC0_RX_GET_EOF_OCC : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_GET_EOF_OCC    (BIT(16))
-#define SLC_SLC0_RX_GET_EOF_OCC_M  (BIT(16))
-#define SLC_SLC0_RX_GET_EOF_OCC_V  0x1
-#define SLC_SLC0_RX_GET_EOF_OCC_S  16
-/* SLC_SLC0_RX_DSCR_CNT_LAT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DSCR_CNT_LAT    0x000003FF
-#define SLC_SLC0_RX_DSCR_CNT_LAT_M  ((SLC_SLC0_RX_DSCR_CNT_LAT_V)<<(SLC_SLC0_RX_DSCR_CNT_LAT_S))
-#define SLC_SLC0_RX_DSCR_CNT_LAT_V  0x3FF
-#define SLC_SLC0_RX_DSCR_CNT_LAT_S  0
-
-#define SLC_LEN_LIM_CONF_REG          (DR_REG_SLC_BASE + 0x138)
-/* SLC_SLC0_LEN_LIM : R/W ;bitpos:[19:0] ;default: 20'h5400 ; */
-/*description: .*/
-#define SLC_SLC0_LEN_LIM    0x000FFFFF
-#define SLC_SLC0_LEN_LIM_M  ((SLC_SLC0_LEN_LIM_V)<<(SLC_SLC0_LEN_LIM_S))
-#define SLC_SLC0_LEN_LIM_V  0xFFFFF
-#define SLC_SLC0_LEN_LIM_S  0
-
-#define SLC_INT_ST1_REG          (DR_REG_SLC_BASE + 0x13C)
-/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1    (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_M  (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_V  0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_S  27
-/* SLC_SLC0_RX_QUICK_EOF_INT_ST1 : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1    (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_S  26
-/* SLC_CMD_DTC_INT_ST1 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_CMD_DTC_INT_ST1    (BIT(25))
-#define SLC_CMD_DTC_INT_ST1_M  (BIT(25))
-#define SLC_CMD_DTC_INT_ST1_V  0x1
-#define SLC_CMD_DTC_INT_ST1_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1    (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1    (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1    (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1    (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1    (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1    (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_S  19
-/* SLC_SLC0_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOHOST_INT_ST1    (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST1_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST1_V  0x1
-#define SLC_SLC0_TOHOST_INT_ST1_S  18
-/* SLC_SLC0_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_EOF_INT_ST1    (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST1_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST1_V  0x1
-#define SLC_SLC0_RX_EOF_INT_ST1_S  17
-/* SLC_SLC0_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DONE_INT_ST1    (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST1_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST1_V  0x1
-#define SLC_SLC0_RX_DONE_INT_ST1_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1    (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1_S  15
-/* SLC_SLC0_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DONE_INT_ST1    (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST1_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST1_V  0x1
-#define SLC_SLC0_TX_DONE_INT_ST1_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1    (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1    (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_S  12
-/* SLC_SLC0_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_OVF_INT_ST1    (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST1_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST1_V  0x1
-#define SLC_SLC0_TX_OVF_INT_ST1_S  11
-/* SLC_SLC0_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_UDF_INT_ST1    (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST1_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST1_V  0x1
-#define SLC_SLC0_RX_UDF_INT_ST1_S  10
-/* SLC_SLC0_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_START_INT_ST1    (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST1_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST1_V  0x1
-#define SLC_SLC0_TX_START_INT_ST1_S  9
-/* SLC_SLC0_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_START_INT_ST1    (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST1_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST1_V  0x1
-#define SLC_SLC0_RX_START_INT_ST1_S  8
-/* SLC_FRHOST_BIT7_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT7_INT_ST1    (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST1_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT7_INT_ST1_S  7
-/* SLC_FRHOST_BIT6_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT6_INT_ST1    (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST1_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT6_INT_ST1_S  6
-/* SLC_FRHOST_BIT5_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT5_INT_ST1    (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST1_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT5_INT_ST1_S  5
-/* SLC_FRHOST_BIT4_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT4_INT_ST1    (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST1_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT4_INT_ST1_S  4
-/* SLC_FRHOST_BIT3_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT3_INT_ST1    (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST1_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT3_INT_ST1_S  3
-/* SLC_FRHOST_BIT2_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT2_INT_ST1    (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST1_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT2_INT_ST1_S  2
-/* SLC_FRHOST_BIT1_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT1_INT_ST1    (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST1_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT1_INT_ST1_S  1
-/* SLC_FRHOST_BIT0_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT0_INT_ST1    (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST1_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT0_INT_ST1_S  0
-
-#define SLC_INT_ENA1_REG          (DR_REG_SLC_BASE + 0x140)
-/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1    (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M  (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V  0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S  27
-/* SLC_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1    (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_S  26
-/* SLC_CMD_DTC_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_CMD_DTC_INT_ENA1    (BIT(25))
-#define SLC_CMD_DTC_INT_ENA1_M  (BIT(25))
-#define SLC_CMD_DTC_INT_ENA1_V  0x1
-#define SLC_CMD_DTC_INT_ENA1_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1    (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1    (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1    (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1    (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1    (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1    (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_S  19
-/* SLC_SLC0_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOHOST_INT_ENA1    (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA1_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA1_V  0x1
-#define SLC_SLC0_TOHOST_INT_ENA1_S  18
-/* SLC_SLC0_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_EOF_INT_ENA1    (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA1_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_EOF_INT_ENA1_S  17
-/* SLC_SLC0_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_DONE_INT_ENA1    (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA1_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_DONE_INT_ENA1_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1    (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_S  15
-/* SLC_SLC0_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_DONE_INT_ENA1    (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA1_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_DONE_INT_ENA1_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1    (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1    (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_S  12
-/* SLC_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_OVF_INT_ENA1    (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA1_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_OVF_INT_ENA1_S  11
-/* SLC_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_UDF_INT_ENA1    (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA1_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_UDF_INT_ENA1_S  10
-/* SLC_SLC0_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_TX_START_INT_ENA1    (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA1_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_START_INT_ENA1_S  9
-/* SLC_SLC0_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_SLC0_RX_START_INT_ENA1    (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA1_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_START_INT_ENA1_S  8
-/* SLC_FRHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT7_INT_ENA1    (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA1_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT7_INT_ENA1_S  7
-/* SLC_FRHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT6_INT_ENA1    (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA1_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT6_INT_ENA1_S  6
-/* SLC_FRHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT5_INT_ENA1    (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA1_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT5_INT_ENA1_S  5
-/* SLC_FRHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT4_INT_ENA1    (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA1_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT4_INT_ENA1_S  4
-/* SLC_FRHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT3_INT_ENA1    (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA1_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT3_INT_ENA1_S  3
-/* SLC_FRHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT2_INT_ENA1    (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA1_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT2_INT_ENA1_S  2
-/* SLC_FRHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT1_INT_ENA1    (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA1_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT1_INT_ENA1_S  1
-/* SLC_FRHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SLC_FRHOST_BIT0_INT_ENA1    (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA1_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT0_INT_ENA1_S  0
-
-#define SLC_SLCDATE_REG          (DR_REG_SLC_BASE + 0x1F8)
-/* SLC_DATE : R/W ;bitpos:[31:0] ;default: 32'h18080700 ; */
-/*description: .*/
-#define SLC_DATE    0xFFFFFFFF
-#define SLC_DATE_M  ((SLC_DATE_V)<<(SLC_DATE_S))
-#define SLC_DATE_V  0xFFFFFFFF
-#define SLC_DATE_S  0
-
-#define SLC_SLCID_REG          (DR_REG_SLC_BASE + 0x1FC)
-/* SLC_ID : R/W ;bitpos:[31:0] ;default: 32'h0100 ; */
-/*description: .*/
-#define SLC_ID    0xFFFFFFFF
-#define SLC_ID_M  ((SLC_ID_V)<<(SLC_ID_S))
-#define SLC_ID_V  0xFFFFFFFF
-#define SLC_ID_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SLC_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/slc_struct.h b/components/soc/esp32s3/include/soc/slc_struct.h
deleted file mode 100644
index 896e781e7d..0000000000
--- a/components/soc/esp32s3/include/soc/slc_struct.h
+++ /dev/null
@@ -1,592 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SLC_STRUCT_H_
-#define _SOC_SLC_STRUCT_H_
-
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t tx_rst                        :    1;
-            uint32_t rx_rst                        :    1;
-            uint32_t ahbm_fifo_rst                 :    1;
-            uint32_t ahbm_rst                      :    1;
-            uint32_t tx_loop_test                  :    1;
-            uint32_t rx_loop_test                  :    1;
-            uint32_t rx_auto_wrback                :    1;
-            uint32_t rx_no_restart_clr             :    1;
-            uint32_t rxdscr_burst_en               :    1;
-            uint32_t rxdata_burst_en               :    1;
-            uint32_t auto_ret                      :    1;
-            uint32_t txdscr_burst_en               :    1;
-            uint32_t txdata_burst_en               :    1;
-            uint32_t token_auto_clr                :    1;
-            uint32_t token_sel                     :    1;
-            uint32_t reserved16                    :    2;
-            uint32_t wr_retry_mask_en              :    1;
-            uint32_t reserved19                    :    13;
-        };
-        uint32_t val;
-    } slcconf0;
-    union {
-        struct {
-            uint32_t frhost_bit0                   :    1;
-            uint32_t frhost_bit1                   :    1;
-            uint32_t frhost_bit2                   :    1;
-            uint32_t frhost_bit3                   :    1;
-            uint32_t frhost_bit4                   :    1;
-            uint32_t frhost_bit5                   :    1;
-            uint32_t frhost_bit6                   :    1;
-            uint32_t frhost_bit7                   :    1;
-            uint32_t rx_start                      :    1;
-            uint32_t tx_start                      :    1;
-            uint32_t rx_udf                        :    1;
-            uint32_t tx_ovf                        :    1;
-            uint32_t token0_1to0                   :    1;
-            uint32_t token1_1to0                   :    1;
-            uint32_t tx_done                       :    1;
-            uint32_t tx_suc_eof                    :    1;
-            uint32_t rx_done                       :    1;
-            uint32_t rx_eof                        :    1;
-            uint32_t tohost                        :    1;
-            uint32_t tx_dscr_err                   :    1;
-            uint32_t rx_dscr_err                   :    1;
-            uint32_t tx_dscr_empty                 :    1;
-            uint32_t host_rd_ack                   :    1;
-            uint32_t wr_retry_done                 :    1;
-            uint32_t tx_err_eof                    :    1;
-            uint32_t cmd_dtc                       :    1;
-            uint32_t rx_quick_eof                  :    1;
-            uint32_t host_pop_eof_err              :    1;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } slc0_int_raw;
-    union {
-        struct {
-            uint32_t frhost_bit0                   :    1;
-            uint32_t frhost_bit1                   :    1;
-            uint32_t frhost_bit2                   :    1;
-            uint32_t frhost_bit3                   :    1;
-            uint32_t frhost_bit4                   :    1;
-            uint32_t frhost_bit5                   :    1;
-            uint32_t frhost_bit6                   :    1;
-            uint32_t frhost_bit7                   :    1;
-            uint32_t rx_start                      :    1;
-            uint32_t tx_start                      :    1;
-            uint32_t rx_udf                        :    1;
-            uint32_t tx_ovf                        :    1;
-            uint32_t token0_1to0                   :    1;
-            uint32_t token1_1to0                   :    1;
-            uint32_t tx_done                       :    1;
-            uint32_t tx_suc_eof                    :    1;
-            uint32_t rx_done                       :    1;
-            uint32_t rx_eof                        :    1;
-            uint32_t tohost                        :    1;
-            uint32_t tx_dscr_err                   :    1;
-            uint32_t rx_dscr_err                   :    1;
-            uint32_t tx_dscr_empty                 :    1;
-            uint32_t host_rd_ack                   :    1;
-            uint32_t wr_retry_done                 :    1;
-            uint32_t tx_err_eof                    :    1;
-            uint32_t cmd_dtc                       :    1;
-            uint32_t rx_quick_eof                  :    1;
-            uint32_t host_pop_eof_err              :    1;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } slc0_int_st;
-    union {
-        struct {
-            uint32_t frhost_bit0                   :    1;
-            uint32_t frhost_bit1                   :    1;
-            uint32_t frhost_bit2                   :    1;
-            uint32_t frhost_bit3                   :    1;
-            uint32_t frhost_bit4                   :    1;
-            uint32_t frhost_bit5                   :    1;
-            uint32_t frhost_bit6                   :    1;
-            uint32_t frhost_bit7                   :    1;
-            uint32_t rx_start                      :    1;
-            uint32_t tx_start                      :    1;
-            uint32_t rx_udf                        :    1;
-            uint32_t tx_ovf                        :    1;
-            uint32_t token0_1to0                   :    1;
-            uint32_t token1_1to0                   :    1;
-            uint32_t tx_done                       :    1;
-            uint32_t tx_suc_eof                    :    1;
-            uint32_t rx_done                       :    1;
-            uint32_t rx_eof                        :    1;
-            uint32_t tohost                        :    1;
-            uint32_t tx_dscr_err                   :    1;
-            uint32_t rx_dscr_err                   :    1;
-            uint32_t tx_dscr_empty                 :    1;
-            uint32_t host_rd_ack                   :    1;
-            uint32_t wr_retry_done                 :    1;
-            uint32_t tx_err_eof                    :    1;
-            uint32_t cmd_dtc                       :    1;
-            uint32_t rx_quick_eof                  :    1;
-            uint32_t host_pop_eof_err              :    1;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } slc0_int_ena;
-    union {
-        struct {
-            uint32_t frhost_bit0                   :    1;
-            uint32_t frhost_bit1                   :    1;
-            uint32_t frhost_bit2                   :    1;
-            uint32_t frhost_bit3                   :    1;
-            uint32_t frhost_bit4                   :    1;
-            uint32_t frhost_bit5                   :    1;
-            uint32_t frhost_bit6                   :    1;
-            uint32_t frhost_bit7                   :    1;
-            uint32_t rx_start                      :    1;
-            uint32_t tx_start                      :    1;
-            uint32_t rx_udf                        :    1;
-            uint32_t tx_ovf                        :    1;
-            uint32_t token0_1to0                   :    1;
-            uint32_t token1_1to0                   :    1;
-            uint32_t tx_done                       :    1;
-            uint32_t tx_suc_eof                    :    1;
-            uint32_t rx_done                       :    1;
-            uint32_t rx_eof                        :    1;
-            uint32_t tohost                        :    1;
-            uint32_t tx_dscr_err                   :    1;
-            uint32_t rx_dscr_err                   :    1;
-            uint32_t tx_dscr_empty                 :    1;
-            uint32_t host_rd_ack                   :    1;
-            uint32_t wr_retry_done                 :    1;
-            uint32_t tx_err_eof                    :    1;
-            uint32_t cmd_dtc                       :    1;
-            uint32_t rx_quick_eof                  :    1;
-            uint32_t host_pop_eof_err              :    1;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } slc0_int_clr;
-    uint32_t reserved_14;
-    uint32_t reserved_18;
-    uint32_t reserved_1c;
-    uint32_t reserved_20;
-    union {
-        struct {
-            uint32_t rx_full                       :    1;
-            uint32_t rx_empty                      :    1;
-            uint32_t rx_buf_len                    :    12;
-            uint32_t reserved14                    :    18;
-        };
-        uint32_t val;
-    } rx_status;
-    union {
-        struct {
-            uint32_t rxfifo_wdata                  :    9;
-            uint32_t reserved9                     :    7;
-            uint32_t rxfifo_push                   :    1;
-            uint32_t reserved17                    :    15;
-        };
-        uint32_t val;
-    } slc0_rxfifo_push;
-    uint32_t reserved_2c;
-    union {
-        struct {
-            uint32_t tx_full                       :    1;
-            uint32_t tx_empty                      :    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } tx_status;
-    union {
-        struct {
-            uint32_t txfifo_rdata                  :    11;
-            uint32_t reserved11                    :    5;
-            uint32_t txfifo_pop                    :    1;
-            uint32_t reserved17                    :    15;
-        };
-        uint32_t val;
-    } slc0_txfifo_pop;
-    uint32_t reserved_38;
-    union {
-        struct {
-            uint32_t addr                          :    20;
-            uint32_t reserved20                    :    8;
-            uint32_t stop                          :    1;
-            uint32_t start                         :    1;
-            uint32_t restart                       :    1;
-            uint32_t park                          :    1;
-        };
-        uint32_t val;
-    } slc0_rx_link;
-    union {
-        struct {
-            uint32_t addr                          :    20;
-            uint32_t reserved20                    :    8;
-            uint32_t stop                          :    1;
-            uint32_t start                         :    1;
-            uint32_t restart                       :    1;
-            uint32_t park                          :    1;
-        };
-        uint32_t val;
-    } slc0_tx_link;
-    uint32_t reserved_44;
-    uint32_t reserved_48;
-    union {
-        struct {
-            uint32_t tohost_intvec                 :    8;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } slcintvec_tohost;
-    union {
-        struct {
-            uint32_t wdata                         :    12;
-            uint32_t wr                            :    1;
-            uint32_t inc                           :    1;
-            uint32_t inc_more                      :    1;
-            uint32_t reserved15                    :    1;
-            uint32_t token0                        :    12;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } slc0token0;
-    union {
-        struct {
-            uint32_t wdata                         :    12;
-            uint32_t wr                            :    1;
-            uint32_t inc                           :    1;
-            uint32_t inc_more                      :    1;
-            uint32_t reserved15                    :    1;
-            uint32_t token1                        :    12;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } slc0_token1;
-    uint32_t reserved_58;
-    uint32_t reserved_5c;
-    union {
-        struct {
-            uint32_t check_owner                   :    1;
-            uint32_t tx_check_sum_en               :    1;
-            uint32_t rx_check_sum_en               :    1;
-            uint32_t reg_cmd_hold_en               :    1;
-            uint32_t len_auto_clr                  :    1;
-            uint32_t tx_stitch_en                  :    1;
-            uint32_t rx_stitch_en                  :    1;
-            uint32_t reserved7                     :    12;
-            uint32_t host_int_level_sel            :    1;
-            uint32_t reserved20                    :    2;
-            uint32_t reg_clk_en                    :    1;
-            uint32_t reserved23                    :    9;
-        };
-        uint32_t val;
-    } slcconf1;
-    uint32_t slc0_state0;
-    uint32_t slc0_state1;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    union {
-        struct {
-            uint32_t txeof_ena                     :    6;
-            uint32_t reserved6                     :    2;
-            uint32_t fifo_map_ena                  :    4;
-            uint32_t tx_dummy_mode                 :    1;
-            uint32_t hda_map_128k                  :    1;
-            uint32_t reserved14                    :    2;
-            uint32_t tx_push_idle_num              :    16;
-        };
-        uint32_t val;
-    } slcbridge_conf;
-    uint32_t slc0_to_eof_des_addr;
-    uint32_t slc0_tx_eof_des_addr;
-    uint32_t slc0_to_eof_bfr_des_addr;
-    uint32_t reserved_84;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    union {
-        struct {
-            uint32_t mode                          :    3;
-            uint32_t reserved3                     :    1;
-            uint32_t addr                          :    2;
-            uint32_t reserved6                     :    26;
-        };
-        uint32_t val;
-    } ahb_test;
-    union {
-        struct {
-            uint32_t cmd_st                        :    3;
-            uint32_t reserved3                     :    1;
-            uint32_t func_st                       :    4;
-            uint32_t sdio_wakeup                   :    1;
-            uint32_t reserved9                     :    3;
-            uint32_t bus_st                        :    3;
-            uint32_t reserved15                    :    1;
-            uint32_t func1_acc_state               :    5;
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } sdio_st;
-    union {
-        struct {
-            uint32_t token_no_replace              :    1;
-            uint32_t infor_no_replace              :    1;
-            uint32_t rx_fill_mode                  :    1;
-            uint32_t rx_eof_mode                   :    1;
-            uint32_t rx_fill_en                    :    1;
-            uint32_t rd_retry_threshold            :    11;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } rx_dscr_conf;
-    uint32_t slc0_txlink_dscr;
-    uint32_t slc0_txlink_dscr_bf0;
-    uint32_t slc0_txlink_dscr_bf1;
-    uint32_t slc0_rxlink_dscr;
-    uint32_t slc0_rxlink_dscr_bf0;
-    uint32_t slc0_rxlink_dscr_bf1;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t slc0_tx_erreof_des_addr;
-    uint32_t reserved_d0;
-    union {
-        struct {
-            uint32_t token                         :    12;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } token_lat;
-    union {
-        struct {
-            uint32_t wr_retry_threshold            :    11;
-            uint32_t reserved11                    :    21;
-        };
-        uint32_t val;
-    } tx_dscr_conf;
-    uint32_t cmd_infor0;
-    uint32_t cmd_infor1;
-    union {
-        struct {
-            uint32_t len_wdata                     :    20;
-            uint32_t len_wr                        :    1;
-            uint32_t len_inc                       :    1;
-            uint32_t len_inc_more                  :    1;
-            uint32_t rx_packet_load_en             :    1;
-            uint32_t tx_packet_load_en             :    1;
-            uint32_t rx_get_used_dscr              :    1;
-            uint32_t tx_get_used_dscr              :    1;
-            uint32_t rx_new_pkt_ind                :    1;
-            uint32_t tx_new_pkt_ind                :    1;
-            uint32_t reserved29                    :    3;
-        };
-        uint32_t val;
-    } slc0_len_conf;
-    union {
-        struct {
-            uint32_t len                           :    20;
-            uint32_t reserved20                    :    12;
-        };
-        uint32_t val;
-    } slc0_length;
-    uint32_t slc0_txpkt_h_dscr;
-    uint32_t slc0_txpkt_e_dscr;
-    uint32_t slc0_rxpkt_h_dscr;
-    uint32_t slc0_rxpkt_e_dscr;
-    uint32_t slc0_txpktu_h_dscr;
-    uint32_t slc0_txpktu_e_dscr;
-    uint32_t slc0_rxpktu_h_dscr;
-    uint32_t slc0_rxpktu_e_dscr;
-    uint32_t reserved_10c;
-    uint32_t reserved_110;
-    union {
-        struct {
-            uint32_t seq_position                  :    8;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } seq_position;
-    union {
-        struct {
-            uint32_t rx_dscr_rec_lim               :    10;
-            uint32_t reserved10                    :    22;
-        };
-        uint32_t val;
-    } slc0_dscr_rec_conf;
-    union {
-        struct {
-            uint32_t dat0_crc_err_cnt              :    8;
-            uint32_t dat1_crc_err_cnt              :    8;
-            uint32_t dat2_crc_err_cnt              :    8;
-            uint32_t dat3_crc_err_cnt              :    8;
-        };
-        uint32_t val;
-    } sdio_crc_st0;
-    union {
-        struct {
-            uint32_t cmd_crc_err_cnt               :    8;
-            uint32_t reserved8                     :    23;
-            uint32_t err_cnt_clr                   :    1;
-        };
-        uint32_t val;
-    } sdio_crc_st1;
-    uint32_t slc0_eof_start_des;
-    uint32_t slc0_push_dscr_addr;
-    uint32_t slc0_done_dscr_addr;
-    uint32_t slc0_sub_start_des;
-    union {
-        struct {
-            uint32_t rx_dscr_cnt_lat               :    10;
-            uint32_t reserved10                    :    6;
-            uint32_t rx_get_eof_occ                :    1;
-            uint32_t reserved17                    :    15;
-        };
-        uint32_t val;
-    } slc0_dscr_cnt;
-    union {
-        struct {
-            uint32_t len_lim                       :    20;
-            uint32_t reserved20                    :    12;
-        };
-        uint32_t val;
-    } slc0_len_lim_conf;
-    union {
-        struct {
-            uint32_t frhost_bit01                  :    1;
-            uint32_t frhost_bit11                  :    1;
-            uint32_t frhost_bit21                  :    1;
-            uint32_t frhost_bit31                  :    1;
-            uint32_t frhost_bit41                  :    1;
-            uint32_t frhost_bit51                  :    1;
-            uint32_t frhost_bit61                  :    1;
-            uint32_t frhost_bit71                  :    1;
-            uint32_t rx_start1                     :    1;
-            uint32_t tx_start1                     :    1;
-            uint32_t rx_udf1                       :    1;
-            uint32_t tx_ovf1                       :    1;
-            uint32_t token0_1to01                  :    1;
-            uint32_t token1_1to01                  :    1;
-            uint32_t tx_done1                      :    1;
-            uint32_t tx_suc_eof1                   :    1;
-            uint32_t rx_done1                      :    1;
-            uint32_t rx_eof1                       :    1;
-            uint32_t tohost1                       :    1;
-            uint32_t tx_dscr_err1                  :    1;
-            uint32_t rx_dscr_err1                  :    1;
-            uint32_t tx_dscr_empty1                :    1;
-            uint32_t host_rd_ack1                  :    1;
-            uint32_t wr_retry_done1                :    1;
-            uint32_t tx_err_eof1                   :    1;
-            uint32_t cmd_dtc1                      :    1;
-            uint32_t rx_quick_eof1                 :    1;
-            uint32_t host_pop_eof_err1             :    1;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } slc0_int_st1;
-    union {
-        struct {
-            uint32_t frhost_bit01                  :    1;
-            uint32_t frhost_bit11                  :    1;
-            uint32_t frhost_bit21                  :    1;
-            uint32_t frhost_bit31                  :    1;
-            uint32_t frhost_bit41                  :    1;
-            uint32_t frhost_bit51                  :    1;
-            uint32_t frhost_bit61                  :    1;
-            uint32_t frhost_bit71                  :    1;
-            uint32_t rx_start1                     :    1;
-            uint32_t tx_start1                     :    1;
-            uint32_t rx_udf1                       :    1;
-            uint32_t tx_ovf1                       :    1;
-            uint32_t token0_1to01                  :    1;
-            uint32_t token1_1to01                  :    1;
-            uint32_t tx_done1                      :    1;
-            uint32_t tx_suc_eof1                   :    1;
-            uint32_t rx_done1                      :    1;
-            uint32_t rx_eof1                       :    1;
-            uint32_t tohost1                       :    1;
-            uint32_t tx_dscr_err1                  :    1;
-            uint32_t rx_dscr_err1                  :    1;
-            uint32_t tx_dscr_empty1                :    1;
-            uint32_t host_rd_ack1                  :    1;
-            uint32_t wr_retry_done1                :    1;
-            uint32_t tx_err_eof1                   :    1;
-            uint32_t cmd_dtc1                      :    1;
-            uint32_t rx_quick_eof1                 :    1;
-            uint32_t host_pop_eof_err1             :    1;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } slc0_int_ena1;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t date;
-    uint32_t id;
-} slc_dev_t;
-extern slc_dev_t SLC;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SLC_STRUCT_H_ */
diff --git a/components/soc/esp32s3/include/soc/spi_mem_struct.h b/components/soc/esp32s3/include/soc/spi_mem_struct.h
index 32ce1bf933..aa6f388653 100644
--- a/components/soc/esp32s3/include/soc/spi_mem_struct.h
+++ b/components/soc/esp32s3/include/soc/spi_mem_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct spi_mem_dev_s {
     union {
         struct {
             uint32_t reserved0                     :    17;  /*reserved*/
diff --git a/components/soc/esp32s3/include/soc/spi_struct.h b/components/soc/esp32s3/include/soc/spi_struct.h
index c57ad937ce..2a3abd257c 100644
--- a/components/soc/esp32s3/include/soc/spi_struct.h
+++ b/components/soc/esp32s3/include/soc/spi_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct spi_dev_s {
     union {
         struct {
             uint32_t conf_bitlen                   :    18;  /*Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.*/
diff --git a/components/soc/esp32s3/include/soc/syscon_struct.h b/components/soc/esp32s3/include/soc/syscon_struct.h
index 6c32efe3d6..98c5a64619 100644
--- a/components/soc/esp32s3/include/soc/syscon_struct.h
+++ b/components/soc/esp32s3/include/soc/syscon_struct.h
@@ -18,7 +18,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct syscon_dev_s {
     union {
         struct {
             uint32_t apb_ctrl_pre_div_cnt: 10;
diff --git a/components/soc/esp32s3/include/soc/system_struct.h b/components/soc/esp32s3/include/soc/system_struct.h
index d81146c9b0..6c4ce1f118 100644
--- a/components/soc/esp32s3/include/soc/system_struct.h
+++ b/components/soc/esp32s3/include/soc/system_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct system_dev_s {
     union {
         struct {
             uint32_t control_core_1_runstall       :    1;
diff --git a/components/soc/esp32s3/include/soc/systimer_struct.h b/components/soc/esp32s3/include/soc/systimer_struct.h
index 1d5c4a8c5f..115058c522 100644
--- a/components/soc/esp32s3/include/soc/systimer_struct.h
+++ b/components/soc/esp32s3/include/soc/systimer_struct.h
@@ -90,6 +90,7 @@ typedef union {
          *  update timer_unit0
          */
         uint32_t timer_unit_update: 1;
+        uint32_t reserved_32: 1;
     };
     uint32_t val;
 } systimer_unit_op_reg_t;
@@ -104,6 +105,7 @@ typedef struct {
              *  timer unit load high 32 bit
              */
             uint32_t timer_unit_load_hi: 20;
+            uint32_t reserved_20: 12;
         };
         uint32_t val;
     } hi;
@@ -129,6 +131,7 @@ typedef struct {
              *  timer target high 32 bit
              */
             uint32_t timer_target_hi: 20;
+            uint32_t reserved_20: 12;
         };
         uint32_t val;
     } hi;
@@ -177,6 +180,7 @@ typedef struct {
              *  timer read value high 20bit
              */
             uint32_t timer_unit_value_hi: 20;
+            uint32_t reserved_20: 12;
         };
         uint32_t val;
     } hi;
@@ -201,6 +205,7 @@ typedef union {
          *  timer comp load value
          */
         uint32_t timer_comp_load: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } systimer_comp_load_reg_t;
@@ -215,6 +220,7 @@ typedef union {
          *  timer unit load value
          */
         uint32_t timer_unit_load: 1;
+        uint32_t reserved_1: 31;
     };
     uint32_t val;
 } systimer_unit_load_reg_t;
@@ -238,6 +244,7 @@ typedef union {
          *  interupt2 enable
          */
         uint32_t target2_int_ena: 1;
+        uint32_t reserved_3: 29;
     };
     uint32_t val;
 } systimer_int_ena_reg_t;
@@ -259,6 +266,7 @@ typedef union {
          *  interupt2 raw
          */
         uint32_t target2_int_raw: 1;
+        uint32_t reserved_3: 29;
     };
     uint32_t val;
 } systimer_int_raw_reg_t;
@@ -280,6 +288,7 @@ typedef union {
          *  interupt2 clear
          */
         uint32_t target2_int_clr: 1;
+        uint32_t reserved_3: 29;
     };
     uint32_t val;
 } systimer_int_clr_reg_t;
@@ -301,6 +310,7 @@ typedef union {
          *  interupt2 status
          */
         uint32_t target2_int_st: 1;
+        uint32_t reserved_3: 29;
     };
     uint32_t val;
 } systimer_int_st_reg_t;
@@ -325,6 +335,7 @@ typedef struct {
              *  actual target value value high 20bits
              */
             uint32_t target_hi_ro: 20;
+            uint32_t reserved_20: 12;
         };
         uint32_t val;
     } hi;
diff --git a/components/soc/esp32s3/include/soc/twai_struct.h b/components/soc/esp32s3/include/soc/twai_struct.h
index 19810eda15..df022feb47 100644
--- a/components/soc/esp32s3/include/soc/twai_struct.h
+++ b/components/soc/esp32s3/include/soc/twai_struct.h
@@ -23,7 +23,7 @@ extern "C" {
 
 /* ---------------------------- Register Layout ------------------------------ */
 
-/* The TWAI peripheral's registers are 8bits, however the ESP32 can only access
+/* The TWAI peripheral's registers are 8bits, however the ESP32-S3 can only access
  * peripheral registers every 32bits. Therefore each TWAI register is mapped to
  * the least significant byte of every 32bits.
  */
@@ -36,10 +36,10 @@ typedef volatile struct twai_dev_s {
             uint32_t lom: 1;                    /* MOD.1 Listen Only Mode */
             uint32_t stm: 1;                    /* MOD.2 Self Test Mode */
             uint32_t afm: 1;                    /* MOD.3 Acceptance Filter Mode */
-            uint32_t reserved28: 28;            /* Internal Reserved. MOD.4 Sleep Mode not supported */
+            uint32_t reserved4: 28;             /* Internal Reserved. MOD.4 Sleep Mode not supported */
         };
         uint32_t val;
-    } mode_reg;                                 /* Address 0 */
+    } mode_reg;                                 /* Address 0x0000 */
     union {
         struct {
             uint32_t tr: 1;                     /* CMR.0 Transmission Request */
@@ -47,10 +47,10 @@ typedef volatile struct twai_dev_s {
             uint32_t rrb: 1;                    /* CMR.2 Release Receive Buffer */
             uint32_t cdo: 1;                    /* CMR.3 Clear Data Overrun */
             uint32_t srr: 1;                    /* CMR.4 Self Reception Request */
-            uint32_t reserved27: 27;            /* Internal Reserved */
+            uint32_t reserved5: 27;             /* Internal Reserved */
         };
         uint32_t val;
-    } command_reg;                              /* Address 1 */
+    } command_reg;                              /* Address 0x0004 */
     union {
         struct {
             uint32_t rbs: 1;                    /* SR.0 Receive Buffer Status */
@@ -62,97 +62,99 @@ typedef volatile struct twai_dev_s {
             uint32_t es: 1;                     /* SR.6 Error Status */
             uint32_t bs: 1;                     /* SR.7 Bus Status */
             uint32_t ms: 1;                     /* SR.8 Miss Status */
-            uint32_t reserved24: 23;            /* Internal Reserved */
+            uint32_t reserved9: 23;             /* Internal Reserved */
         };
         uint32_t val;
-    } status_reg;                               /* Address 2 */
+    } status_reg;                               /* Address 0x0008 */
     union {
         struct {
             uint32_t ri: 1;                     /* IR.0 Receive Interrupt */
             uint32_t ti: 1;                     /* IR.1 Transmit Interrupt */
             uint32_t ei: 1;                     /* IR.2 Error Interrupt */
-            uint32_t reserved2: 2;              /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
+            uint32_t doi: 1;                    /* IR.3 Data Overrun Interrupt */
+            uint32_t reserved4: 1;              /* Internal Reserved (Wake-up not supported) */
             uint32_t epi: 1;                    /* IR.5 Error Passive Interrupt */
             uint32_t ali: 1;                    /* IR.6 Arbitration Lost Interrupt */
             uint32_t bei: 1;                    /* IR.7 Bus Error Interrupt */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } interrupt_reg;                           /* Address 3 */
+    } interrupt_reg;                           /* Address 0x000C */
     union {
         struct {
             uint32_t rie: 1;                    /* IER.0 Receive Interrupt Enable */
             uint32_t tie: 1;                    /* IER.1 Transmit Interrupt Enable */
             uint32_t eie: 1;                    /* IER.2 Error Interrupt Enable */
-            uint32_t reserved2: 2;              /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
+            uint32_t doie: 1;                   /* IER.3 Data Overrun Interrupt Enable */
+            uint32_t reserved4: 1;              /* Internal Reserved (Wake-up not supported) */
             uint32_t epie: 1;                   /* IER.5 Error Passive Interrupt Enable */
             uint32_t alie: 1;                   /* IER.6 Arbitration Lost Interrupt Enable */
             uint32_t beie: 1;                   /* IER.7 Bus Error Interrupt Enable */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } interrupt_enable_reg;                     /* Address 4 */
-    uint32_t reserved_05;                       /* Address 5 */
+    } interrupt_enable_reg;                     /* Address 0x0010 */
+    uint32_t reserved_14;
     union {
         struct {
             uint32_t brp: 13;                   /* BTR0[12:0] Baud Rate Prescaler */
-            uint32_t reserved1: 1;              /* Internal Reserved */
+            uint32_t reserved13: 1;             /* Internal Reserved */
             uint32_t sjw: 2;                    /* BTR0[15:14] Synchronization Jump Width*/
             uint32_t reserved16: 16;            /* Internal Reserved */
         };
         uint32_t val;
-    } bus_timing_0_reg;                         /* Address 6 */
+    } bus_timing_0_reg;                         /* Address 0x0018 */
     union {
         struct {
             uint32_t tseg1: 4;                  /* BTR1[3:0] Timing Segment 1 */
             uint32_t tseg2: 3;                  /* BTR1[6:4] Timing Segment 2 */
             uint32_t sam: 1;                    /* BTR1.7 Sampling*/
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } bus_timing_1_reg;                         /* Address 7 */
-    uint32_t reserved_08;                       /* Address 8 (Output control not supported) */
-    uint32_t reserved_09;                       /* Address 9 (Test Register not supported) */
-    uint32_t reserved_10;                       /* Address 10 */
+    } bus_timing_1_reg;                         /* Address 0x001C */
+    uint32_t reserved_20;                       /* Address 0x0020 (Output control not supported) */
+    uint32_t reserved_24;                       /* Address 0x0024 (Test Register not supported) */
+    uint32_t reserved_28;                       /* Address 0x0028 */
 
     //Capture and Counter Registers
     union {
         struct {
             uint32_t alc: 5;                    /* ALC[4:0] Arbitration lost capture */
-            uint32_t reserved27: 27;            /* Internal Reserved */
+            uint32_t reserved5: 27;             /* Internal Reserved */
         };
         uint32_t val;
-    } arbitration_lost_captue_reg;              /* Address 11 */
+    } arbitration_lost_captue_reg;              /* Address 0x002C */
     union {
         struct {
             uint32_t seg: 5;                    /* ECC[4:0] Error Code Segment 0 to 5 */
             uint32_t dir: 1;                    /* ECC.5 Error Direction (TX/RX) */
             uint32_t errc: 2;                   /* ECC[7:6] Error Code */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } error_code_capture_reg;                   /* Address 12 */
+    } error_code_capture_reg;                   /* Address 0x0030 */
     union {
         struct {
             uint32_t ewl: 8;                    /* EWL[7:0] Error Warning Limit */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } error_warning_limit_reg;                  /* EWLR[7:0] Error Warning Limit: Address 13 */
+    } error_warning_limit_reg;                  /* Address 0x0034 */
     union {
         struct {
             uint32_t rxerr: 8;                  /* RXERR[7:0] Receive Error Counter */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } rx_error_counter_reg;                     /* Address 12 */
+    } rx_error_counter_reg;                     /* Address 0x0038 */
     union {
         struct {
             uint32_t txerr: 8;                  /* TXERR[7:0] Receive Error Counter */
-            uint32_t reserved24: 24;            /* Internal Reserved */
+            uint32_t reserved8: 24;             /* Internal Reserved */
         };
         uint32_t val;
-    } tx_error_counter_reg;                     /* Address 15 */
+    } tx_error_counter_reg;                     /* Address 0x003C */
 
     //Shared Registers (TX Buff/RX Buff/Acc Filter)
     union {
@@ -160,45 +162,49 @@ typedef volatile struct twai_dev_s {
             union {
                 struct {
                     uint32_t byte: 8;           /* ACRx[7:0] Acceptance Code */
-                    uint32_t reserved24: 24;    /* Internal Reserved */
+                    uint32_t reserved8: 24;     /* Internal Reserved */
                 };
                 uint32_t val;
             } acr[4];
             union {
                 struct {
                     uint32_t byte: 8;           /* AMRx[7:0] Acceptance Mask */
-                    uint32_t reserved24: 24;    /* Internal Reserved */
+                    uint32_t reserved8: 24;     /* Internal Reserved */
                 };
                 uint32_t val;
             } amr[4];
-            uint32_t reserved32[5];
+            uint32_t reserved_60;
+            uint32_t reserved_64;
+            uint32_t reserved_68;
+            uint32_t reserved_6c;
+            uint32_t reserved_70;
         } acceptance_filter;
         union {
             struct {
-                uint32_t byte: 8;
-                uint32_t reserved24: 24;
+                uint32_t byte: 8;               /* TX/RX Byte X [7:0] */
+                uint32_t reserved24: 24;        /* Internal Reserved */
             };
             uint32_t val;
         } tx_rx_buffer[13];
-    };                                          /* Address 16-28 TX/RX Buffer and Acc Filter*/;
+    };                                          /* Address 0x0040 - 0x0070 */
 
     //Misc Registers
     union {
         struct {
             uint32_t rmc: 7;                    /* RMC[6:0] RX Message Counter */
-            uint32_t reserved25: 25;            /* Internal Reserved */
+            uint32_t reserved7: 25;             /* Internal Reserved */
         };
         uint32_t val;
-    } rx_message_counter_reg;                   /* Address 29 */
-    uint32_t reserved_30;                       /* Address 30 (RX Buffer Start Address not supported) */
+    } rx_message_counter_reg;                   /* Address 0x0074 */
+    uint32_t reserved_78;                       /* Address 0x0078 (RX Buffer Start Address not supported) */
     union {
         struct {
             uint32_t cd: 8;                     /* CDR[7:0] CLKOUT frequency selector based of fOSC */
             uint32_t co: 1;                     /* CDR.8 CLKOUT enable/disable */
-            uint32_t reserved24: 23;            /* Internal Reserved  */
+            uint32_t reserved9: 23;             /* Internal Reserved  */
         };
         uint32_t val;
-    } clock_divider_reg;                        /* Address 31 */
+    } clock_divider_reg;                        /* Address 0x007C */
 } twai_dev_t;
 
 _Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
diff --git a/components/soc/esp32s3/include/soc/uhci_struct.h b/components/soc/esp32s3/include/soc/uhci_struct.h
index 2f7f2cee28..6fdd2cad1f 100644
--- a/components/soc/esp32s3/include/soc/uhci_struct.h
+++ b/components/soc/esp32s3/include/soc/uhci_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct uhci_dev_s {
     union {
         struct {
             uint32_t tx_rst                        :    1;
diff --git a/components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
index cac2ddedac..539717f267 100644
--- a/components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
+++ b/components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
@@ -20,7 +20,7 @@ extern "C" {
 #endif
 #include "soc.h"
 
-typedef volatile struct {
+typedef volatile struct usb_serial_jtag_dev_s {
     union {
         struct {
             uint32_t rdwr_byte                 :    32;  /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.*/
diff --git a/components/soc/esp32s3/include/soc/usb_wrap_struct.h b/components/soc/esp32s3/include/soc/usb_wrap_struct.h
index ba38facf52..91b79d9119 100644
--- a/components/soc/esp32s3/include/soc/usb_wrap_struct.h
+++ b/components/soc/esp32s3/include/soc/usb_wrap_struct.h
@@ -154,6 +154,7 @@ typedef union {
          *  USB D- rx value in test.
          */
         uint32_t test_rx_dm:1;
+        uint32_t reserved7: 25;
     };
     uint32_t val;
 } usb_wrap_test_conf_reg_t;
diff --git a/components/soc/esp32s3/include/soc/usbh_struct.h b/components/soc/esp32s3/include/soc/usbh_struct.h
index 7401bbf9cf..3a52bf9952 100644
--- a/components/soc/esp32s3/include/soc/usbh_struct.h
+++ b/components/soc/esp32s3/include/soc/usbh_struct.h
@@ -831,7 +831,7 @@ typedef union {
         uint32_t bbleerr: 1;
         uint32_t nakintrpt: 1;
         uint32_t nyetintrpt: 1;
-        uint32_t reserved16: 16;
+        uint32_t reserved15: 17;
     };
     uint32_t val;
 } usb_diepint_reg_t;
diff --git a/components/soc/esp32s3/include/soc/world_controller_struct.h b/components/soc/esp32s3/include/soc/world_controller_struct.h
index da042acda5..89a317d9a3 100644
--- a/components/soc/esp32s3/include/soc/world_controller_struct.h
+++ b/components/soc/esp32s3/include/soc/world_controller_struct.h
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct world_controller_dev_s {
     uint32_t wcl_core_0_entry_1_addr;
     uint32_t wcl_core_0_entry_2_addr;
     uint32_t wcl_core_0_entry_3_addr;
diff --git a/components/soc/include/soc/sdio_slave_periph.h b/components/soc/include/soc/sdio_slave_periph.h
index d39f72f526..0f748ae12e 100644
--- a/components/soc/include/soc/sdio_slave_periph.h
+++ b/components/soc/include/soc/sdio_slave_periph.h
@@ -15,9 +15,12 @@
 #pragma once
 #include <stdint.h>
 //include soc related (generated) definitions
+#include "soc/soc_caps.h"
 #include "soc/soc_pins.h"
+#ifdef SOC_SDIO_SLAVE_SUPPORTED
 #include "soc/slc_reg.h"
 #include "soc/slc_struct.h"
+#endif
 #include "soc/host_reg.h"
 #include "soc/host_struct.h"
 #include "soc/hinf_reg.h"
diff --git a/tools/ci/check_soc_struct_headers.py b/tools/ci/check_soc_struct_headers.py
new file mode 100755
index 0000000000..7611a4a2fa
--- /dev/null
+++ b/tools/ci/check_soc_struct_headers.py
@@ -0,0 +1,420 @@
+#!/usr/bin/env python
+
+# A check script that just works at the time of writing...
+#
+# also builds a structure tree for further reference
+#
+# Input file format must be similiar to those headers generated by regtool, or this script makes no sense at all
+#
+# Known limitation:
+# 1. won't accept /* ... */ /* ... */': badly behavior with multiline comment
+# 2. won't accept multiple expression within same line' (but will info that)
+# 3. won't accept single line struct/union definition
+#
+# Check list:
+# 1. a structure should not contain bitfield member alongside with nested struct/union
+# 2. bitfield sum in a struct should be 32 (means being well padded)
+# 3. each bitfield type should be uint32_t
+# 4. expecting union to be `union { struct {xxx}; uint32_t val; }` and complain if it is not an u32 val (but not fail)
+# 5. typedef volatile struct xxx{}: xxx must exists
+#
+# Otherwise won't fail but warning
+
+import os
+import re
+import sys
+from typing import Any
+
+
+class MemberField:
+    member_type = ''
+    bitfield = None
+
+    def __init__(self, m_type: str, m_bits: int=None) -> None:
+        self.member_type = m_type
+        self.bitfield = m_bits
+
+    def __unicode__(self) -> str:
+        return self.__str__()
+
+    def __repr__(self) -> str:
+        return self.__str__()
+
+    def __str__(self) -> str:
+        if self.bitfield is None:
+            return '"Field type={}"'.format(self.member_type)
+        return '"Field type={} bit={}"'.format(self.member_type, self.bitfield)
+
+
+class SoCStructureHeaderChecker:
+    # capture: typedef, volatile, struct name
+    __REGEXP_MATCH_STRUCTURE_BEGIN = r'^[\s]*(typedef)?(?:[\s]+(volatile))?[\s]+struct[\s]+([\w]+)?[\s\S]*$'
+    # capture: typedef, volatile, union name
+    __REGEXP_MATCH_UNION_BEGIN = r'^[\s]*(typedef)?(?:[\s]+(volatile))?[\s]+union[\s]+([\w]+)?[\s\S]*$'
+    # capture: type_var_name
+    __REGEXP_MATCH_STRUCT_UNION_END_NAME = r'^[\s]*}[\s]*([\w\[\]\*]*)[\s]*;[\s\S]*$'
+    # capture: type, name, bitfield
+    __REGEXP_MATCH_BITFIELD_MEMBER = (r'^[\s]*(?:(?:volatile[\s]+)|(?:))([\w\*]+)[\s]+([\w\*]+(?:(?:\[[\s\S]*\])|(?:)))'
+                                      r'[\s]*(?:(?:[\s]*;)|(?::[\s]*([\d]+)[\s]*;))[\s\S]*$')
+    # should be useless and can be safely deleted
+    __REGEXP_MATCH_MULTILINE_COMMENT = r'^[\s]*[\/]{0,2}\*[\/]?[\s\S]*$'
+    __REGEX_MATCH_SIMPLE_VAL_FIELD = r'^[\s]*(?:(?:volatile[\s]+)|(?:))([\w]+)[\s]+([\w\[\]\*]+)[\s]*;[\s]*$'
+    # capture: type, name
+    __REGEX_MATCH_ROOT_EXTERNAL = r'^[\s]*extern[\s]+([\w]+)[\s]+([\w]+)[\s]*;[\s]*$'
+
+    __linecount = 0
+    __fd = None     # type: Any
+    __is_eof = False
+
+    # generated reference tree
+    __ref_tree = dict()     # type: dict
+    # middle result of generated tree, shared
+    # named typedef, or named struct/union. referd but will not delete
+    __temp_ref_types = dict()   # type: dict
+
+    def __expand_type(self, member_type: str, bitfield: int=None) -> Any:
+        if member_type == 'uint32_t':
+            return MemberField(member_type, bitfield)
+        if bitfield is not None:
+            print('\033[0;31mERROR\033[0m: non-u32 type with bitfield')
+            return None
+        if member_type in self.__temp_ref_types:
+            return self.__temp_ref_types[member_type]
+        return None
+
+    def __getline(self, incomment:bool=False) -> Any:
+        rawline = self.__fd.readline()
+        if not rawline:
+            self.__is_eof = True
+            return None
+        self.__linecount += 1
+
+        if incomment:
+            pos = rawline.find('*/')
+            if pos != -1:
+                # set string that is behind comment
+                rawline = rawline[pos + 2:]
+            else:
+                # continue multiple line
+                return self.__getline(True)
+
+        # preprocess: remove '// comment'
+        match_obj = re.match(r'^([^(\/\/)]*)\/\/[\s\S]*$', rawline)
+        if match_obj is not None:
+            rawline = match_obj.groups()[0]
+        # preprocess: remove '/* comment'
+        match_obj = re.match(r'^([^(\/\*)]*)\/\*([\s\S]*)$', rawline)
+        if match_obj is not None:
+            rawline = match_obj.groups()[0]
+            # check if multiline commit in oneline
+            pos = match_obj.groups()[1].find('*/')
+            if pos != -1:
+                # apply string that is behind comment
+                rawline = rawline + match_obj.groups()[1][pos + 2:]
+            else:
+                # multiple line
+                return self.__getline(True)
+
+        if re.match(r'^[\s]*$', rawline):
+            # skip empty line
+            return self.__getline()
+        if rawline.count(';') > 1:
+            print('\033[0;34mINFO\033[0m: line: {}: possibily multiple expression within same line'.format(self.__linecount))
+            print(rawline)
+        return rawline
+
+    def __process_structure(self, name: str, is_typedef: bool, is_volatile: bool) -> Any:
+        ret_val = 0
+        # first check for anonymous register structs
+        if is_typedef and is_volatile and name is None:
+            print('\033[0;31mERROR\033[0m: line {}: annoymous struct'.format(self.__linecount))
+            ret_val = -1
+        node_tree = dict()
+        bitcount = 0
+        has_nested_struct_union = False
+        has_non_bitfield_member = False
+        parsed_varname = ''
+        while not self.__is_eof:
+            rawline = self.__getline()
+            if rawline is None:
+                break
+            # check for nested structure
+            match_obj = re.match(self.__REGEXP_MATCH_STRUCTURE_BEGIN, rawline)
+            if match_obj is not None:
+                has_nested_struct_union = True
+                ret, inherited_node_tree = self.__process_structure(
+                    match_obj.groups()[2], match_obj.groups()[0] == 'typedef', match_obj.groups()[1] == 'volatile')
+                if ret != 0:
+                    ret_val = -2
+                if inherited_node_tree is not None:
+                    for node in inherited_node_tree:
+                        node_tree[node] = inherited_node_tree[node]
+                continue
+            match_obj = re.match(self.__REGEXP_MATCH_UNION_BEGIN, rawline)
+            if match_obj is not None:
+                has_nested_struct_union = True
+                ret, inherited_node_tree = self.__process_union(match_obj.groups()[2], match_obj.groups()[0] == 'typedef', match_obj.groups()[1] == 'volatile')
+                if ret != 0:
+                    ret_val = -2
+                if inherited_node_tree is not None:
+                    for node in inherited_node_tree:
+                        node_tree[node] = inherited_node_tree[node]
+                continue
+            # check if end of struct
+            match_obj = re.match(self.__REGEXP_MATCH_STRUCT_UNION_END_NAME, rawline)
+            if match_obj is not None:
+                # end of struct
+                if bitcount not in (0, 32):
+                    ret_val = -2
+                    if is_typedef:
+                        print('\033[0;31mERROR\033[0m: line {}: bitfield count is {}, type {}'.format(self.__linecount, bitcount, match_obj.groups()[0]))
+                    else:
+                        print('\033[0;31mERROR\033[0m: line {}: bitfield count is {}, type {}, varname "{}"'
+                              .format(self.__linecount, bitcount, name, match_obj.groups()[0]))
+                parsed_varname = match_obj.groups()[0]
+                if is_typedef:
+                    # is a typedef
+                    if match_obj.groups()[0] == '' or match_obj.groups()[0].find('[') != -1:
+                        # should be c error
+                        print('\033[0;31mERROR\033[0m: line {}: C error'.format(self.__linecount))
+                        ret_val = -3
+                    if match_obj.groups()[0] in self.__temp_ref_types:
+                        # duplication, script bug: we are putting all types into same namespace
+                        print('script run into bug...')
+                    self.__temp_ref_types[match_obj.groups()[0]] = dict()
+                    for member in node_tree:
+                        self.__temp_ref_types[match_obj.groups()[0]][member] = node_tree[member]
+                elif name is not None:
+                    # currently this kind of expression doesn't exist
+                    print('!!!!!!UNDEALED CONDITION!!!!!')
+                elif match_obj.groups()[0] != '':
+                    # named member, wrap and overwrite
+                    if len(node_tree) == 0:
+                        node_tree = None
+                    else:
+                        array_match = re.match(r'^([\w]*)\[[\s\S]*\]$', match_obj.groups()[0])
+                        if array_match is not None:
+                            node_tree = {array_match.groups()[0] + '[]': node_tree}
+                        else:
+                            node_tree = {match_obj.groups()[0]: node_tree}
+                else:
+                    # not a type, no member name, treat its fields as its parent's
+                    pass
+                break
+            # check member
+            match_obj = re.match(self.__REGEXP_MATCH_BITFIELD_MEMBER, rawline)
+            if match_obj is not None:
+                field_bit = None
+                if match_obj.groups()[2] is not None:
+                    field_bit = int(match_obj.groups()[2])
+                    bitcount += field_bit
+                    # bitfield should be u32
+                    if match_obj.groups()[0] != 'uint32_t':
+                        print('\033[0;33mWARN\033[0m: line: {}: {} has type {}'.format(self.__linecount, match_obj.groups()[1], match_obj.groups()[0]))
+                else:
+                    has_non_bitfield_member = True
+                # append to node tree
+                member_node = self.__expand_type(match_obj.groups()[0], field_bit)
+                if member_node is not None:
+                    array_match = re.match(r'^([\w]*)\[[\s\S]*\]$', match_obj.groups()[1])
+                    if array_match is not None:
+                        node_tree[array_match.groups()[0] + '[]'] = member_node
+                    else:
+                        node_tree[match_obj.groups()[1]] = member_node
+                else:
+                    if '*' not in match_obj.groups()[0]:
+                        print('\033[0;33mWARN\033[0m: line {}: unknown type {}'.format(self.__linecount, match_obj.groups()[0]))
+                    else:
+                        print('\033[0;33mWARN\033[0m: line {}: pointer type {}'.format(self.__linecount, match_obj.groups()[0]))
+                continue
+            # check comments
+            match_obj = re.match(self.__REGEXP_MATCH_MULTILINE_COMMENT, rawline)
+            if match_obj is not None:
+                # code comments
+                continue
+            # dump out unmatched condition
+            print(('\033[0;33mWARN\033[0m: line: {}: unexpected expression: {}'.format(self.__linecount, rawline)).replace('\n', ''))
+
+        if bitcount != 0 and has_nested_struct_union:
+            print('\033[0;33mWARN\033[0m: line: {}: mixed bitfield member and nested structure/union'.format(self.__linecount))
+        if bitcount != 0 and has_non_bitfield_member:
+            print('\033[0;33mWARN\033[0m: line: {}: mixed bitfield member and non-bitfield member'.format(self.__linecount))
+        if is_typedef and is_volatile and name is None:
+            if parsed_varname != '':
+                print('SUGGEST: {}'.format(parsed_varname.rstrip('t') + 's'))
+        if name is not None and is_typedef and is_volatile and parsed_varname.rstrip('t') != name.rstrip('s'):
+            print('\033[0;33mWARN\033[0m: line: {}: different type and typedef name: {} {}'.format(self.__linecount, name, parsed_varname))
+        return ret_val, node_tree
+
+    def __process_union(self, name: str, is_typedef: bool, is_volatile: bool) -> Any:
+        ret_val = 0
+        # first check for anonymous register structs
+        if is_typedef and is_volatile and name is None:
+            print('\033[0;31mERROR\033[0m: line {}: annoymous union'.format(self.__linecount))
+            ret_val = -1
+        node_tree = dict()  # type: Any
+        has_struct_count = 0
+        has_val_field_count = 0
+        while not self.__is_eof:
+            rawline = self.__getline()
+            if rawline is None:
+                break
+            # check for nested structure
+            match_obj = re.match(self.__REGEXP_MATCH_STRUCTURE_BEGIN, rawline)
+            if match_obj is not None:
+                has_struct_count += 1
+                ret, inherited_node_tree = self.__process_structure(
+                    match_obj.groups()[2], match_obj.groups()[0] == 'typedef', match_obj.groups()[1] == 'volatile')
+                if ret != 0:
+                    ret_val = -2
+                if inherited_node_tree is not None:
+                    for node in inherited_node_tree:
+                        node_tree[node] = inherited_node_tree[node]
+                continue
+            match_obj = re.match(self.__REGEXP_MATCH_UNION_BEGIN, rawline)
+            if match_obj is not None:
+                has_struct_count += 1
+                ret, inherited_node_tree = self.__process_union(match_obj.groups()[2], match_obj.groups()[0] == 'typedef', match_obj.groups()[1] == 'volatile')
+                if ret != 0:
+                    ret_val = -2
+                if inherited_node_tree is not None:
+                    for node in inherited_node_tree:
+                        node_tree[node] = inherited_node_tree[node]
+                continue
+            match_obj = re.match(self.__REGEXP_MATCH_STRUCT_UNION_END_NAME, rawline)
+            if match_obj is not None:
+                parsed_varname = match_obj.groups()[0]
+                # end of struct
+                if is_typedef:
+                    # is a typedef
+                    if match_obj.groups()[0] == '':
+                        # should be c error
+                        print('\033[0;31mERROR\033[0m: line {}: C error'.format(self.__linecount))
+                        ret_val = -3
+                    if match_obj.groups()[0] in self.__temp_ref_types:
+                        # duplication, script bug: we are putting all types into same namespace
+                        print('script run into bug...')
+                    self.__temp_ref_types[match_obj.groups()[0]] = dict()
+                    for member in node_tree:
+                        self.__temp_ref_types[match_obj.groups()[0]][member] = node_tree[member]
+                    node_tree = None
+                elif name is not None:
+                    # currently this kind of expression doesn't exist
+                    print('!!!!!!UNDEALED CONDITION!!!!!')
+                elif match_obj.groups()[0] != '':
+                    # named member, wrap and overwrite
+                    if len(node_tree) == 0:
+                        node_tree = None
+                    else:
+                        array_match = re.match(r'^([\w]*)\[[\s\S]*\]$', match_obj.groups()[0])
+                        if array_match is not None:
+                            node_tree = {array_match.groups()[0] + '[]': node_tree}
+                        else:
+                            node_tree = {match_obj.groups()[0]: node_tree}
+                else:
+                    # not a type, no member name, treat its fields as its parent's
+                    pass
+                break
+            match_obj = re.match(self.__REGEXP_MATCH_MULTILINE_COMMENT, rawline)
+            if match_obj is not None:
+                # code comments
+                continue
+            match_obj = re.match(self.__REGEX_MATCH_SIMPLE_VAL_FIELD, rawline)
+            if match_obj is not None:
+                # expecting to see 'uint32_t val;'
+                if match_obj.groups()[0] != 'uint32_t' or match_obj.groups()[1] != 'val':
+                    print(('\033[0;33mWARN\033[0m: unexpected union member at {}: {}'.format(self.__linecount, rawline)).replace('\n', ''))
+                else:
+                    has_val_field_count += 1
+                # append to node tree
+                member_node = self.__expand_type(match_obj.groups()[0], None)
+                if member_node is not None:
+                    node_tree[match_obj.groups()[1]] = member_node
+                else:
+                    if '*' not in match_obj.groups()[0]:
+                        print('\033[0;31mERROR\033[0m: line {}: unknown type {}'.format(self.__linecount, match_obj.groups()[0]))
+                    else:
+                        print('\033[0;33mWARN\033[0m: line {}: pointer type {}'.format(self.__linecount, match_obj.groups()[0]))
+                continue
+            # dump out unmatched condition
+            print(('\033[0;33mWARN\033[0m: line: {}: unexpected expression: {}'.format(self.__linecount, rawline)).replace('\n', ''))
+
+        if not (has_struct_count == 1 and has_val_field_count == 1):
+            print('\033[0;34mINFO\033[0m: line: {}: not a typical union: {} nested structures, {} u32 val member'
+                  .format(self.__linecount, has_struct_count, has_val_field_count))
+        if is_typedef and is_volatile and name is None:
+            if parsed_varname != '':
+                print('SUGGEST: {}'.format(parsed_varname.rstrip('t') + 's'))
+        if name is not None and is_typedef and is_volatile and parsed_varname.rstrip('t') != name.rstrip('s'):
+            print('\033[0;33mWARN\033[0m: line: {}: different type and typedef name: {} {}'.format(self.__linecount, name, parsed_varname))
+        return ret_val, node_tree
+
+    def __process_root(self) -> int:
+        ret_val = 0
+        node_tree = dict()
+
+        while not self.__is_eof:
+            rawline = self.__getline()
+            if rawline is None:
+                break
+            # start checking by finding any of structure or union
+            match_obj = re.match(self.__REGEXP_MATCH_STRUCTURE_BEGIN, rawline)
+            if match_obj is not None:
+                ret, inherited_node_tree = self.__process_structure(
+                    match_obj.groups()[2], match_obj.groups()[0] == 'typedef', match_obj.groups()[1] == 'volatile')
+                if ret != 0:
+                    ret_val = -2
+                if inherited_node_tree is not None:
+                    for node in inherited_node_tree:
+                        node_tree[node] = inherited_node_tree[node]
+                continue
+            match_obj = re.match(self.__REGEXP_MATCH_UNION_BEGIN, rawline)
+            if match_obj is not None:
+                ret, inherited_node_tree = self.__process_union(match_obj.groups()[2], match_obj.groups()[0] == 'typedef', match_obj.groups()[1] == 'volatile')
+                if ret != 0:
+                    ret_val = -2
+                if inherited_node_tree is not None:
+                    for node in inherited_node_tree:
+                        node_tree[node] = inherited_node_tree[node]
+                continue
+            # processing root level external declaration
+            match_obj = re.match(self.__REGEX_MATCH_ROOT_EXTERNAL, rawline)
+            if match_obj is not None:
+                self.__ref_tree[match_obj.groups()[1]] = self.__expand_type(match_obj.groups()[0])
+                continue
+        return ret_val
+
+    def check(self, file: str) -> int:
+        self.__fd = open(file, 'r', encoding='utf8')
+        self.__linecount = 0
+        self.__is_eof = False
+
+        ret_val = self.__process_root()
+
+        self.__fd.close()
+        if ret_val != 0:
+            print('\033[0;31mCHECK FAILED\033[0m:\t{}'.format(file))
+        else:
+            print('\033[0;32mCHECK PASSED\033[0m:\t{}'.format(file))
+        return ret_val
+
+    def get_ref_tree(self) -> Any:
+        return self.__ref_tree
+
+
+def main() -> None:
+    ret = 0
+    if len(sys.argv) <= 1 or not os.path.isfile(sys.argv[1]):
+        print('file not exist')
+        exit(-1)
+    checker = SoCStructureHeaderChecker()
+    print('CHECKING:\t{}'.format(sys.argv[1]))
+    ret = checker.check(sys.argv[1])
+    if len(sys.argv) == 3 and sys.argv[2] == 'print':
+        print(checker.get_ref_tree())
+    del checker
+    sys.exit(ret)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/tools/ci/executable-list.txt b/tools/ci/executable-list.txt
index 370042d92c..08a7100646 100644
--- a/tools/ci/executable-list.txt
+++ b/tools/ci/executable-list.txt
@@ -47,6 +47,7 @@ tools/ci/check_idf_version.sh
 tools/ci/check_kconfigs.py
 tools/ci/check_readme_links.py
 tools/ci/check_rules_yml.py
+tools/ci/check_soc_struct_headers.py
 tools/ci/check_tools_files_patterns.py
 tools/ci/check_type_comments.py
 tools/ci/check_ut_cmake_make.sh

From 892f5e7df324157824e4ce2bf45e24de39f050f2 Mon Sep 17 00:00:00 2001
From: SalimTerryLi <lihangfan@espressif.com>
Date: Tue, 24 Aug 2021 15:32:08 +0800
Subject: [PATCH 2/2] timer_group: fix wrongly generated reg header that
 introduced in 443845fd54e6cf874933138ea492e70aa6345140

---
 .../soc/esp32c3/include/soc/timer_group_reg.h | 46 +++++-----
 .../soc/esp32h2/include/soc/timer_group_reg.h | 46 +++++-----
 .../soc/esp32s2/include/soc/timer_group_reg.h | 84 +++++++++----------
 3 files changed, 88 insertions(+), 88 deletions(-)

diff --git a/components/soc/esp32c3/include/soc/timer_group_reg.h b/components/soc/esp32c3/include/soc/timer_group_reg.h
index 35f29209aa..4d591035fc 100644
--- a/components/soc/esp32c3/include/soc/timer_group_reg.h
+++ b/components/soc/esp32c3/include/soc/timer_group_reg.h
@@ -35,7 +35,7 @@ extern "C" {
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
  */
-#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
+#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
 /** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
  *  1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
  *  clock of timer group.
@@ -92,7 +92,7 @@ extern "C" {
 /** TIMG_T0LO_REG register
  *  Timer 0 current value, low 32 bits
  */
-#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
+#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
 /** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
  *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
  *  of timer 0 can be read here.
@@ -105,7 +105,7 @@ extern "C" {
 /** TIMG_T0HI_REG register
  *  Timer $x current value, high 22 bits
  */
-#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
+#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
 /** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
  *  After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
  *  of timer $x can be read here.
@@ -118,7 +118,7 @@ extern "C" {
 /** TIMG_T0UPDATE_REG register
  *  Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
  */
-#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
+#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
 /** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
  *  After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
  */
@@ -130,7 +130,7 @@ extern "C" {
 /** TIMG_T0ALARMLO_REG register
  *  Timer $x alarm value, low 32 bits
  */
-#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
+#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
 /** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
  *  Timer $x alarm trigger time-base counter value, low 32 bits.
  */
@@ -142,7 +142,7 @@ extern "C" {
 /** TIMG_T0ALARMHI_REG register
  *  Timer $x alarm value, high bits
  */
-#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
+#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
 /** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
  *  Timer $x alarm trigger time-base counter value, high 22 bits.
  */
@@ -154,7 +154,7 @@ extern "C" {
 /** TIMG_T0LOADLO_REG register
  *  Timer $x reload value, low 32 bits
  */
-#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
+#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
 /** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
  *  Low 32 bits of the value that a reload will load onto timer $x time-base
  *  Counter.
@@ -167,7 +167,7 @@ extern "C" {
 /** TIMG_T0LOADHI_REG register
  *  Timer $x reload value, high 22 bits
  */
-#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
+#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
 /** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
  *  High 22 bits of the value that a reload will load onto timer $x time-base
  *  counter.
@@ -180,7 +180,7 @@ extern "C" {
 /** TIMG_T0LOAD_REG register
  *  Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
  */
-#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
+#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
 /** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
  *
  *  Write any value to trigger a timer $x time-base counter reload.
@@ -193,7 +193,7 @@ extern "C" {
 /** TIMG_WDTCONFIG0_REG register
  *  Watchdog timer configuration register
  */
-#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
+#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
 /** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
  *  WDT reset CPU enable.
  */
@@ -284,7 +284,7 @@ extern "C" {
 /** TIMG_WDTCONFIG1_REG register
  *  Watchdog timer prescaler register
  */
-#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
+#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
 /** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
  *  When set, WDT 's clock divider counter will be reset.
  */
@@ -304,7 +304,7 @@ extern "C" {
 /** TIMG_WDTCONFIG2_REG register
  *  Watchdog timer stage 0 timeout value
  */
-#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
+#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
 /** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
  *  Stage 0 timeout value, in MWDT clock cycles.
  */
@@ -316,7 +316,7 @@ extern "C" {
 /** TIMG_WDTCONFIG3_REG register
  *  Watchdog timer stage 1 timeout value
  */
-#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
+#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
 /** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
  *  Stage 1 timeout value, in MWDT clock cycles.
  */
@@ -328,7 +328,7 @@ extern "C" {
 /** TIMG_WDTCONFIG4_REG register
  *  Watchdog timer stage 2 timeout value
  */
-#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
+#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
 /** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
  *  Stage 2 timeout value, in MWDT clock cycles.
  */
@@ -340,7 +340,7 @@ extern "C" {
 /** TIMG_WDTCONFIG5_REG register
  *  Watchdog timer stage 3 timeout value
  */
-#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
+#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
 /** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
  *  Stage 3 timeout value, in MWDT clock cycles.
  */
@@ -352,7 +352,7 @@ extern "C" {
 /** TIMG_WDTFEED_REG register
  *  Write to feed the watchdog timer
  */
-#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
+#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
 /** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
  *  Write any value to feed the MWDT. (WO)
  */
@@ -364,7 +364,7 @@ extern "C" {
 /** TIMG_WDTWPROTECT_REG register
  *  Watchdog write protect register
  */
-#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
+#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
 /** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
  *  If the register contains a different value than its reset value, write
  *  protection is enabled.
@@ -436,7 +436,7 @@ extern "C" {
 /** TIMG_INT_ENA_TIMERS_REG register
  *  Interrupt enable bits
  */
-#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
+#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
 /** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
  */
@@ -455,7 +455,7 @@ extern "C" {
 /** TIMG_INT_RAW_TIMERS_REG register
  *  Raw interrupt status
  */
-#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
+#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
 /** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
  *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
  */
@@ -474,7 +474,7 @@ extern "C" {
 /** TIMG_INT_ST_TIMERS_REG register
  *  Masked interrupt status
  */
-#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
+#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
 /** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
  *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
  */
@@ -493,7 +493,7 @@ extern "C" {
 /** TIMG_INT_CLR_TIMERS_REG register
  *  Interrupt clear bits
  */
-#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
+#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
 /** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
  *  Set this bit to clear the TIMG_T$x_INT interrupt.
  */
@@ -539,7 +539,7 @@ extern "C" {
 /** TIMG_NTIMERS_DATE_REG register
  *  Timer version control register
  */
-#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
+#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
 /** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 33579409;
  *  Timer version control register
  */
@@ -551,7 +551,7 @@ extern "C" {
 /** TIMG_REGCLK_REG register
  *  Timer group clock gate register
  */
-#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
+#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
 /** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
  *  enable WDT's clock
  */
diff --git a/components/soc/esp32h2/include/soc/timer_group_reg.h b/components/soc/esp32h2/include/soc/timer_group_reg.h
index 35f29209aa..4d591035fc 100644
--- a/components/soc/esp32h2/include/soc/timer_group_reg.h
+++ b/components/soc/esp32h2/include/soc/timer_group_reg.h
@@ -35,7 +35,7 @@ extern "C" {
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
  */
-#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
+#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
 /** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
  *  1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
  *  clock of timer group.
@@ -92,7 +92,7 @@ extern "C" {
 /** TIMG_T0LO_REG register
  *  Timer 0 current value, low 32 bits
  */
-#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
+#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
 /** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
  *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
  *  of timer 0 can be read here.
@@ -105,7 +105,7 @@ extern "C" {
 /** TIMG_T0HI_REG register
  *  Timer $x current value, high 22 bits
  */
-#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
+#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
 /** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
  *  After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
  *  of timer $x can be read here.
@@ -118,7 +118,7 @@ extern "C" {
 /** TIMG_T0UPDATE_REG register
  *  Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
  */
-#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
+#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
 /** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
  *  After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
  */
@@ -130,7 +130,7 @@ extern "C" {
 /** TIMG_T0ALARMLO_REG register
  *  Timer $x alarm value, low 32 bits
  */
-#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
+#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
 /** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
  *  Timer $x alarm trigger time-base counter value, low 32 bits.
  */
@@ -142,7 +142,7 @@ extern "C" {
 /** TIMG_T0ALARMHI_REG register
  *  Timer $x alarm value, high bits
  */
-#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
+#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
 /** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
  *  Timer $x alarm trigger time-base counter value, high 22 bits.
  */
@@ -154,7 +154,7 @@ extern "C" {
 /** TIMG_T0LOADLO_REG register
  *  Timer $x reload value, low 32 bits
  */
-#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
+#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
 /** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
  *  Low 32 bits of the value that a reload will load onto timer $x time-base
  *  Counter.
@@ -167,7 +167,7 @@ extern "C" {
 /** TIMG_T0LOADHI_REG register
  *  Timer $x reload value, high 22 bits
  */
-#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
+#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
 /** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
  *  High 22 bits of the value that a reload will load onto timer $x time-base
  *  counter.
@@ -180,7 +180,7 @@ extern "C" {
 /** TIMG_T0LOAD_REG register
  *  Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
  */
-#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
+#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
 /** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
  *
  *  Write any value to trigger a timer $x time-base counter reload.
@@ -193,7 +193,7 @@ extern "C" {
 /** TIMG_WDTCONFIG0_REG register
  *  Watchdog timer configuration register
  */
-#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
+#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
 /** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
  *  WDT reset CPU enable.
  */
@@ -284,7 +284,7 @@ extern "C" {
 /** TIMG_WDTCONFIG1_REG register
  *  Watchdog timer prescaler register
  */
-#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
+#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
 /** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
  *  When set, WDT 's clock divider counter will be reset.
  */
@@ -304,7 +304,7 @@ extern "C" {
 /** TIMG_WDTCONFIG2_REG register
  *  Watchdog timer stage 0 timeout value
  */
-#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
+#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
 /** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
  *  Stage 0 timeout value, in MWDT clock cycles.
  */
@@ -316,7 +316,7 @@ extern "C" {
 /** TIMG_WDTCONFIG3_REG register
  *  Watchdog timer stage 1 timeout value
  */
-#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
+#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
 /** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
  *  Stage 1 timeout value, in MWDT clock cycles.
  */
@@ -328,7 +328,7 @@ extern "C" {
 /** TIMG_WDTCONFIG4_REG register
  *  Watchdog timer stage 2 timeout value
  */
-#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
+#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
 /** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
  *  Stage 2 timeout value, in MWDT clock cycles.
  */
@@ -340,7 +340,7 @@ extern "C" {
 /** TIMG_WDTCONFIG5_REG register
  *  Watchdog timer stage 3 timeout value
  */
-#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
+#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
 /** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
  *  Stage 3 timeout value, in MWDT clock cycles.
  */
@@ -352,7 +352,7 @@ extern "C" {
 /** TIMG_WDTFEED_REG register
  *  Write to feed the watchdog timer
  */
-#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
+#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
 /** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
  *  Write any value to feed the MWDT. (WO)
  */
@@ -364,7 +364,7 @@ extern "C" {
 /** TIMG_WDTWPROTECT_REG register
  *  Watchdog write protect register
  */
-#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
+#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
 /** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
  *  If the register contains a different value than its reset value, write
  *  protection is enabled.
@@ -436,7 +436,7 @@ extern "C" {
 /** TIMG_INT_ENA_TIMERS_REG register
  *  Interrupt enable bits
  */
-#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
+#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
 /** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
  */
@@ -455,7 +455,7 @@ extern "C" {
 /** TIMG_INT_RAW_TIMERS_REG register
  *  Raw interrupt status
  */
-#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
+#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
 /** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
  *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
  */
@@ -474,7 +474,7 @@ extern "C" {
 /** TIMG_INT_ST_TIMERS_REG register
  *  Masked interrupt status
  */
-#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
+#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
 /** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
  *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
  */
@@ -493,7 +493,7 @@ extern "C" {
 /** TIMG_INT_CLR_TIMERS_REG register
  *  Interrupt clear bits
  */
-#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
+#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
 /** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
  *  Set this bit to clear the TIMG_T$x_INT interrupt.
  */
@@ -539,7 +539,7 @@ extern "C" {
 /** TIMG_NTIMERS_DATE_REG register
  *  Timer version control register
  */
-#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
+#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
 /** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 33579409;
  *  Timer version control register
  */
@@ -551,7 +551,7 @@ extern "C" {
 /** TIMG_REGCLK_REG register
  *  Timer group clock gate register
  */
-#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
+#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
 /** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
  *  enable WDT's clock
  */
diff --git a/components/soc/esp32s2/include/soc/timer_group_reg.h b/components/soc/esp32s2/include/soc/timer_group_reg.h
index 8fb0e517ad..a74c3e2e5e 100644
--- a/components/soc/esp32s2/include/soc/timer_group_reg.h
+++ b/components/soc/esp32s2/include/soc/timer_group_reg.h
@@ -35,7 +35,7 @@ extern "C" {
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
  */
-#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
+#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
 /** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
  *  1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
  *  clock of timer group.
@@ -101,7 +101,7 @@ extern "C" {
 /** TIMG_T0LO_REG register
  *  Timer 0 current value, low 32 bits
  */
-#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
+#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
 /** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
  *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
  *
@@ -115,7 +115,7 @@ extern "C" {
 /** TIMG_T0HI_REG register
  *  Timer 0 current value, high 32 bits
  */
-#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
+#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
 /** TIMG_T0_HI : RO; bitpos: [31:0]; default: 0;
  *  After writing to TIMG_T0UPDATE_REG, the high 32 bits of the time-base counter
  *
@@ -129,7 +129,7 @@ extern "C" {
 /** TIMG_T0UPDATE_REG register
  *  Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
  */
-#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
+#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
 /** TIMG_T0_UPDATE : R/W; bitpos: [31]; default: 0;
  *  After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
  */
@@ -141,7 +141,7 @@ extern "C" {
 /** TIMG_T0ALARMLO_REG register
  *  Timer 0 alarm value, low 32 bits
  */
-#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
+#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
 /** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
  *  Timer 0 alarm trigger time-base counter value, low 32 bits.
  */
@@ -153,7 +153,7 @@ extern "C" {
 /** TIMG_T0ALARMHI_REG register
  *  Timer 0 alarm value, high bits
  */
-#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
+#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
 /** TIMG_T0_ALARM_HI : R/W; bitpos: [31:0]; default: 0;
  *
  *
@@ -167,7 +167,7 @@ extern "C" {
 /** TIMG_T0LOADLO_REG register
  *  Timer 0 reload value, low 32 bits
  */
-#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
+#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
 /** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
  *
  *
@@ -183,7 +183,7 @@ extern "C" {
 /** TIMG_T0LOADHI_REG register
  *  Timer 0 reload value, high 32 bits
  */
-#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
+#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
 /** TIMG_T0_LOAD_HI : R/W; bitpos: [31:0]; default: 0;
  *
  *
@@ -199,7 +199,7 @@ extern "C" {
 /** TIMG_T0LOAD_REG register
  *  Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
  */
-#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
+#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
 /** TIMG_T0_LOAD : WO; bitpos: [31:0]; default: 0;
  *
  *
@@ -213,7 +213,7 @@ extern "C" {
 /** TIMG_T1CONFIG_REG register
  *  Timer 1 configuration register
  */
-#define TIMG_T1CONFIG_REG (DR_REG_TIMG_BASE + 0x24)
+#define TIMG_T1CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x24)
 /** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
  *  1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
  *  clock of timer group.
@@ -279,7 +279,7 @@ extern "C" {
 /** TIMG_T1LO_REG register
  *  Timer 1 current value, low 32 bits
  */
-#define TIMG_T1LO_REG (DR_REG_TIMG_BASE + 0x28)
+#define TIMG_T1LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x28)
 /** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
  *  After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
  *
@@ -293,7 +293,7 @@ extern "C" {
 /** TIMG_T1HI_REG register
  *  Timer 1 current value, high 32 bits
  */
-#define TIMG_T1HI_REG (DR_REG_TIMG_BASE + 0x2c)
+#define TIMG_T1HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x2c)
 /** TIMG_T0_HI : RO; bitpos: [31:0]; default: 0;
  *  After writing to TIMG_T1UPDATE_REG, the high 32 bits of the time-base counter
  *
@@ -307,7 +307,7 @@ extern "C" {
 /** TIMG_T1UPDATE_REG register
  *  Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
  */
-#define TIMG_T1UPDATE_REG (DR_REG_TIMG_BASE + 0x30)
+#define TIMG_T1UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0x30)
 /** TIMG_T0_UPDATE : R/W; bitpos: [31]; default: 0;
  *  After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
  */
@@ -319,7 +319,7 @@ extern "C" {
 /** TIMG_T1ALARMLO_REG register
  *  Timer 1 alarm value, low 32 bits
  */
-#define TIMG_T1ALARMLO_REG (DR_REG_TIMG_BASE + 0x34)
+#define TIMG_T1ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x34)
 /** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
  *  Timer 1 alarm trigger time-base counter value, low 32 bits.
  */
@@ -331,7 +331,7 @@ extern "C" {
 /** TIMG_T1ALARMHI_REG register
  *  Timer 1 alarm value, high bits
  */
-#define TIMG_T1ALARMHI_REG (DR_REG_TIMG_BASE + 0x38)
+#define TIMG_T1ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x38)
 /** TIMG_T0_ALARM_HI : R/W; bitpos: [31:0]; default: 0;
  *
  *
@@ -345,7 +345,7 @@ extern "C" {
 /** TIMG_T1LOADLO_REG register
  *  Timer 1 reload value, low 32 bits
  */
-#define TIMG_T1LOADLO_REG (DR_REG_TIMG_BASE + 0x3c)
+#define TIMG_T1LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x3c)
 /** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
  *
  *
@@ -361,7 +361,7 @@ extern "C" {
 /** TIMG_T1LOADHI_REG register
  *  Timer 1 reload value, high 32 bits
  */
-#define TIMG_T1LOADHI_REG (DR_REG_TIMG_BASE + 0x40)
+#define TIMG_T1LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x40)
 /** TIMG_T0_LOAD_HI : R/W; bitpos: [31:0]; default: 0;
  *
  *
@@ -377,7 +377,7 @@ extern "C" {
 /** TIMG_T1LOAD_REG register
  *  Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
  */
-#define TIMG_T1LOAD_REG (DR_REG_TIMG_BASE + 0x44)
+#define TIMG_T1LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x44)
 /** TIMG_T0_LOAD : WO; bitpos: [31:0]; default: 0;
  *
  *
@@ -391,7 +391,7 @@ extern "C" {
 /** TIMG_WDTCONFIG0_REG register
  *  Watchdog timer configuration register
  */
-#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
+#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
 /** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
  *  Reserved
  */
@@ -492,7 +492,7 @@ extern "C" {
 /** TIMG_WDTCONFIG1_REG register
  *  Watchdog timer prescaler register
  */
-#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
+#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
 /** TIMG_WDT_CLK_PRESCALER : R/W; bitpos: [31:16]; default: 1;
  *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
  *
@@ -506,7 +506,7 @@ extern "C" {
 /** TIMG_WDTCONFIG2_REG register
  *  Watchdog timer stage 0 timeout value
  */
-#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
+#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
 /** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
  *  Stage 0 timeout value, in MWDT clock cycles.
  */
@@ -518,7 +518,7 @@ extern "C" {
 /** TIMG_WDTCONFIG3_REG register
  *  Watchdog timer stage 1 timeout value
  */
-#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
+#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
 /** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
  *  Stage 1 timeout value, in MWDT clock cycles.
  */
@@ -530,7 +530,7 @@ extern "C" {
 /** TIMG_WDTCONFIG4_REG register
  *  Watchdog timer stage 2 timeout value
  */
-#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
+#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
 /** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
  *  Stage 2 timeout value, in MWDT clock cycles.
  */
@@ -542,7 +542,7 @@ extern "C" {
 /** TIMG_WDTCONFIG5_REG register
  *  Watchdog timer stage 3 timeout value
  */
-#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
+#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
 /** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
  *  Stage 3 timeout value, in MWDT clock cycles.
  */
@@ -554,7 +554,7 @@ extern "C" {
 /** TIMG_WDTFEED_REG register
  *  Write to feed the watchdog timer
  */
-#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
+#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
 /** TIMG_WDT_FEED : WO; bitpos: [31:0]; default: 0;
  *  Write any value to feed the MWDT. (WO)
  */
@@ -566,7 +566,7 @@ extern "C" {
 /** TIMG_WDTWPROTECT_REG register
  *  Watchdog write protect register
  */
-#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
+#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
 /** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
  *  If the register contains a different value than its reset value, write
  *
@@ -639,7 +639,7 @@ extern "C" {
 /** TIMG_LACTCONFIG_REG register
  *  LACT configuration register
  */
-#define TIMG_LACTCONFIG_REG (DR_REG_TIMG_BASE + 0x70)
+#define TIMG_LACTCONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
 /** TIMG_LACT_USE_REFTICK : R/W; bitpos: [6]; default: 0;
  *  Reserved
  */
@@ -721,7 +721,7 @@ extern "C" {
 /** TIMG_LACTRTC_REG register
  *  LACT RTC register
  */
-#define TIMG_LACTRTC_REG (DR_REG_TIMG_BASE + 0x74)
+#define TIMG_LACTRTC_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
 /** TIMG_LACT_RTC_STEP_LEN : R/W; bitpos: [31:6]; default: 0;
  *  Reserved
  */
@@ -733,7 +733,7 @@ extern "C" {
 /** TIMG_LACTLO_REG register
  *  LACT low register
  */
-#define TIMG_LACTLO_REG (DR_REG_TIMG_BASE + 0x78)
+#define TIMG_LACTLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
 /** TIMG_LACT_LO : RO; bitpos: [31:0]; default: 0;
  *  Reserved
  */
@@ -745,7 +745,7 @@ extern "C" {
 /** TIMG_LACTHI_REG register
  *  LACT high register
  */
-#define TIMG_LACTHI_REG (DR_REG_TIMG_BASE + 0x7c)
+#define TIMG_LACTHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
 /** TIMG_LACT_HI : RO; bitpos: [31:0]; default: 0;
  *  Reserved
  */
@@ -757,7 +757,7 @@ extern "C" {
 /** TIMG_LACTUPDATE_REG register
  *  LACT update register
  */
-#define TIMG_LACTUPDATE_REG (DR_REG_TIMG_BASE + 0x80)
+#define TIMG_LACTUPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
 /** TIMG_LACT_UPDATE : WO; bitpos: [31:0]; default: 0;
  *  Reserved
  */
@@ -769,7 +769,7 @@ extern "C" {
 /** TIMG_LACTALARMLO_REG register
  *  LACT alarm low register
  */
-#define TIMG_LACTALARMLO_REG (DR_REG_TIMG_BASE + 0x84)
+#define TIMG_LACTALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x84)
 /** TIMG_LACT_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
  *  Reserved
  */
@@ -781,7 +781,7 @@ extern "C" {
 /** TIMG_LACTALARMHI_REG register
  *  LACT alarm high register
  */
-#define TIMG_LACTALARMHI_REG (DR_REG_TIMG_BASE + 0x88)
+#define TIMG_LACTALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x88)
 /** TIMG_LACT_ALARM_HI : R/W; bitpos: [31:0]; default: 0;
  *  Reserved
  */
@@ -793,7 +793,7 @@ extern "C" {
 /** TIMG_LACTLOADLO_REG register
  *  LACT load low register
  */
-#define TIMG_LACTLOADLO_REG (DR_REG_TIMG_BASE + 0x8c)
+#define TIMG_LACTLOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x8c)
 /** TIMG_LACT_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
  *  Reserved
  */
@@ -805,7 +805,7 @@ extern "C" {
 /** TIMG_LACTLOADHI_REG register
  *  Timer LACT load high register
  */
-#define TIMG_LACTLOADHI_REG (DR_REG_TIMG_BASE + 0x90)
+#define TIMG_LACTLOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x90)
 /** TIMG_LACT_LOAD_HI : R/W; bitpos: [31:0]; default: 0;
  *  Reserved
  */
@@ -817,7 +817,7 @@ extern "C" {
 /** TIMG_LACTLOAD_REG register
  *  Timer LACT load register
  */
-#define TIMG_LACTLOAD_REG (DR_REG_TIMG_BASE + 0x94)
+#define TIMG_LACTLOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x94)
 /** TIMG_LACT_LOAD : WO; bitpos: [31:0]; default: 0;
  *  Reserved
  */
@@ -829,7 +829,7 @@ extern "C" {
 /** TIMG_INT_ENA_TIMERS_REG register
  *  Interrupt enable bits
  */
-#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x98)
+#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x98)
 /** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  The interrupt enable bit for the TIMG_T0_INT interrupt.
  */
@@ -862,7 +862,7 @@ extern "C" {
 /** TIMG_INT_RAW_TIMERS_REG register
  *  Raw interrupt status
  */
-#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x9c)
+#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x9c)
 /** TIMG_T0_INT_RAW : RO; bitpos: [0]; default: 0;
  *  The raw interrupt status bit for the TIMG_T0_INT interrupt.
  */
@@ -895,7 +895,7 @@ extern "C" {
 /** TIMG_INT_ST_TIMERS_REG register
  *  Masked interrupt status
  */
-#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0xa0)
+#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0xa0)
 /** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
  *  The masked interrupt status bit for the TIMG_T0_INT interrupt.
  */
@@ -928,7 +928,7 @@ extern "C" {
 /** TIMG_INT_CLR_TIMERS_REG register
  *  Interrupt clear bits
  */
-#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0xa4)
+#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0xa4)
 /** TIMG_T0_INT_CLR : WO; bitpos: [0]; default: 0;
  *  Set this bit to clear the TIMG_T0_INT interrupt.
  */
@@ -988,7 +988,7 @@ extern "C" {
 /** TIMG_TIMERS_DATE_REG register
  *  Version control register
  */
-#define TIMG_TIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
+#define TIMG_TIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
 /** TIMG_TIMERS_DATE : R/W; bitpos: [27:0]; default: 26243681;
  *  Version control register.
  */
@@ -1000,7 +1000,7 @@ extern "C" {
 /** TIMG_REGCLK_REG register
  *  Timer group clock gate register
  */
-#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
+#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
 /** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
  *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
  *  Registers can not be read or written to by software.