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esp32h2: fixes after rebase

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This commit is contained in:
Shu Chen 2021-06-18 19:20:42 +08:00
parent 15a907da48
commit 2df4ddf998
9 changed files with 28 additions and 35 deletions
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2
components/bootloader/subproject/main/ld/esp32h2/bootloader.ld
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@ -170,7 +170,7 @@ SECTIONS
}
/* ESP32H2-TODO: IDF-3466 */
/**
* Appendix: Memory Usage of ROM bootloader
*

14
components/bootloader_support/src/flash_encrypt.c
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@ -86,10 +86,7 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
uint8_t dis_dl_enc = 0;
uint8_t dis_dl_icache = 0;
uint8_t dis_dl_dcache = 0;
#elif CONFIG_IDF_TARGET_ESP32C3
uint8_t dis_dl_enc = 0;
uint8_t dis_dl_icache = 0;
#elif CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
uint8_t dis_dl_enc = 0;
uint8_t dis_dl_icache = 0;
#endif
@ -126,14 +123,7 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
if (dis_dl_enc && dis_dl_icache && dis_dl_dcache) {
mode = ESP_FLASH_ENC_MODE_RELEASE;
}
#elif CONFIG_IDF_TARGET_ESP32C3
dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
if (dis_dl_enc && dis_dl_icache) {
mode = ESP_FLASH_ENC_MODE_RELEASE;
}
#elif CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);

2
components/efuse/esp32h2/esp_efuse_utility.c
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@ -75,7 +75,7 @@ void esp_efuse_utility_clear_program_registers(void)
}
// Burn values written to the efuse write registers
void esp_efuse_utility_burn_efuses(void)
void esp_efuse_utility_burn_chip(void)
{
#ifdef CONFIG_EFUSE_VIRTUAL
ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");

5
components/hal/esp32h2/include/hal/memprot_ll.h
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@ -16,6 +16,7 @@
#include "soc/sensitive_reg.h"
#include "soc/cache_memory.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
@ -96,7 +97,7 @@ static inline uint32_t memprot_ll_iram0_get_intr_source_num(void)
static inline void memprot_ll_set_iram0_split_line(const void *line_addr, uint32_t sensitive_reg)
{
uint32_t addr = (uint32_t)line_addr;
assert( addr >= IRAM0_SRAM_LEVEL_1_LOW && addr <= IRAM0_SRAM_LEVEL_3_HIGH );
HAL_ASSERT( addr >= IRAM0_SRAM_LEVEL_1_LOW && addr <= IRAM0_SRAM_LEVEL_3_HIGH );
uint32_t category[3] = {0};
if (addr <= IRAM0_SRAM_LEVEL_1_HIGH) {
@ -353,7 +354,7 @@ static inline uint32_t memprot_ll_dram0_get_intr_source_num(void)
static inline void memprot_ll_set_dram0_split_line(const void *line_addr, uint32_t sensitive_reg)
{
uint32_t addr = (uint32_t)line_addr;
assert( addr >= DRAM0_SRAM_LEVEL_1_LOW && addr <= DRAM0_SRAM_LEVEL_3_HIGH );
HAL_ASSERT( addr >= DRAM0_SRAM_LEVEL_1_LOW && addr <= DRAM0_SRAM_LEVEL_3_HIGH );
uint32_t category[3] = {0};
if (addr <= DRAM0_SRAM_LEVEL_1_HIGH) {

4
components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h
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@ -20,11 +20,11 @@
// The Lowlevel layer for SPI Flash Encryption.
#include "hal/assert.h"
#include "soc/system_reg.h"
#include "soc/hwcrypto_reg.h"
#include "soc/soc.h"
#include "string.h"
#include "assert.h"
#include <stdbool.h>
#ifdef __cplusplus
@ -67,7 +67,7 @@ static inline void spi_flash_encrypt_ll_disable(void)
static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
{
// Our hardware only support flash encryption
assert(type == FLASH_ENCRYPTION_MANU);
HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
REG_WRITE(AES_XTS_DESTINATION_REG, type);
}

15
components/hal/esp32h2/include/hal/spi_ll.h
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@ -24,11 +24,12 @@
#include <stdlib.h> //for abs()
#include <string.h>
#include "hal/hal_defs.h"
#include "esp_attr.h"
#include "esp_types.h"
#include "soc/spi_periph.h"
#include "esp32h2/rom/lldesc.h"
#include "esp_attr.h"
#include "soc/lldesc.h"
#include "hal/assert.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@ -37,7 +38,7 @@ extern "C" {
/// Interrupt not used. Don't use in app.
#define SPI_LL_UNUSED_INT_MASK (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
/// Swap the bit order to its correct place to send
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
/// This is the expected clock frequency
#define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):&GPSPI2)
@ -351,9 +352,9 @@ static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_s
*/
static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *data, int len)
{
assert(byte_id+len <= 64);
assert(len > 0);
assert(byte_id >= 0);
HAL_ASSERT(byte_id+len <= 64);
HAL_ASSERT(len > 0);
HAL_ASSERT(byte_id >= 0);
while (len > 0) {
uint32_t word;

4
components/hal/esp32h2/include/hal/systimer_ll.h
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@ -15,8 +15,8 @@
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include "soc/systimer_struct.h"
#include "hal/assert.h"
#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time
#define SYSTIMER_LL_COUNTER_OS_TICK (1) // Counter used for OS tick
@ -120,7 +120,7 @@ __attribute__((always_inline)) static inline void systimer_ll_enable_alarm_perio
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
{
assert(period < (1 << 26));
HAL_ASSERT(period < (1 << 26));
dev->target_conf[alarm_id].target_period = period;
}

5
components/hal/esp32h2/include/hal/timer_ll.h
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@ -22,8 +22,9 @@ extern "C" {
#endif
#include <stdlib.h>
#include "hal/timer_types.h"
#include "soc/timer_periph.h"
#include "hal/timer_types.h"
#include "hal/assert.h"
_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
_Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
@ -47,7 +48,7 @@ typedef struct {
*/
static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider)
{
assert(divider >= 2 && divider <= 65536);
HAL_ASSERT(divider >= 2 && divider <= 65536);
if (divider >= 65536) {
divider = 0;
}

12
components/hal/esp32h2/rtc_cntl_hal.c
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@ -14,10 +14,10 @@
// The HAL layer for RTC CNTL (common part)
#include "hal/rtc_hal.h"
#include "soc/soc_caps.h"
#include "esp32h2/rom/lldesc.h"
#include "esp_attr.h"
#include "soc/lldesc.h"
#include "hal/rtc_hal.h"
#include "hal/assert.h"
#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */
@ -27,9 +27,9 @@ typedef struct rtc_cntl_link_buf_conf {
void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next)
{
assert(elem != NULL);
assert(buff != NULL);
assert(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
HAL_ASSERT(elem != NULL);
HAL_ASSERT(buff != NULL);
HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
lldesc_t *plink = (lldesc_t *)elem;