mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
Merge branch 'feature/usb_serial_jtag_s3' into 'master'
usb_serial_jtag: add initial support for S3 (no stub support) See merge request espressif/esp-idf!13890
This commit is contained in:
Michael (XIAO Xufeng)
commit
2d5f3a4825
@ -20,6 +20,8 @@
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/ets_sys.h"
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#include "esp32c3/rom/uart.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/uart.h"
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#endif
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#include "esp_rom_gpio.h"
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#include "esp_rom_uart.h"
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@ -36,6 +36,6 @@ PROVIDE ( UART2 = 0x6002E000 );
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PROVIDE ( DMA = 0x6003F000 );
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PROVIDE ( APB_SARADC = 0x60040000 );
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PROVIDE ( LCD_CAM = 0x60041000 );
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PROVIDE ( USB0 = 0x60080000 );
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PROVIDE ( USB_SERIAL_JTAG = 0x60038000 );
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PROVIDE ( USBH = 0x60080000 );
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PROVIDE ( USB_WRAP = 0x60039000 );
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@ -20,3 +20,4 @@
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#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging
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#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM
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#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking
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#define ESP_ROM_USB_SERIAL_DEVICE_NUM (4) // The serial port ID (UART, USB, ...) of USB_SERIAL_JTAG in the ROM.
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@ -192,7 +192,9 @@ menu "ESP System Settings"
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depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !USB_ENABLED
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config ESP_CONSOLE_USB_SERIAL_JTAG
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bool "USB Serial/JTAG Controller"
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depends on IDF_TARGET_ESP32C3
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select ESPTOOLPY_NO_STUB if IDF_TARGET_ESP32S3 #ESPTOOL-251
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select ESPTOOLPY_NO_STUB if IDF_TARGET_ESP32C3 #ESPTOOL-252
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depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
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config ESP_CONSOLE_UART_CUSTOM
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bool "Custom UART"
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config ESP_CONSOLE_NONE
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169
components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h
Normal file
169
components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h
Normal file
@ -0,0 +1,169 @@
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// Copyright 2021 Espressif Systems (Shanghai)
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// The LL layer of the USB-serial-jtag controller
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#pragma once
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#include "soc/usb_serial_jtag_reg.h"
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#include "soc/usb_serial_jtag_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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//The in and out endpoints are this long.
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#define USB_SERIAL_JTAG_PACKET_SZ_BYTES 64
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#define USB_SERIAL_JTAG_LL_INTR_MASK (0x7ffff) //All interrupt mask
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// Define USB_SERIAL_JTAG interrupts
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// Note the hardware has more interrupts, but they're only useful for debugging
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// the hardware.
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typedef enum {
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USB_SERIAL_JTAG_INTR_SOF = (1 << 1),
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USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT = (1 << 2),
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USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY = (1 << 3),
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USB_SERIAL_JTAG_INTR_TOKEN_REC_IN_EP1 = (1 << 8),
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USB_SERIAL_JTAG_INTR_BUS_RESET = (1 << 9),
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USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD = (1 << 10),
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} usb_serial_jtag_intr_t;
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/**
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* @brief Enable the USB_SERIAL_JTAG interrupt based on the given mask.
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*
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* @param mask The bitmap of the interrupts need to be enabled.
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*
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* @return None
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*/
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static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask)
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{
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USB_SERIAL_JTAG.int_ena.val |= mask;
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}
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/**
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* @brief Disable the USB_SERIAL_JTAG interrupt based on the given mask.
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*
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* @param mask The bitmap of the interrupts need to be disabled.
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*
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* @return None
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*/
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static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask)
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{
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USB_SERIAL_JTAG.int_ena.val &= (~mask);
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}
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/**
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* @brief Get the USB_SERIAL_JTAG interrupt status.
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*
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* @return The USB_SERIAL_JTAG interrupt status.
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*/
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static inline uint32_t usb_serial_jtag_ll_get_intsts_mask(void)
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{
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return USB_SERIAL_JTAG.int_st.val;
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}
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/**
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* @brief Clear the USB_SERIAL_JTAG interrupt status based on the given mask.
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*
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* @param mask The bitmap of the interrupts need to be cleared.
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*
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* @return None
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*/
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static inline void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask)
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{
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USB_SERIAL_JTAG.int_clr.val = mask;
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}
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/**
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* @brief Get status of enabled interrupt.
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*
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* @return interrupt enable value
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*/
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static inline uint32_t usb_serial_jtag_ll_get_intr_ena_status(void)
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{
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return USB_SERIAL_JTAG.int_ena.val;
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}
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/**
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* @brief Read the bytes from the USB_SERIAL_JTAG rxfifo.
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*
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* @param buf The data buffer.
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* @param rd_len The data length needs to be read.
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*
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* @return amount of bytes read
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*/
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static inline uint32_t usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
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{
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uint32_t i;
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for (i = 0; i < rd_len; i++) {
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if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
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buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
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}
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return i;
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}
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/**
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* @brief Write byte to the USB_SERIAL_JTAG txfifo. Only writes bytes as long / if there
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* is room in the buffer.
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*
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* @param buf The data buffer.
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* @param wr_len The data length needs to be writen.
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*
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* @return Amount of bytes actually written. May be less than wr_len.
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*/
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static inline uint32_t usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t wr_len)
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{
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uint32_t i;
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for (i = 0; i < wr_len; i++) {
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if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
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USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
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}
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return i;
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}
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/**
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* @brief Returns 1 if the USB_SERIAL_JTAG rxfifo has data available.
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*
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* @return 0 if no data available, 1 if data available
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*/
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static inline int usb_serial_jtag_ll_rxfifo_data_available(void)
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{
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return USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail;
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}
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/**
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* @brief Returns 1 if the USB_SERIAL_JTAG txfifo has room.
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*
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* @return 0 if no data available, 1 if data available
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*/
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static inline int usb_serial_jtag_ll_txfifo_writable(void)
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{
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return USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free;
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}
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/**
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* @brief Flushes the TX buffer, that is, make it available for the
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* host to pick up.
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*
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* @return na
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*/
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static inline void usb_serial_jtag_ll_txfifo_flush(void)
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{
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USB_SERIAL_JTAG.ep1_conf.wr_done=1;
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}
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#ifdef __cplusplus
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}
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#endif
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745
components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h
Normal file
745
components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h
Normal file
@ -0,0 +1,745 @@
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_USB_DEVICE_REG_H_
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#define _SOC_USB_DEVICE_REG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "soc.h"
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#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0)
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/* USB_SERIAL_JTAG_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
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/*description: Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DE
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VICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into
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UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB
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_DEVICE_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is rece
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ived, then read data from UART Rx FIFO..*/
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#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FF
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#define USB_SERIAL_JTAG_RDWR_BYTE_M ((USB_DEVICE_RDWR_BYTE_V)<<(USB_DEVICE_RDWR_BYTE_S))
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#define USB_SERIAL_JTAG_RDWR_BYTE_V 0xFF
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#define USB_SERIAL_JTAG_RDWR_BYTE_S 0
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#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4)
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/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO ;bitpos:[2] ;default: 1'b0 ; */
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/*description: 1'b1: Indicate there is data in UART Rx FIFO..*/
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#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2))
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#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (BIT(2))
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#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x1
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#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
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/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */
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/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writin
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g USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
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USB Host..*/
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#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1))
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#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (BIT(1))
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#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x1
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#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1
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/* USB_SERIAL_JTAG_WR_DONE : WT ;bitpos:[0] ;default: 1'b0 ; */
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/*description: Set this bit to indicate writing byte data to UART Tx FIFO is done..*/
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#define USB_SERIAL_JTAG_WR_DONE (BIT(0))
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#define USB_SERIAL_JTAG_WR_DONE_M (BIT(0))
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#define USB_SERIAL_JTAG_WR_DONE_V 0x1
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#define USB_SERIAL_JTAG_WR_DONE_S 0
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#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8)
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/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
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/*description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet wi
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th zero palyload..*/
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#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11))
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#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (BIT(11))
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#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x1
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#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
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/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
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/*description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet wi
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||||
th zero palyload..*/
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#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10))
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#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (BIT(10))
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#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x1
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#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10
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/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
|
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/*description: The raw interrupt bit turns to high level when usb bus reset is detected..*/
|
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#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9))
|
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#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (BIT(9))
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#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x1
|
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#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9
|
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/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is rec
|
||||
eived..*/
|
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#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8))
|
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#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (BIT(8))
|
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#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x1
|
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#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8
|
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/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when stuff error is detected..*/
|
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#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7))
|
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#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (BIT(7))
|
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#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x1
|
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#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7
|
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/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when CRC16 error is detected..*/
|
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#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6))
|
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#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (BIT(6))
|
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#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x1
|
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#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when CRC5 error is detected..*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (BIT(5))
|
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#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5
|
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/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when pid error is detected..*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (BIT(3))
|
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#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3
|
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/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
|
||||
one packet..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (BIT(2))
|
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#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x1
|
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#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2
|
||||
/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when SOF frame is received..*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1))
|
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#define USB_SERIAL_JTAG_SOF_INT_RAW_M (BIT(1))
|
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#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x1
|
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#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1
|
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/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when flush cmd is received for IN endp
|
||||
oint 2 of JTAG..*/
|
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#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xC)
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interru
|
||||
pt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interru
|
||||
pt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10
|
||||
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9
|
||||
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrup
|
||||
t..*/
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8
|
||||
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7
|
||||
/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5
|
||||
/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrup
|
||||
t..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2
|
||||
/* USB_SERIAL_JTAG_SOF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST_S 1
|
||||
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10)
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10
|
||||
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9
|
||||
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8
|
||||
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7
|
||||
/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5
|
||||
/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2
|
||||
/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1
|
||||
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14)
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10
|
||||
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9
|
||||
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8
|
||||
/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7
|
||||
/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5
|
||||
/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2
|
||||
/* USB_SERIAL_JTAG_SOF_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1
|
||||
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18)
|
||||
/* USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
|
||||
/*description: Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disc
|
||||
onnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input thr
|
||||
ough GPIO Matrix..*/
|
||||
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(16))
|
||||
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (BIT(16))
|
||||
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 16
|
||||
/* USB_SERIAL_JTAG_PHY_TX_EDGE_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: 0: TX output at clock negedge. 1: Tx output at clock posedge..*/
|
||||
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL (BIT(15))
|
||||
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_M (BIT(15))
|
||||
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_V 0x1
|
||||
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_S 15
|
||||
/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W ;bitpos:[14] ;default: 1'b1 ; */
|
||||
/*description: Enable USB pad function..*/
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14))
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (BIT(14))
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14
|
||||
/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W ;bitpos:[13] ;default: 1'b0 ; */
|
||||
/*description: Control pull up value..*/
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13))
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE_M (BIT(13))
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x1
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13
|
||||
/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: Control USB D- pull down..*/
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12))
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN_M (BIT(12))
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x1
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12
|
||||
/* USB_SERIAL_JTAG_DM_PULLUP : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: Control USB D- pull up..*/
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11))
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP_M (BIT(11))
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP_V 0x1
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP_S 11
|
||||
/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: Control USB D+ pull down..*/
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10))
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN_M (BIT(10))
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x1
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10
|
||||
/* USB_SERIAL_JTAG_DP_PULLUP : R/W ;bitpos:[9] ;default: 1'b1 ; */
|
||||
/*description: Control USB D+ pull up..*/
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9))
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP_M (BIT(9))
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP_V 0x1
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP_S 9
|
||||
/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: Enable software control USB D+ D- pullup pulldown.*/
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8))
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (BIT(8))
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x1
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8
|
||||
/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: Enable software control input threshold.*/
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7))
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (BIT(7))
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x1
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7
|
||||
/* USB_SERIAL_JTAG_VREFL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
|
||||
/*description: Control single-end input low threshold,0.8V to 1.04V, step 80mV.*/
|
||||
#define USB_SERIAL_JTAG_VREFL 0x00000003
|
||||
#define USB_SERIAL_JTAG_VREFL_M ((USB_DEVICE_VREFL_V)<<(USB_DEVICE_VREFL_S))
|
||||
#define USB_SERIAL_JTAG_VREFL_V 0x3
|
||||
#define USB_SERIAL_JTAG_VREFL_S 5
|
||||
/* USB_SERIAL_JTAG_VREFH : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
|
||||
/*description: Control single-end input high threshold,1.76V to 2V, step 80mV.*/
|
||||
#define USB_SERIAL_JTAG_VREFH 0x00000003
|
||||
#define USB_SERIAL_JTAG_VREFH_M ((USB_DEVICE_VREFH_V)<<(USB_DEVICE_VREFH_S))
|
||||
#define USB_SERIAL_JTAG_VREFH_V 0x3
|
||||
#define USB_SERIAL_JTAG_VREFH_S 3
|
||||
/* USB_SERIAL_JTAG_EXCHG_PINS : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: USB D+ D- exchange.*/
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2))
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x1
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_S 2
|
||||
/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Enable software control USB D+ D- exchange.*/
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1))
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x1
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1
|
||||
/* USB_SERIAL_JTAG_PHY_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Select internal/external PHY.*/
|
||||
#define USB_SERIAL_JTAG_PHY_SEL (BIT(0))
|
||||
#define USB_SERIAL_JTAG_PHY_SEL_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_PHY_SEL_V 0x1
|
||||
#define USB_SERIAL_JTAG_PHY_SEL_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1C)
|
||||
/* USB_SERIAL_JTAG_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: USB D- rx value in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DM_M (BIT(6))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DM_S 6
|
||||
/* USB_SERIAL_JTAG_TEST_RX_DP : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: USB D+ rx value in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DP_M (BIT(5))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DP_S 5
|
||||
/* USB_SERIAL_JTAG_TEST_RX_RCV : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: USB differential rx value in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_RCV_M (BIT(4))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4
|
||||
/* USB_SERIAL_JTAG_TEST_TX_DM : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: USB D- tx value in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3))
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM_M (BIT(3))
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM_S 3
|
||||
/* USB_SERIAL_JTAG_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: USB D+ tx value in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2))
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP_S 2
|
||||
/* USB_SERIAL_JTAG_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: USB pad oen in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1))
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE_S 1
|
||||
/* USB_SERIAL_JTAG_TEST_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Enable test of the USB pad.*/
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0))
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20)
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: Write 1 to reset JTAG out fifo..*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (BIT(9))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: Write 1 to reset JTAG in fifo..*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: 1: JTAG out fifo is full..*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (BIT(7))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: 1: JTAG out fifo is empty..*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (BIT(6))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO ;bitpos:[5:4] ;default: 2'd0 ; */
|
||||
/*description: JTAT out fifo counter..*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M ((USB_DEVICE_OUT_FIFO_CNT_V)<<(USB_DEVICE_OUT_FIFO_CNT_S))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x3
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: 1: JTAG in fifo is full..*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (BIT(3))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: 1: JTAG in fifo is empty..*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO ;bitpos:[1:0] ;default: 2'd0 ; */
|
||||
/*description: JTAT in fifo counter..*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT_M ((USB_DEVICE_IN_FIFO_CNT_V)<<(USB_DEVICE_IN_FIFO_CNT_S))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x3
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24)
|
||||
/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO ;bitpos:[10:0] ;default: 11'd0 ; */
|
||||
/*description: Frame index of received SOF frame..*/
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FF
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M ((USB_DEVICE_SOF_FRAME_INDEX_V)<<(USB_DEVICE_SOF_FRAME_INDEX_S))
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x7FF
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28)
|
||||
/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of IN endpoint 0..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M ((USB_DEVICE_IN_EP0_RD_ADDR_V)<<(USB_DEVICE_IN_EP0_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of IN endpoint 0..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M ((USB_DEVICE_IN_EP0_WR_ADDR_V)<<(USB_DEVICE_IN_EP0_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
|
||||
/*description: State of IN Endpoint 0..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE_M ((USB_DEVICE_IN_EP0_STATE_V)<<(USB_DEVICE_IN_EP0_STATE_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2C)
|
||||
/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of IN endpoint 1..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M ((USB_DEVICE_IN_EP1_RD_ADDR_V)<<(USB_DEVICE_IN_EP1_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of IN endpoint 1..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M ((USB_DEVICE_IN_EP1_WR_ADDR_V)<<(USB_DEVICE_IN_EP1_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
|
||||
/*description: State of IN Endpoint 1..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE_M ((USB_DEVICE_IN_EP1_STATE_V)<<(USB_DEVICE_IN_EP1_STATE_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30)
|
||||
/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of IN endpoint 2..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M ((USB_DEVICE_IN_EP2_RD_ADDR_V)<<(USB_DEVICE_IN_EP2_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of IN endpoint 2..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M ((USB_DEVICE_IN_EP2_WR_ADDR_V)<<(USB_DEVICE_IN_EP2_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
|
||||
/*description: State of IN Endpoint 2..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE_M ((USB_DEVICE_IN_EP2_STATE_V)<<(USB_DEVICE_IN_EP2_STATE_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34)
|
||||
/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of IN endpoint 3..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M ((USB_DEVICE_IN_EP3_RD_ADDR_V)<<(USB_DEVICE_IN_EP3_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of IN endpoint 3..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M ((USB_DEVICE_IN_EP3_WR_ADDR_V)<<(USB_DEVICE_IN_EP3_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP3_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
|
||||
/*description: State of IN Endpoint 3..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE_M ((USB_DEVICE_IN_EP3_STATE_V)<<(USB_DEVICE_IN_EP3_STATE_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38)
|
||||
/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of OUT endpoint 0..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M ((USB_DEVICE_OUT_EP0_RD_ADDR_V)<<(USB_DEVICE_OUT_EP0_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
|
||||
detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M ((USB_DEVICE_OUT_EP0_WR_ADDR_V)<<(USB_DEVICE_OUT_EP0_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: State of OUT Endpoint 0..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE_M ((USB_DEVICE_OUT_EP0_STATE_V)<<(USB_DEVICE_OUT_EP0_STATE_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3C)
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO ;bitpos:[22:16] ;default: 7'd0 ; */
|
||||
/*description: Data count in OUT endpoint 1 when one packet is received..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M ((USB_DEVICE_OUT_EP1_REC_DATA_CNT_V)<<(USB_DEVICE_OUT_EP1_REC_DATA_CNT_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of OUT endpoint 1..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M ((USB_DEVICE_OUT_EP1_RD_ADDR_V)<<(USB_DEVICE_OUT_EP1_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
|
||||
detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M ((USB_DEVICE_OUT_EP1_WR_ADDR_V)<<(USB_DEVICE_OUT_EP1_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: State of OUT Endpoint 1..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE_M ((USB_DEVICE_OUT_EP1_STATE_V)<<(USB_DEVICE_OUT_EP1_STATE_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40)
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of OUT endpoint 2..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M ((USB_DEVICE_OUT_EP2_RD_ADDR_V)<<(USB_DEVICE_OUT_EP2_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
|
||||
detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M ((USB_DEVICE_OUT_EP2_WR_ADDR_V)<<(USB_DEVICE_OUT_EP2_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: State of OUT Endpoint 2..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE_M ((USB_DEVICE_OUT_EP2_STATE_V)<<(USB_DEVICE_OUT_EP2_STATE_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44)
|
||||
/* USB_SERIAL_JTAG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri
|
||||
tes registers..*/
|
||||
#define USB_SERIAL_JTAG_CLK_EN (BIT(0))
|
||||
#define USB_SERIAL_JTAG_CLK_EN_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_CLK_EN_V 0x1
|
||||
#define USB_SERIAL_JTAG_CLK_EN_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48)
|
||||
/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: 1: Force clock on for usb memory..*/
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1))
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1
|
||||
/* USB_SERIAL_JTAG_USB_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: 1: power down usb memory..*/
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0))
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80)
|
||||
/* USB_SERIAL_JTAG_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101200 ; */
|
||||
/*description: register version..*/
|
||||
#define USB_SERIAL_JTAG_DATE 0xFFFFFFFF
|
||||
#define USB_SERIAL_JTAG_DATE_M ((USB_DEVICE_DATE_V)<<(USB_DEVICE_DATE_S))
|
||||
#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFF
|
||||
#define USB_SERIAL_JTAG_DATE_S 0
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_USB_DEVICE_REG_H_ */
|
||||
267
components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
Normal file
267
components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
Normal file
@ -0,0 +1,267 @@
|
||||
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
|
||||
#define _SOC_USB_SERIAL_JTAG_STRUCT_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t rdwr_byte : 32; /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ep1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wr_done : 1; /*Set this bit to indicate writing byte data to UART Tx FIFO is done.*/
|
||||
uint32_t serial_in_ep_data_free : 1; /*1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.*/
|
||||
uint32_t serial_out_ep_data_avail : 1; /*1'b1: Indicate there is data in UART Rx FIFO.*/
|
||||
uint32_t reserved3 : 29; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ep1_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_raw : 1; /*The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.*/
|
||||
uint32_t sof_int_raw : 1; /*The raw interrupt bit turns to high level when SOF frame is received.*/
|
||||
uint32_t serial_out_recv_pkt_int_raw: 1; /*The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.*/
|
||||
uint32_t serial_in_empty_int_raw : 1; /*The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.*/
|
||||
uint32_t pid_err_int_raw : 1; /*The raw interrupt bit turns to high level when pid error is detected.*/
|
||||
uint32_t crc5_err_int_raw : 1; /*The raw interrupt bit turns to high level when CRC5 error is detected.*/
|
||||
uint32_t crc16_err_int_raw : 1; /*The raw interrupt bit turns to high level when CRC16 error is detected.*/
|
||||
uint32_t stuff_err_int_raw : 1; /*The raw interrupt bit turns to high level when stuff error is detected.*/
|
||||
uint32_t in_token_rec_in_ep1_int_raw: 1; /*The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.*/
|
||||
uint32_t usb_bus_reset_int_raw : 1; /*The raw interrupt bit turns to high level when usb bus reset is detected.*/
|
||||
uint32_t out_ep1_zero_payload_int_raw: 1; /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.*/
|
||||
uint32_t out_ep2_zero_payload_int_raw: 1; /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
|
||||
uint32_t sof_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.*/
|
||||
uint32_t serial_out_recv_pkt_int_st: 1; /*The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
|
||||
uint32_t serial_in_empty_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
|
||||
uint32_t pid_err_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.*/
|
||||
uint32_t crc5_err_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/
|
||||
uint32_t crc16_err_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/
|
||||
uint32_t stuff_err_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/
|
||||
uint32_t in_token_rec_in_ep1_int_st: 1; /*The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
|
||||
uint32_t usb_bus_reset_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
|
||||
uint32_t out_ep1_zero_payload_int_st: 1; /*The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t out_ep2_zero_payload_int_st: 1; /*The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
|
||||
uint32_t sof_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.*/
|
||||
uint32_t serial_out_recv_pkt_int_ena: 1; /*The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
|
||||
uint32_t serial_in_empty_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
|
||||
uint32_t pid_err_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.*/
|
||||
uint32_t crc5_err_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/
|
||||
uint32_t crc16_err_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/
|
||||
uint32_t stuff_err_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/
|
||||
uint32_t in_token_rec_in_ep1_int_ena: 1; /*The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
|
||||
uint32_t usb_bus_reset_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
|
||||
uint32_t out_ep1_zero_payload_int_ena: 1; /*The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t out_ep2_zero_payload_int_ena: 1; /*The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_clr : 1; /*Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
|
||||
uint32_t sof_int_clr : 1; /*Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.*/
|
||||
uint32_t serial_out_recv_pkt_int_clr: 1; /*Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
|
||||
uint32_t serial_in_empty_int_clr : 1; /*Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
|
||||
uint32_t pid_err_int_clr : 1; /*Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.*/
|
||||
uint32_t crc5_err_int_clr : 1; /*Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.*/
|
||||
uint32_t crc16_err_int_clr : 1; /*Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.*/
|
||||
uint32_t stuff_err_int_clr : 1; /*Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.*/
|
||||
uint32_t in_token_rec_in_ep1_int_clr: 1; /*Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.*/
|
||||
uint32_t usb_bus_reset_int_clr : 1; /*Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
|
||||
uint32_t out_ep1_zero_payload_int_clr: 1; /*Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t out_ep2_zero_payload_int_clr: 1; /*Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t phy_sel : 1; /*Select internal/external PHY*/
|
||||
uint32_t exchg_pins_override : 1; /*Enable software control USB D+ D- exchange*/
|
||||
uint32_t exchg_pins : 1; /*USB D+ D- exchange*/
|
||||
uint32_t vrefh : 2; /*Control single-end input high threshold,1.76V to 2V, step 80mV*/
|
||||
uint32_t vrefl : 2; /*Control single-end input low threshold,0.8V to 1.04V, step 80mV*/
|
||||
uint32_t vref_override : 1; /*Enable software control input threshold*/
|
||||
uint32_t pad_pull_override : 1; /*Enable software control USB D+ D- pullup pulldown*/
|
||||
uint32_t dp_pullup : 1; /*Control USB D+ pull up.*/
|
||||
uint32_t dp_pulldown : 1; /*Control USB D+ pull down.*/
|
||||
uint32_t dm_pullup : 1; /*Control USB D- pull up.*/
|
||||
uint32_t dm_pulldown : 1; /*Control USB D- pull down.*/
|
||||
uint32_t pullup_value : 1; /*Control pull up value.*/
|
||||
uint32_t usb_pad_enable : 1; /*Enable USB pad function.*/
|
||||
uint32_t phy_tx_edge_sel : 1; /*0: TX output at clock negedge. 1: Tx output at clock posedge.*/
|
||||
uint32_t usb_jtag_bridge_en : 1; /*Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix.*/
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t test_enable : 1; /*Enable test of the USB pad*/
|
||||
uint32_t test_usb_oe : 1; /*USB pad oen in test*/
|
||||
uint32_t test_tx_dp : 1; /*USB D+ tx value in test*/
|
||||
uint32_t test_tx_dm : 1; /*USB D- tx value in test*/
|
||||
uint32_t test_rx_rcv : 1; /*USB differential rx value in test*/
|
||||
uint32_t test_rx_dp : 1; /*USB D+ rx value in test*/
|
||||
uint32_t test_rx_dm : 1; /*USB D- rx value in test*/
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} test;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_fifo_cnt : 2; /*JTAT in fifo counter.*/
|
||||
uint32_t in_fifo_empty : 1; /*1: JTAG in fifo is empty.*/
|
||||
uint32_t in_fifo_full : 1; /*1: JTAG in fifo is full.*/
|
||||
uint32_t out_fifo_cnt : 2; /*JTAT out fifo counter.*/
|
||||
uint32_t out_fifo_empty : 1; /*1: JTAG out fifo is empty.*/
|
||||
uint32_t out_fifo_full : 1; /*1: JTAG out fifo is full.*/
|
||||
uint32_t in_fifo_reset : 1; /*Write 1 to reset JTAG in fifo.*/
|
||||
uint32_t out_fifo_reset : 1; /*Write 1 to reset JTAG out fifo.*/
|
||||
uint32_t reserved10 : 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} jfifo_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sof_frame_index : 11; /*Frame index of received SOF frame.*/
|
||||
uint32_t reserved11 : 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} fram_num;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep0_state : 2; /*State of IN Endpoint 0.*/
|
||||
uint32_t in_ep0_wr_addr : 7; /*Write data address of IN endpoint 0.*/
|
||||
uint32_t in_ep0_rd_addr : 7; /*Read data address of IN endpoint 0.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep0_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep1_state : 2; /*State of IN Endpoint 1.*/
|
||||
uint32_t in_ep1_wr_addr : 7; /*Write data address of IN endpoint 1.*/
|
||||
uint32_t in_ep1_rd_addr : 7; /*Read data address of IN endpoint 1.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep1_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep2_state : 2; /*State of IN Endpoint 2.*/
|
||||
uint32_t in_ep2_wr_addr : 7; /*Write data address of IN endpoint 2.*/
|
||||
uint32_t in_ep2_rd_addr : 7; /*Read data address of IN endpoint 2.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep2_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep3_state : 2; /*State of IN Endpoint 3.*/
|
||||
uint32_t in_ep3_wr_addr : 7; /*Write data address of IN endpoint 3.*/
|
||||
uint32_t in_ep3_rd_addr : 7; /*Read data address of IN endpoint 3.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep3_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_ep0_state : 2; /*State of OUT Endpoint 0.*/
|
||||
uint32_t out_ep0_wr_addr : 7; /*Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.*/
|
||||
uint32_t out_ep0_rd_addr : 7; /*Read data address of OUT endpoint 0.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_ep0_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_ep1_state : 2; /*State of OUT Endpoint 1.*/
|
||||
uint32_t out_ep1_wr_addr : 7; /*Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/
|
||||
uint32_t out_ep1_rd_addr : 7; /*Read data address of OUT endpoint 1.*/
|
||||
uint32_t out_ep1_rec_data_cnt : 7; /*Data count in OUT endpoint 1 when one packet is received.*/
|
||||
uint32_t reserved23 : 9; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_ep1_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_ep2_state : 2; /*State of OUT Endpoint 2.*/
|
||||
uint32_t out_ep2_wr_addr : 7; /*Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/
|
||||
uint32_t out_ep2_rd_addr : 7; /*Read data address of OUT endpoint 2.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_ep2_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} misc_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usb_mem_pd : 1; /*1: power down usb memory.*/
|
||||
uint32_t usb_mem_clk_en : 1; /*1: Force clock on for usb memory.*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_conf;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t date;
|
||||
} usb_serial_jtag_dev_t;
|
||||
extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_USB_SERIAL_JTAG_STRUCT_H_ */
|
||||
Loading…
Reference in New Issue
Block a user