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feat(lp_io): Add support for ESP32P4

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This commit is contained in:
Song Ruo Jing 2023-09-15 12:56:13 +08:00
parent 46a692fd22
commit 2d458a3f93
32 changed files with 1105 additions and 2330 deletions
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51
components/driver/gpio/include/driver/lp_io.h Normal file
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@ -0,0 +1,51 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc_caps.h"
#include "esp_err.h"
#include "driver/gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_LP_GPIO_MATRIX_SUPPORTED
/**
* @brief Connect a RTC(LP) GPIO input with a peripheral signal, which tagged as input attribute
*
* @note There's no limitation on the number of signals that a RTC(LP) GPIO can connect with
*
* @param gpio_num GPIO number, especially, `LP_GPIO_MATRIX_CONST_ZERO_INPUT` means connect logic 0 to signal
* `LP_GPIO_MATRIX_CONST_ONE_INPUT` means connect logic 1 to signal
* @param signal_idx LP peripheral signal index (tagged as input attribute)
* @param inv Whether the RTC(LP) GPIO input to be inverted or not
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t lp_gpio_connect_in_signal(gpio_num_t gpio_num, uint32_t signal_idx, bool inv);
/**
* @brief Connect a peripheral signal which tagged as output attribute with a RTC(LP) GPIO
*
* @note There's no limitation on the number of RTC(LP) GPIOs that a signal can connect with
*
* @param gpio_num GPIO number
* @param signal_idx LP peripheral signal index (tagged as input attribute), especially, `SIG_LP_GPIO_OUT_IDX` means disconnect RTC(LP) GPIO and other peripherals. Only the RTC GPIO driver can control the output level
* @param out_inv Whether to signal to be inverted or not
* @param oen_inv Whether the output enable control is inverted or not
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t lp_gpio_connect_out_signal(gpio_num_t gpio_num, uint32_t signal_idx, bool out_inv, bool oen_inv);
#endif // SOC_LP_GPIO_MATRIX_SUPPORTED
#ifdef __cplusplus
}
#endif

4
components/driver/gpio/include/driver/rtc_io.h
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@ -107,8 +107,8 @@ esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode);
* @brief RTC GPIO set direction in deep sleep mode or disable sleep status (default).
* In some application scenarios, IO needs to have another states during deep sleep.
*
* NOTE: ESP32 support INPUT_ONLY mode.
* ESP32S2 support INPUT_ONLY, OUTPUT_ONLY, INPUT_OUTPUT mode.
* NOTE: ESP32 supports INPUT_ONLY mode.
* The rest targets support INPUT_ONLY, OUTPUT_ONLY, INPUT_OUTPUT mode.
*
* @param gpio_num GPIO number (e.g. GPIO_NUM_12)
* @param mode GPIO direction

21
components/driver/gpio/rtc_io.c
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@ -12,6 +12,7 @@
#include "freertos/semphr.h"
#include "freertos/timers.h"
#include "driver/rtc_io.h"
#include "driver/lp_io.h"
#include "hal/rtc_io_hal.h"
#include "soc/rtc_io_periph.h"
#include "soc/soc_caps.h"
@ -44,7 +45,7 @@ esp_err_t rtc_gpio_init(gpio_num_t gpio_num)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
RTCIO_ENTER_CRITICAL();
rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_FUNC_RTC);
rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_RTC);
RTCIO_EXIT_CRITICAL();
return ESP_OK;
@ -55,7 +56,7 @@ esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num)
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
RTCIO_ENTER_CRITICAL();
// Select Gpio as Digital Gpio
rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_FUNC_DIGITAL);
rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_DIGITAL);
RTCIO_EXIT_CRITICAL();
return ESP_OK;
@ -170,6 +171,22 @@ esp_err_t rtc_gpio_iomux_func_sel(gpio_num_t gpio_num, int func)
return ESP_OK;
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
esp_err_t lp_gpio_connect_in_signal(gpio_num_t gpio_num, uint32_t signal_idx, bool inv)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "LP_IO number error");
rtcio_hal_matrix_in(rtc_io_number_get(gpio_num), signal_idx, inv);
return ESP_OK;
}
esp_err_t lp_gpio_connect_out_signal(gpio_num_t gpio_num, uint32_t signal_idx, bool out_inv, bool oen_inv)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "LP_IO number error");
rtcio_hal_matrix_out(rtc_io_number_get(gpio_num), signal_idx, out_inv, oen_inv);
return ESP_OK;
}
#endif // SOC_LP_GPIO_MATRIX_SUPPORTED
#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_HOLD_SUPPORTED

112
components/driver/test_apps/gpio/main/test_rtcio.c
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@ -5,6 +5,7 @@
*/
#include <stdio.h>
#include <string.h>
#include "test_rtcio.h"
#include "esp_system.h"
#include "esp_sleep.h"
#include "unity.h"
@ -16,114 +17,7 @@
#include "esp_err.h"
#include "esp_log.h"
#include "soc/rtc_io_periph.h"
#ifdef CONFIG_IDF_TARGET_ESP32
// The input-only rtcio pins do not have pull-up/down resistors (not support pull-up/down)
#define RTCIO_SUPPORT_PU_PD(num) (rtc_io_desc[num].pullup != 0)
#define TEST_GPIO_PIN_COUNT 16
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
// GPIO_NUM_0, //GPIO0 // Workaround: GPIO0 is strap pin, can not be used pullup/pulldown test.
GPIO_NUM_2, //GPIO2
GPIO_NUM_4, //GPIO4
// GPIO_NUM_12, //GPIO12 // Workaround: GPIO12 is strap pin, can not be used pullup/pulldown test.
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
GPIO_NUM_25, //GPIO25
GPIO_NUM_26, //GPIO26
GPIO_NUM_27, //GPIO27
GPIO_NUM_32, //GPIO32
GPIO_NUM_33, //GPIO33
GPIO_NUM_34, //GPIO34
GPIO_NUM_35, //GPIO35
GPIO_NUM_36, //GPIO36
GPIO_NUM_37, //GPIO37
GPIO_NUM_38, //GPIO38
GPIO_NUM_39, //GPIO39
};
#elif defined CONFIG_IDF_TARGET_ESP32S2
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 20
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
// GPIO_NUM_0, //GPIO0 // Workaround: GPIO0 is strap pin, can not be used pullup/pulldown test.
GPIO_NUM_1, //GPIO1
GPIO_NUM_2, //GPIO2
GPIO_NUM_3, //GPIO3
GPIO_NUM_4, //GPIO4
GPIO_NUM_5, //GPIO5
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
GPIO_NUM_8, //GPIO8
GPIO_NUM_9, //GPIO9
GPIO_NUM_10, //GPIO10
GPIO_NUM_11, //GPIO11
GPIO_NUM_12, //GPIO12
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
GPIO_NUM_16, //GPIO16
GPIO_NUM_17, //GPIO17
// GPIO_NUM_18, //GPIO18 // Workaround: IO18 is pullup outside in ESP32S2-Saola Runner.
GPIO_NUM_19, //GPIO19
GPIO_NUM_20, //GPIO20
GPIO_NUM_21, //GPIO21
};
#elif defined CONFIG_IDF_TARGET_ESP32S3
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 21
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
// GPIO_NUM_0, //GPIO0 // Workaround: GPIO0 is strap pin, can not be used pullup/pulldown test.
GPIO_NUM_1, //GPIO1
GPIO_NUM_2, //GPIO2
GPIO_NUM_3, //GPIO3
GPIO_NUM_4, //GPIO4
GPIO_NUM_5, //GPIO5
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
GPIO_NUM_8, //GPIO8
GPIO_NUM_9, //GPIO9
GPIO_NUM_10, //GPIO10
GPIO_NUM_11, //GPIO11
GPIO_NUM_12, //GPIO12
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
GPIO_NUM_16, //GPIO16
GPIO_NUM_17, //GPIO17
GPIO_NUM_18, //GPIO18
GPIO_NUM_19, //GPIO19
GPIO_NUM_20, //GPIO20
GPIO_NUM_21, //GPIO21
};
#elif CONFIG_IDF_TARGET_ESP32C6
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 8
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_0, //GPIO0
GPIO_NUM_1, //GPIO1
GPIO_NUM_2, //GPIO2
GPIO_NUM_3, //GPIO3
GPIO_NUM_4, //GPIO4
GPIO_NUM_5, //GPIO5
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
};
#elif CONFIG_IDF_TARGET_ESP32H2
#define TEST_GPIO_PIN_COUNT 8
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_7, //GPIO7
GPIO_NUM_8, //GPIO8
GPIO_NUM_9, //GPIO9
GPIO_NUM_10, //GPIO10
GPIO_NUM_11, //GPIO11
GPIO_NUM_12, //GPIO12
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
};
#endif
#include "soc/soc_caps.h"
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
static const char *TAG = "rtcio_test";
@ -341,6 +235,7 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]")
#endif //SOC_RTCIO_HOLD_SUPPORTED
#endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO: IDF-7529
// It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep
// Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin
// (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5, H2: IO12) these pads' default configuration is low level
@ -389,3 +284,4 @@ static void rtcio_deep_sleep_hold_test_second_stage(void)
TEST_CASE_MULTIPLE_STAGES("RTCIO_deep_sleep_output_hold_test", "[rtcio]",
rtcio_deep_sleep_hold_test_first_stage,
rtcio_deep_sleep_hold_test_second_stage)
#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4)

148
components/driver/test_apps/gpio/main/test_rtcio.h Normal file
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@ -0,0 +1,148 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "sdkconfig.h"
#include "soc/gpio_num.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_IDF_TARGET_ESP32
// The input-only rtcio pins do not have pull-up/down resistors (not support pull-up/down)
#define RTCIO_SUPPORT_PU_PD(num) (rtc_io_desc[num].pullup != 0)
#define TEST_GPIO_PIN_COUNT 16
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
// GPIO_NUM_0, //GPIO0 // Workaround: GPIO0 is strap pin, can not be used pullup/pulldown test.
GPIO_NUM_2, //GPIO2
GPIO_NUM_4, //GPIO4
// GPIO_NUM_12, //GPIO12 // Workaround: GPIO12 is strap pin, can not be used pullup/pulldown test.
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
GPIO_NUM_25, //GPIO25
GPIO_NUM_26, //GPIO26
GPIO_NUM_27, //GPIO27
GPIO_NUM_32, //GPIO32
GPIO_NUM_33, //GPIO33
GPIO_NUM_34, //GPIO34
GPIO_NUM_35, //GPIO35
GPIO_NUM_36, //GPIO36
GPIO_NUM_37, //GPIO37
GPIO_NUM_38, //GPIO38
GPIO_NUM_39, //GPIO39
};
#elif defined CONFIG_IDF_TARGET_ESP32S2
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 20
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
// GPIO_NUM_0, //GPIO0 // Workaround: GPIO0 is strap pin, can not be used pullup/pulldown test.
GPIO_NUM_1, //GPIO1
GPIO_NUM_2, //GPIO2
GPIO_NUM_3, //GPIO3
GPIO_NUM_4, //GPIO4
GPIO_NUM_5, //GPIO5
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
GPIO_NUM_8, //GPIO8
GPIO_NUM_9, //GPIO9
GPIO_NUM_10, //GPIO10
GPIO_NUM_11, //GPIO11
GPIO_NUM_12, //GPIO12
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
GPIO_NUM_16, //GPIO16
GPIO_NUM_17, //GPIO17
// GPIO_NUM_18, //GPIO18 // Workaround: IO18 is pullup outside in ESP32S2-Saola Runner.
GPIO_NUM_19, //GPIO19
GPIO_NUM_20, //GPIO20
GPIO_NUM_21, //GPIO21
};
#elif defined CONFIG_IDF_TARGET_ESP32S3
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 21
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
// GPIO_NUM_0, //GPIO0 // Workaround: GPIO0 is strap pin, can not be used pullup/pulldown test.
GPIO_NUM_1, //GPIO1
GPIO_NUM_2, //GPIO2
GPIO_NUM_3, //GPIO3
GPIO_NUM_4, //GPIO4
GPIO_NUM_5, //GPIO5
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
GPIO_NUM_8, //GPIO8
GPIO_NUM_9, //GPIO9
GPIO_NUM_10, //GPIO10
GPIO_NUM_11, //GPIO11
GPIO_NUM_12, //GPIO12
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
GPIO_NUM_16, //GPIO16
GPIO_NUM_17, //GPIO17
GPIO_NUM_18, //GPIO18
GPIO_NUM_19, //GPIO19
GPIO_NUM_20, //GPIO20
GPIO_NUM_21, //GPIO21
};
#elif CONFIG_IDF_TARGET_ESP32C6
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 8
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_0, //GPIO0
GPIO_NUM_1, //GPIO1
GPIO_NUM_2, //GPIO2
GPIO_NUM_3, //GPIO3
GPIO_NUM_4, //GPIO4
GPIO_NUM_5, //GPIO5
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
};
#elif CONFIG_IDF_TARGET_ESP32H2
#define TEST_GPIO_PIN_COUNT 8
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_7, //GPIO7
GPIO_NUM_8, //GPIO8
GPIO_NUM_9, //GPIO9
GPIO_NUM_10, //GPIO10
GPIO_NUM_11, //GPIO11
GPIO_NUM_12, //GPIO12
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
};
#elif CONFIG_IDF_TARGET_ESP32P4
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 16
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_0, //GPIO0
GPIO_NUM_1, //GPIO1
GPIO_NUM_2, //GPIO2
GPIO_NUM_3, //GPIO3
GPIO_NUM_4, //GPIO4
GPIO_NUM_5, //GPIO5
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
GPIO_NUM_8, //GPIO8
GPIO_NUM_9, //GPIO9
GPIO_NUM_10, //GPIO10
GPIO_NUM_11, //GPIO11
GPIO_NUM_12, //GPIO12
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
};
#endif
#ifdef __cplusplus
}
#endif

1
components/driver/test_apps/gpio/pytest_gpio.py
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@ -34,6 +34,7 @@ def test_legacy_sigma_delta(dut: IdfDut) -> None:
@pytest.mark.esp32s3
@pytest.mark.esp32c6
@pytest.mark.esp32h2
@pytest.mark.esp32p4
@pytest.mark.generic
@pytest.mark.parametrize('config', CONFIGS, indirect=True)
def test_rtc_io(dut: IdfDut) -> None:

6
components/esp_hw_support/sleep_modes.c
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@ -1389,7 +1389,7 @@ static void ext0_wakeup_prepare(void)
{
int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
rtcio_hal_ext0_set_wakeup_pin(rtc_gpio_num, s_config.ext0_trigger_level);
rtcio_hal_function_select(rtc_gpio_num, RTCIO_FUNC_RTC);
rtcio_hal_function_select(rtc_gpio_num, RTCIO_LL_FUNC_RTC);
rtcio_hal_input_enable(rtc_gpio_num);
}
#endif // SOC_PM_SUPPORT_EXT0_WAKEUP
@ -1462,7 +1462,7 @@ static void ext1_wakeup_prepare(void)
}
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
// Route pad to RTC
rtcio_hal_function_select(rtc_pin, RTCIO_FUNC_RTC);
rtcio_hal_function_select(rtc_pin, RTCIO_LL_FUNC_RTC);
// set input enable in sleep mode
rtcio_hal_input_enable(rtc_pin);
#if SOC_PM_SUPPORT_RTC_PERIPH_PD
@ -1477,7 +1477,7 @@ static void ext1_wakeup_prepare(void)
* a pathway to EXT1. */
// Route pad to DIGITAL
rtcio_hal_function_select(rtc_pin, RTCIO_FUNC_DIGITAL);
rtcio_hal_function_select(rtc_pin, RTCIO_LL_FUNC_DIGITAL);
// set input enable
gpio_ll_input_enable(&GPIO, gpio);
// hold rtc_pin to use it during sleep state

53
components/hal/esp32/include/hal/rtc_io_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -13,8 +13,9 @@
#pragma once
#include <stdlib.h>
#include "soc/rtc_io_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/rtc_periph.h"
#include "hal/gpio_types.h"
#define RTCIO_LL_PIN_FUNC 0
@ -23,19 +24,19 @@ extern "C" {
#endif
typedef enum {
RTCIO_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */
RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */
RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
} rtcio_ll_func_t;
typedef enum {
RTCIO_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */
RTCIO_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */
RTCIO_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */
RTCIO_LL_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */
RTCIO_LL_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */
RTCIO_LL_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */
} rtcio_ll_wake_type_t;
typedef enum {
RTCIO_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */
RTCIO_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
RTCIO_LL_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */
RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
/**
@ -58,12 +59,12 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
*/
static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
{
if (func == RTCIO_FUNC_RTC) {
if (func == RTCIO_LL_FUNC_RTC) {
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
//0:RTC FUNCTION 1,2,3:Reserved
rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
} else if (func == RTCIO_FUNC_DIGITAL) {
} else if (func == RTCIO_LL_FUNC_DIGITAL) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
}
}
@ -291,7 +292,7 @@ static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t ty
static inline void rtcio_ll_wakeup_disable(int rtcio_num)
{
RTCIO.pin[rtcio_num].wakeup_enable = 0;
RTCIO.pin[rtcio_num].int_type = RTCIO_WAKEUP_DISABLE;
RTCIO.pin[rtcio_num].int_type = RTCIO_LL_WAKEUP_DISABLE;
}
/**
@ -299,10 +300,10 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_output_in_sleep(int rtcio_num)
{
if (rtc_io_desc[gpio_num].slpoe) {
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe);
if (rtc_io_desc[rtcio_num].slpoe) {
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpoe);
}
}
@ -311,10 +312,10 @@ static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_output_in_sleep(int rtcio_num)
{
if (rtc_io_desc[gpio_num].slpoe) {
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe);
if (rtc_io_desc[rtcio_num].slpoe) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpoe);
}
}
@ -323,9 +324,9 @@ static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num)
{
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpie);
}
/**
@ -333,9 +334,9 @@ static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_input_in_sleep(int rtcio_num)
{
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpie);
}
/**
@ -343,9 +344,9 @@ static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_sleep_setting(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_sleep_setting(int rtcio_num)
{
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel);
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpsel);
}
/**
@ -353,9 +354,9 @@ static inline void rtcio_ll_enable_sleep_setting(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_sleep_setting(int rtcio_num)
{
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel);
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpsel);
}
/**

64
components/hal/esp32c6/include/hal/rtc_io_ll.h
View File

@ -14,15 +14,13 @@
#include <stdlib.h>
#include <stdbool.h>
#include "soc/rtc_periph.h"
#include "soc/soc_caps.h"
#include "soc/pcr_struct.h"
#include "soc/rtc_io_struct.h"
#include "soc/lp_io_struct.h"
#include "soc/lp_aon_struct.h"
#include "soc/pmu_struct.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/gpio_types.h"
#include "soc/io_mux_reg.h"
#ifdef __cplusplus
extern "C" {
@ -31,19 +29,19 @@ extern "C" {
#define RTCIO_LL_PIN_FUNC 0
typedef enum {
RTCIO_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */
RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */
RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
} rtcio_ll_func_t;
typedef enum {
RTCIO_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */
RTCIO_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */
RTCIO_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */
RTCIO_LL_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */
RTCIO_LL_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */
RTCIO_LL_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */
} rtcio_ll_wake_type_t;
typedef enum {
RTCIO_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */
RTCIO_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
RTCIO_LL_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */
RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
/**
@ -69,14 +67,14 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
*/
static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
{
if (func == RTCIO_FUNC_RTC) {
if (func == RTCIO_LL_FUNC_RTC) {
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
sel_mask |= BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
//0:RTC FUNCTION 1,2,3:Reserved
rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
} else if (func == RTCIO_FUNC_DIGITAL) {
} else if (func == RTCIO_LL_FUNC_DIGITAL) {
// Clear the bit to use digital GPIO module
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
sel_mask &= ~BIT(rtcio_num);
@ -147,7 +145,7 @@ static inline void rtcio_ll_input_disable(int rtcio_num)
*/
static inline uint32_t rtcio_ll_get_level(int rtcio_num)
{
return (uint32_t)(LP_IO.in.in_data_next >> rtcio_num) & 0x1;
return (uint32_t)(HAL_FORCE_READ_U32_REG_FIELD(LP_IO.in, in_data_next) >> rtcio_num) & 0x1;
}
/**
@ -296,7 +294,7 @@ static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t ty
static inline void rtcio_ll_wakeup_disable(int rtcio_num)
{
LP_IO.pin[rtcio_num].wakeup_enable = 0;
LP_IO.pin[rtcio_num].int_type = RTCIO_WAKEUP_DISABLE;
LP_IO.pin[rtcio_num].int_type = RTCIO_LL_WAKEUP_DISABLE;
}
/**
@ -304,9 +302,9 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_output_in_sleep(int rtcio_num)
{
LP_IO.gpio[gpio_num].mcu_oe = 1;
LP_IO.gpio[rtcio_num].mcu_oe = 1;
}
/**
@ -314,9 +312,9 @@ static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_output_in_sleep(int rtcio_num)
{
LP_IO.gpio[gpio_num].mcu_oe = 0;
LP_IO.gpio[rtcio_num].mcu_oe = 0;
}
/**
@ -324,9 +322,9 @@ static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num)
{
LP_IO.gpio[gpio_num].mcu_ie = 1;
LP_IO.gpio[rtcio_num].mcu_ie = 1;
}
/**
@ -334,9 +332,9 @@ static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_input_in_sleep(int rtcio_num)
{
LP_IO.gpio[gpio_num].mcu_ie = 0;
LP_IO.gpio[rtcio_num].mcu_ie = 0;
}
/**
@ -344,9 +342,9 @@ static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_sleep_setting(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_sleep_setting(int rtcio_num)
{
LP_IO.gpio[gpio_num].slp_sel = 1;
LP_IO.gpio[rtcio_num].slp_sel = 1;
}
/**
@ -354,23 +352,21 @@ static inline void rtcio_ll_enable_sleep_setting(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_sleep_setting(int rtcio_num)
{
LP_IO.gpio[gpio_num].slp_sel = 0;
LP_IO.gpio[rtcio_num].slp_sel = 0;
}
/**
* @brief Get the status of whether an IO is used for sleep wake-up.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @return True if the pin is enabled to wake up from deep-sleep
*/
static inline bool rtcio_ll_wakeup_is_enabled(gpio_num_t gpio_num)
static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num)
{
HAL_ASSERT(gpio_num <= GPIO_NUM_7 && "gpio larger than 7 does not support deep sleep wake-up function");
// On ESP32-C6, (lp_io pin number) == (gpio pin number)
return LP_IO.pin[gpio_num].wakeup_enable;
HAL_ASSERT(rtcio_num >= 0 && rtcio_num < SOC_RTCIO_PIN_COUNT && "io does not support deep sleep wake-up function");
return LP_IO.pin[rtcio_num].wakeup_enable;
}
/**
@ -380,7 +376,7 @@ static inline bool rtcio_ll_wakeup_is_enabled(gpio_num_t gpio_num)
*/
static inline uint32_t rtcio_ll_get_interrupt_status(void)
{
return (uint32_t)(LP_IO.status.status_interrupt);
return (uint32_t)HAL_FORCE_READ_U32_REG_FIELD(LP_IO.status, status_interrupt);
}
/**

8
components/hal/esp32h2/include/hal/rtc_io_ll.h
View File

@ -23,8 +23,8 @@ extern "C" {
#define RTCIO_LL_GPIO_NUM_OFFSET 7 // rtcio 0-7 correspond to gpio 7-14
typedef enum {
RTCIO_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */
RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */
RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
} rtcio_ll_func_t;
/**
@ -37,12 +37,12 @@ typedef enum {
*/
static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
{
if (func == RTCIO_FUNC_RTC) {
if (func == RTCIO_LL_FUNC_RTC) {
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
sel_mask |= BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
} else if (func == RTCIO_FUNC_DIGITAL) {
} else if (func == RTCIO_LL_FUNC_DIGITAL) {
// Clear the bit to use digital GPIO module
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
sel_mask &= ~BIT(rtcio_num);

43
components/hal/esp32p4/include/hal/gpio_ll.h
View File

@ -247,18 +247,17 @@ static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: IDF-7480 Fix magic number 16 with proper macro
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO0-15
LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys |= bit_mask;
} else {
if (gpio_num < 32 + 16) {
if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
// GPIO 16-47
HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low |= (bit_mask >> 16);
HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low |= (bit_mask >> SOC_RTCIO_PIN_COUNT);
} else {
// GPIO 48-56
HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high |= (bit_mask >> (32 + 16));
HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high |= (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
}
@ -271,18 +270,17 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
*/
static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: IDF-7480 Fix magic number 16 with proper macro
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO0-15
LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys &= ~bit_mask;
} else {
if (gpio_num < 32 + 16) {
if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
// GPIO 16-47
HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low &= ~(bit_mask >> 16);
HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low &= ~(bit_mask >> SOC_RTCIO_PIN_COUNT);
} else {
// GPIO 48-56
HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high &= ~(bit_mask >> (32 + 16));
HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
}
@ -443,18 +441,19 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: IDF-7480 Fix magic number 16 with proper macro
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO 0-15
LP_IOMUX.lp_pad_hold.reg_lp_gpio_hold |= bit_mask;
uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold);
hold_mask |= bit_mask;
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask);
} else {
if (gpio_num < 32 + 16) {
if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
// GPIO 16-47
HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low |= (bit_mask >> 16);
HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low |= (bit_mask >> SOC_RTCIO_PIN_COUNT);
} else {
// GPIO 48-56
HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high |= (bit_mask >> (32 + 16));
HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high |= (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
}
@ -467,18 +466,19 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: IDF-7480 Fix magic number 16 with proper macro
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO 0-15
LP_IOMUX.lp_pad_hold.reg_lp_gpio_hold &= ~bit_mask;
uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold);
hold_mask &= ~bit_mask;
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask);
} else {
if (gpio_num < 32 + 16) {
if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
// GPIO 16-47
HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low &= ~(bit_mask >> 16);
HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low &= ~(bit_mask >> SOC_RTCIO_PIN_COUNT);
} else {
// GPIO 48-56
HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high &= ~(bit_mask >> (32 + 16));
HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
}
@ -498,18 +498,17 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: IDF-7480 Fix magic number 16 with proper macro
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO 0-15
abort();
} else {
if (gpio_num < 32 + 16) {
if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
// GPIO 16-47
return !!(HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low & (bit_mask >> 16));
return !!(HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low & (bit_mask >> SOC_RTCIO_PIN_COUNT));
} else {
// GPIO 48-56
return !!(HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high & (bit_mask >> (32 + 16)));
return !!(HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high & (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)));
}
}
}

436
components/hal/esp32p4/include/hal/rtc_io_ll.h Normal file
View File

@ -0,0 +1,436 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once
#include <stdbool.h>
#include "esp_bit_defs.h"
#include "soc/soc_caps.h"
#include "soc/lp_gpio_struct.h"
#include "soc/lp_iomux_struct.h"
#include "soc/lp_gpio_sig_map.h"
#include "soc/pmu_struct.h"
#include "hal/misc.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RTCIO_LL_PIN_FUNC 1 // LP_GPIO function
typedef enum {
RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */
RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
} rtcio_ll_func_t;
typedef enum {
RTCIO_LL_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */
RTCIO_LL_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */
RTCIO_LL_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */
} rtcio_ll_wake_type_t;
typedef enum {
RTCIO_LL_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */
RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
/**
* @brief Select RTC GPIO input to a signal.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param signal_idx LP peripheral signal index.
* @param inv True to invert input signal; False then no invert.
*/
static inline void rtcio_ll_matrix_in(int rtcio_num, uint32_t signal_idx, bool inv)
{
lp_gpio_func_in_sel_cfg_reg_t reg;
reg.func_in_sel = rtcio_num;
reg.in_inv_sel = inv;
reg.sig_in_sel = 1; // Bypass LP_GPIO
LP_GPIO.func_in_sel_cfg[signal_idx].val = reg.val;
}
/**
* @brief Select signal output to a RTC GPIO.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param signal_idx LP peripheral signal index.
* @param out_inv True to invert output signal; False then no invert.
* @param oen_inv True to invert output enable signal; False then no invert.
*/
static inline void rtcio_ll_matrix_out(int rtcio_num, uint32_t signal_idx, bool out_inv, bool oen_inv)
{
lp_gpio_func_out_sel_cfg_reg_t reg;
reg.func_out_sel = signal_idx;
reg.out_inv_sel = out_inv;
reg.oe_inv_sel = oen_inv;
LP_GPIO.func_out_sel_cfg[rtcio_num].val = reg.val;
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, reg_gpio_enable_data_w1ts, BIT(rtcio_num));
}
/**
* @brief Select a RTC IOMUX function for the RTC IO
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param func Function to assign to the pin
*/
static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
{
LP_IOMUX.pad[rtcio_num].fun_sel = func;
// When using as normal (output) LP_GPIO, it is reasonable to ensure that no peripheral signal is routed to the pin
if (func == RTCIO_LL_PIN_FUNC) {
LP_GPIO.func_out_sel_cfg[rtcio_num].func_out_sel = SIG_LP_GPIO_OUT_IDX;
}
}
/**
* @brief Select the lp_gpio/hp_gpio function to control the pad.
*
* @note The RTC function must be selected before the pad analog function is enabled.
* @note The clock gating 'HP_SYS_CLKRST.soc_clk_ctrl3.reg_iomux_apb_clk_en' is the gate of 'lp_io', 'ana_cmpr', 'sdm', 'glitch_fliter', and 'etm_gpio'
* And it's default to be turned on, so we don't need to operate this clock gate here additionally
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param func Select pin function.
*/
static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
{
if (func == RTCIO_LL_FUNC_RTC) {
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
LP_IOMUX.pad[rtcio_num].mux_sel = 1;
// LP_GPIO is FUNC 1
rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
} else if (func == RTCIO_LL_FUNC_DIGITAL) {
// Clear the bit to use digital GPIO module
LP_IOMUX.pad[rtcio_num].mux_sel = 0;
}
}
/**
* @brief Enable RTCIO output.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_output_enable(int rtcio_num)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, reg_gpio_enable_data_w1ts, BIT(rtcio_num));
}
/**
* @brief Disable RTCIO output.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_output_disable(int rtcio_num)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, reg_gpio_enable_data_w1tc, BIT(rtcio_num));
// Ensure no other output signal is routed via LP_GPIO matrix to this pin
LP_GPIO.func_out_sel_cfg[rtcio_num].func_out_sel = SIG_LP_GPIO_OUT_IDX;
}
/**
* @brief Set RTCIO output level.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param level 0: output low; 1: output high.
*/
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{
if (level) {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, reg_gpio_out_data_w1ts, BIT(rtcio_num));
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, reg_gpio_out_data_w1tc, BIT(rtcio_num));
}
}
/**
* @brief Enable RTCIO input.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_input_enable(int rtcio_num)
{
LP_IOMUX.pad[rtcio_num].fun_ie = 1;
}
/**
* @brief Disable RTCIO input.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_input_disable(int rtcio_num)
{
LP_IOMUX.pad[rtcio_num].fun_ie = 0;
}
/**
* @brief Get RTCIO input level.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*
* @return 0: input low; 1: input high.
*/
static inline uint32_t rtcio_ll_get_level(int rtcio_num)
{
return (uint32_t)(HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.in, reg_gpio_in_data_next) >> rtcio_num) & 0x1;
}
/**
* @brief Set RTC GPIO pad drive capability
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param strength Drive capability of the pad. Range: 0 ~ 3.
*/
static inline void rtcio_ll_set_drive_capability(int rtcio_num, uint32_t strength)
{
LP_IOMUX.pad[rtcio_num].drv = strength;
}
/**
* @brief Get RTC GPIO pad drive capability.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*
* @return Drive capability of the pad. Range: 0 ~ 3.
*/
static inline uint32_t rtcio_ll_get_drive_capability(int rtcio_num)
{
return LP_IOMUX.pad[rtcio_num].drv;
}
/**
* @brief Set RTC GPIO pad output mode.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*
* @return mode Output mode.
*/
static inline void rtcio_ll_output_mode_set(int rtcio_num, rtcio_ll_out_mode_t mode)
{
LP_GPIO.pin[rtcio_num].pad_driver = mode;
}
/**
* @brief RTC GPIO pullup enable.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_pullup_enable(int rtcio_num)
{
/* Enable internal weak pull-up */
LP_IOMUX.pad[rtcio_num].rue = 1;
}
/**
* @brief RTC GPIO pullup disable.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_pullup_disable(int rtcio_num)
{
/* Disable internal weak pull-up */
LP_IOMUX.pad[rtcio_num].rue = 0;
}
/**
* @brief RTC GPIO pulldown enable.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_pulldown_enable(int rtcio_num)
{
/* Enable internal weak pull-down */
LP_IOMUX.pad[rtcio_num].rde = 1;
}
/**
* @brief RTC GPIO pulldown disable.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_pulldown_disable(int rtcio_num)
{
/* Enable internal weak pull-down */
LP_IOMUX.pad[rtcio_num].rde = 0;
}
/**
* @brief Enable force hold function for an RTC IO pad.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
* This function is useful when going into light or deep sleep mode to prevent
* the pin configuration from changing.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_force_hold_enable(int rtcio_num)
{
uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold);
hold_mask |= BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask);
}
/**
* @brief Disable hold function on an RTC IO pad
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_force_hold_disable(int rtcio_num)
{
uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold);
hold_mask &= ~BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask);
}
/**
* @brief Enable force hold function for all RTC IO pads
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
* This function is useful when going into light or deep sleep mode to prevent
* the pin configuration from changing.
*/
static inline void rtcio_ll_force_hold_all(void)
{
PMU.imm_pad_hold_all.tie_high_lp_pad_hold_all = 1;
}
/**
* @brief Disable hold function fon all RTC IO pads
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
*/
static inline void rtcio_ll_force_unhold_all(void)
{
PMU.imm_pad_hold_all.tie_low_lp_pad_hold_all = 1;
}
/**
* @brief Enable wakeup function and set wakeup type from light sleep or deep sleep for RTCIO.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param type Wakeup on high level or low level.
*/
static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type)
{
LP_GPIO.pin[rtcio_num].wakeup_enable = 1;
LP_GPIO.pin[rtcio_num].int_type = type;
}
/**
* @brief Disable wakeup function from light sleep or deep sleep for RTCIO.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_wakeup_disable(int rtcio_num)
{
LP_GPIO.pin[rtcio_num].wakeup_enable = 0;
LP_GPIO.pin[rtcio_num].int_type = RTCIO_LL_WAKEUP_DISABLE;
}
/**
* @brief Enable RTCIO output in deep sleep.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_output_in_sleep(int rtcio_num)
{
LP_IOMUX.pad[rtcio_num].slp_oe = 1;
}
/**
* @brief Disable RTCIO output in deep sleep.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_output_in_sleep(int rtcio_num)
{
LP_IOMUX.pad[rtcio_num].slp_oe = 0;
}
/**
* @brief Enable RTCIO input in deep sleep.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num)
{
LP_IOMUX.pad[rtcio_num].slp_ie = 1;
}
/**
* @brief Disable RTCIO input in deep sleep.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_input_in_sleep(int rtcio_num)
{
LP_IOMUX.pad[rtcio_num].slp_ie = 0;
}
/**
* @brief Enable RTCIO keep another setting in deep sleep.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_sleep_setting(int rtcio_num)
{
LP_IOMUX.pad[rtcio_num].slp_sel = 1;
}
/**
* @brief Disable RTCIO keep another setting in deep sleep. (Default)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_sleep_setting(int rtcio_num)
{
LP_IOMUX.pad[rtcio_num].slp_sel = 0;
}
/**
* @brief Get the status of whether an IO is used for sleep wake-up.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @return True if the pin is enabled to wake up from deep-sleep
*/
static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num)
{
HAL_ASSERT(rtcio_num >= 0 && rtcio_num < SOC_RTCIO_PIN_COUNT && "io does not support deep sleep wake-up function");
return LP_GPIO.pin[rtcio_num].wakeup_enable;
}
/**
* @brief Get the LP IO interrupt status
*
* @return Bit 0~15 corresponding to 0 ~ SOC_RTCIO_PIN_COUNT.
*/
static inline uint32_t rtcio_ll_get_interrupt_status(void)
{
return (uint32_t)HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.status, reg_gpio_status_data);
}
/**
* @brief Clear all LP IO pads status
*/
static inline void rtcio_ll_clear_interrupt_status(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, reg_gpio_status_data_w1tc, 0xFFFF);
}
#ifdef __cplusplus
}
#endif

53
components/hal/esp32s2/include/hal/rtc_io_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -13,9 +13,10 @@
#pragma once
#include <stdlib.h>
#include "soc/rtc_io_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/rtc_periph.h"
#include "soc/sens_struct.h"
#include "hal/gpio_types.h"
#define RTCIO_LL_PIN_FUNC 0
@ -24,19 +25,19 @@ extern "C" {
#endif
typedef enum {
RTCIO_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */
RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */
RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
} rtcio_ll_func_t;
typedef enum {
RTCIO_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */
RTCIO_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */
RTCIO_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */
RTCIO_LL_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */
RTCIO_LL_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */
RTCIO_LL_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */
} rtcio_ll_wake_type_t;
typedef enum {
RTCIO_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */
RTCIO_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
RTCIO_LL_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */
RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
/**
@ -59,13 +60,13 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
*/
static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
{
if (func == RTCIO_FUNC_RTC) {
if (func == RTCIO_LL_FUNC_RTC) {
SENS.sar_io_mux_conf.iomux_clk_gate_en = 1;
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
//0:RTC FUNCTION 1,2,3:Reserved
rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
} else if (func == RTCIO_FUNC_DIGITAL) {
} else if (func == RTCIO_LL_FUNC_DIGITAL) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;
}
@ -294,7 +295,7 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
{
SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;
RTCIO.pin[rtcio_num].wakeup_enable = 0;
RTCIO.pin[rtcio_num].int_type = RTCIO_WAKEUP_DISABLE;
RTCIO.pin[rtcio_num].int_type = RTCIO_LL_WAKEUP_DISABLE;
}
/**
@ -302,10 +303,10 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_output_in_sleep(int rtcio_num)
{
if (rtc_io_desc[gpio_num].slpoe) {
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe);
if (rtc_io_desc[rtcio_num].slpoe) {
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpoe);
}
}
@ -314,10 +315,10 @@ static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_output_in_sleep(int rtcio_num)
{
if (rtc_io_desc[gpio_num].slpoe) {
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe);
if (rtc_io_desc[rtcio_num].slpoe) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpoe);
}
}
@ -326,9 +327,9 @@ static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num)
{
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpie);
}
/**
@ -336,9 +337,9 @@ static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_input_in_sleep(int rtcio_num)
{
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpie);
}
/**
@ -346,9 +347,9 @@ static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_sleep_setting(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_sleep_setting(int rtcio_num)
{
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel);
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpsel);
}
/**
@ -356,9 +357,9 @@ static inline void rtcio_ll_enable_sleep_setting(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_sleep_setting(int rtcio_num)
{
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel);
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpsel);
}
/**

51
components/hal/esp32s3/include/hal/rtc_io_ll.h
View File

@ -13,8 +13,9 @@
#pragma once
#include <stdlib.h>
#include "soc/rtc_io_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/rtc_periph.h"
#include "hal/gpio_types.h"
#include "soc/io_mux_reg.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/usb_serial_jtag_struct.h"
@ -26,19 +27,19 @@ extern "C" {
#define RTCIO_LL_PIN_FUNC 0
typedef enum {
RTCIO_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */
RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */
RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
} rtcio_ll_func_t;
typedef enum {
RTCIO_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */
RTCIO_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */
RTCIO_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */
RTCIO_LL_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */
RTCIO_LL_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */
RTCIO_LL_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */
} rtcio_ll_wake_type_t;
typedef enum {
RTCIO_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */
RTCIO_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
RTCIO_LL_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */
RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
/**
@ -61,7 +62,7 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
*/
static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
{
if (func == RTCIO_FUNC_RTC) {
if (func == RTCIO_LL_FUNC_RTC) {
// Disable USB Serial JTAG if pin 19 or pin 20 needs to select the rtc function
if (rtcio_num == rtc_io_num_map[USB_INT_PHY0_DM_GPIO_NUM] || rtcio_num == rtc_io_num_map[USB_INT_PHY0_DP_GPIO_NUM]) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
@ -71,7 +72,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
//0:RTC FUNCTION 1,2,3:Reserved
rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
} else if (func == RTCIO_FUNC_DIGITAL) {
} else if (func == RTCIO_LL_FUNC_DIGITAL) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
SENS.sar_peri_clk_gate_conf.iomux_clk_en = 0;
// USB Serial JTAG pad re-enable won't be done here (it requires both DM and DP pins not in rtc function)
@ -309,7 +310,7 @@ static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t ty
static inline void rtcio_ll_wakeup_disable(int rtcio_num)
{
RTCIO.pin[rtcio_num].wakeup_enable = 0;
RTCIO.pin[rtcio_num].int_type = RTCIO_WAKEUP_DISABLE;
RTCIO.pin[rtcio_num].int_type = RTCIO_LL_WAKEUP_DISABLE;
}
/**
@ -317,10 +318,10 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_output_in_sleep(int rtcio_num)
{
if (rtc_io_desc[gpio_num].slpoe) {
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe);
if (rtc_io_desc[rtcio_num].slpoe) {
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpoe);
}
}
@ -329,10 +330,10 @@ static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_output_in_sleep(int rtcio_num)
{
if (rtc_io_desc[gpio_num].slpoe) {
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe);
if (rtc_io_desc[rtcio_num].slpoe) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpoe);
}
}
@ -341,9 +342,9 @@ static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num)
{
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpie);
}
/**
@ -351,9 +352,9 @@ static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_input_in_sleep(int rtcio_num)
{
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpie);
}
/**
@ -361,9 +362,9 @@ static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_sleep_setting(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_sleep_setting(int rtcio_num)
{
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel);
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpsel);
}
/**
@ -371,9 +372,9 @@ static inline void rtcio_ll_enable_sleep_setting(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_sleep_setting(int rtcio_num)
{
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel);
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].slpsel);
}
/**

34
components/hal/include/hal/rtc_io_hal.h
View File

@ -19,6 +19,7 @@
#include "soc/soc_caps.h"
#if SOC_RTCIO_PIN_COUNT > 0
#include "soc/rtc_io_periph.h"
#include "hal/rtc_io_ll.h"
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#include "hal/rtc_io_types.h"
@ -130,8 +131,8 @@ void rtcio_hal_set_direction(int rtcio_num, rtc_gpio_mode_t mode);
/**
* Set RTC IO direction in deep sleep or disable sleep status.
*
* NOTE: ESP32 support INPUT_ONLY mode.
* ESP32S2 support INPUT_ONLY, OUTPUT_ONLY, INPUT_OUTPUT mode.
* NOTE: ESP32 supports INPUT_ONLY mode.
* The rest targets support INPUT_ONLY, OUTPUT_ONLY, INPUT_OUTPUT mode.
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
* @param mode IO direction.
@ -174,6 +175,27 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
*/
#define rtcio_hal_iomux_func_sel(rtcio_num, func) rtcio_ll_iomux_func_sel(rtcio_num, func)
#if SOC_LP_GPIO_MATRIX_SUPPORTED
/**
* Select RTC GPIO input to a signal
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
* @param signal_idx LP peripheral signal index.
* @param inv inv True to invert input signal; False then no invert.
*/
#define rtcio_hal_matrix_in(rtcio_num, signal_idx, inv) rtcio_ll_matrix_in(rtcio_num, signal_idx, inv)
/**
* Select signal output to a RTC GPIO
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
* @param signal_idx LP peripheral signal index.
* @param out_inv True to invert output signal; False then no invert.
* @param oen_inv True to invert output enable signal; False then no invert.
*/
#define rtcio_hal_matrix_out(rtcio_num, signal_idx, out_inv, oen_inv) rtcio_ll_matrix_out(rtcio_num, signal_idx, out_inv, oen_inv)
#endif // SOC_LP_GPIO_MATRIX_SUPPORTED
#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_HOLD_SUPPORTED
@ -269,9 +291,9 @@ void rtcio_hal_isolate(int rtc_num);
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0)
#define gpio_hal_deepsleep_wakeup_enable(hal, gpio_num, intr_type) rtcio_hal_wakeup_enable(gpio_num, intr_type)
#define gpio_hal_deepsleep_wakeup_disable(hal, gpio_num) rtcio_hal_wakeup_disable(gpio_num)
#define gpio_hal_deepsleep_wakeup_is_enabled(hal, gpio_num) rtcio_hal_wakeup_is_enabled(gpio_num)
#define gpio_hal_deepsleep_wakeup_enable(hal, gpio_num, intr_type) rtcio_hal_wakeup_enable(rtc_io_num_map[gpio_num], intr_type)
#define gpio_hal_deepsleep_wakeup_disable(hal, gpio_num) rtcio_hal_wakeup_disable(rtc_io_num_map[gpio_num])
#define gpio_hal_deepsleep_wakeup_is_enabled(hal, gpio_num) rtcio_hal_wakeup_is_enabled(rtc_io_num_map[gpio_num])
#define rtc_hal_gpio_get_wakeup_status() rtcio_hal_get_interrupt_status()
#define rtc_hal_gpio_clear_wakeup_status() rtcio_hal_clear_interrupt_status()
@ -279,7 +301,7 @@ void rtcio_hal_isolate(int rtc_num);
* @brief Get the status of whether an IO is used for sleep wake-up.
*
* @param hw Peripheral GPIO hardware instance address.
* @param rtcio_num GPIO number
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
* @return True if the pin is enabled to wake up from deep-sleep
*/
#define rtcio_hal_wakeup_is_enabled(rtcio_num) rtcio_ll_wakeup_is_enabled(rtcio_num)

12
components/hal/rtc_io_hal.c
View File

@ -15,32 +15,32 @@ void rtcio_hal_set_direction(int rtcio_num, rtc_gpio_mode_t mode)
{
switch (mode) {
case RTC_GPIO_MODE_INPUT_ONLY:
rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_NORMAL);
rtcio_ll_output_mode_set(rtcio_num, RTCIO_LL_OUTPUT_NORMAL);
rtcio_ll_output_disable(rtcio_num);
rtcio_ll_input_enable(rtcio_num);
break;
case RTC_GPIO_MODE_OUTPUT_ONLY:
rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_NORMAL);
rtcio_ll_output_mode_set(rtcio_num, RTCIO_LL_OUTPUT_NORMAL);
rtcio_ll_output_enable(rtcio_num);
rtcio_ll_input_disable(rtcio_num);
break;
case RTC_GPIO_MODE_INPUT_OUTPUT:
rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_NORMAL);
rtcio_ll_output_mode_set(rtcio_num, RTCIO_LL_OUTPUT_NORMAL);
rtcio_ll_output_enable(rtcio_num);
rtcio_ll_input_enable(rtcio_num);
break;
case RTC_GPIO_MODE_DISABLED:
rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_NORMAL);
rtcio_ll_output_mode_set(rtcio_num, RTCIO_LL_OUTPUT_NORMAL);
rtcio_ll_output_disable(rtcio_num);
rtcio_ll_input_disable(rtcio_num);
break;
case RTC_GPIO_MODE_OUTPUT_OD:
rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_OD);
rtcio_ll_output_mode_set(rtcio_num, RTCIO_LL_OUTPUT_OD);
rtcio_ll_output_enable(rtcio_num);
rtcio_ll_input_disable(rtcio_num);
break;
case RTC_GPIO_MODE_INPUT_OUTPUT_OD:
rtcio_ll_output_mode_set(rtcio_num, RTCIO_OUTPUT_OD);
rtcio_ll_output_mode_set(rtcio_num, RTCIO_LL_OUTPUT_OD);
rtcio_ll_output_enable(rtcio_num);
rtcio_ll_input_enable(rtcio_num);
break;

1
components/soc/esp32/rtc_io_periph.c
View File

@ -5,6 +5,7 @@
*/
#include "soc/rtc_periph.h"
#include "soc/rtc_io_reg.h"
const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO0_CHANNEL, //GPIO0

28
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@ -91,6 +91,14 @@ config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_LP_GPIO_MATRIX_SUPPORTED
bool
default y
config SOC_LP_PERIPHERALS_SUPPORTED
bool
default y
config SOC_SPIRAM_SUPPORTED
bool
default y
@ -315,6 +323,10 @@ config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_VALID_GPIO_MASK
hex
default 0x01FFFFFFFFFFFFFF
@ -335,6 +347,22 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 16
config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
bool
default y
config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_RTCIO_WAKE_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8

21
components/soc/esp32p4/include/soc/lp_gpio_pins.h Normal file
View File

@ -0,0 +1,21 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// `LP_GPIO_MATRIX_CONST_ONE_INPUT` means connect logic 1 to the LP peripheral signal
#define LP_GPIO_MATRIX_CONST_ONE_INPUT (0x30)
// `LP_GPIO_MATRIX_CONST_ZERO_INPUT` means connect logic 0 to the LP peripheral signal
#define LP_GPIO_MATRIX_CONST_ZERO_INPUT (0x20)
#ifdef __cplusplus
}
#endif

3
components/soc/esp32p4/include/soc/lp_gpio_sig_map.h
View File

@ -50,4 +50,7 @@
#define LP_PROBE_TOP_OUT14_IDX 28
#define LP_PROBE_TOP_OUT15_IDX 29
#define PROBE_CHAIN_CLK_PAD_OUT_IDX 30
#define SIG_LP_GPIO_OUT_IDX 32
#define LP_GPIO_MAP_DATE_IDX 0x230323

1267
components/soc/esp32p4/include/soc/lp_gpio_struct.h
View File

File diff suppressed because it is too large Load Diff

843
components/soc/esp32p4/include/soc/lp_iomux_struct.h
View File

@ -42,836 +42,56 @@ typedef union {
} lp_iomux_ver_date_reg_t;
/** Group: pad0 */
/** Type of pad0 register
/** Group: pad */
/** Type of pad register
* Reserved
*/
typedef union {
struct {
/** reg_pad0_drv : R/W; bitpos: [1:0]; default: 2;
/** drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad0_drv:2;
/** reg_pad0_rde : R/W; bitpos: [2]; default: 0;
uint32_t drv:2;
/** rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad0_rde:1;
/** reg_pad0_rue : R/W; bitpos: [3]; default: 0;
uint32_t rde:1;
/** rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad0_rue:1;
/** reg_pad0_mux_sel : R/W; bitpos: [4]; default: 0;
uint32_t rue:1;
/** mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad0_mux_sel:1;
/** reg_pad0_fun_sel : R/W; bitpos: [6:5]; default: 0;
uint32_t mux_sel:1;
/** fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad0_fun_sel:2;
/** reg_pad0_slp_sel : R/W; bitpos: [7]; default: 0;
uint32_t fun_sel:2;
/** slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad0_slp_sel:1;
/** reg_pad0_slp_ie : R/W; bitpos: [8]; default: 0;
uint32_t slp_sel:1;
/** slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad0_slp_ie:1;
/** reg_pad0_slp_oe : R/W; bitpos: [9]; default: 0;
uint32_t slp_ie:1;
/** slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad0_slp_oe:1;
/** reg_pad0_fun_ie : R/W; bitpos: [10]; default: 0;
uint32_t slp_oe:1;
/** fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad0_fun_ie:1;
/** reg_pad0_filter_en : R/W; bitpos: [11]; default: 0;
uint32_t fun_ie:1;
/** filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad0_filter_en:1;
uint32_t filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad0_reg_t;
/** Group: pad1 */
/** Type of pad1 register
* Reserved
*/
typedef union {
struct {
/** reg_pad1_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad1_drv:2;
/** reg_pad1_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad1_rde:1;
/** reg_pad1_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad1_rue:1;
/** reg_pad1_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad1_mux_sel:1;
/** reg_pad1_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad1_fun_sel:2;
/** reg_pad1_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad1_slp_sel:1;
/** reg_pad1_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad1_slp_ie:1;
/** reg_pad1_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad1_slp_oe:1;
/** reg_pad1_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad1_fun_ie:1;
/** reg_pad1_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad1_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad1_reg_t;
/** Group: pad2 */
/** Type of pad2 register
* Reserved
*/
typedef union {
struct {
/** reg_pad2_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad2_drv:2;
/** reg_pad2_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad2_rde:1;
/** reg_pad2_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad2_rue:1;
/** reg_pad2_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad2_mux_sel:1;
/** reg_pad2_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad2_fun_sel:2;
/** reg_pad2_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad2_slp_sel:1;
/** reg_pad2_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad2_slp_ie:1;
/** reg_pad2_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad2_slp_oe:1;
/** reg_pad2_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad2_fun_ie:1;
/** reg_pad2_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad2_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad2_reg_t;
/** Group: pad3 */
/** Type of pad3 register
* Reserved
*/
typedef union {
struct {
/** reg_pad3_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad3_drv:2;
/** reg_pad3_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad3_rde:1;
/** reg_pad3_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad3_rue:1;
/** reg_pad3_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad3_mux_sel:1;
/** reg_pad3_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad3_fun_sel:2;
/** reg_pad3_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad3_slp_sel:1;
/** reg_pad3_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad3_slp_ie:1;
/** reg_pad3_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad3_slp_oe:1;
/** reg_pad3_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad3_fun_ie:1;
/** reg_pad3_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad3_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad3_reg_t;
/** Group: pad4 */
/** Type of pad4 register
* Reserved
*/
typedef union {
struct {
/** reg_pad4_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad4_drv:2;
/** reg_pad4_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad4_rde:1;
/** reg_pad4_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad4_rue:1;
/** reg_pad4_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad4_mux_sel:1;
/** reg_pad4_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad4_fun_sel:2;
/** reg_pad4_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad4_slp_sel:1;
/** reg_pad4_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad4_slp_ie:1;
/** reg_pad4_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad4_slp_oe:1;
/** reg_pad4_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad4_fun_ie:1;
/** reg_pad4_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad4_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad4_reg_t;
/** Group: pad5 */
/** Type of pad5 register
* Reserved
*/
typedef union {
struct {
/** reg_pad5_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad5_drv:2;
/** reg_pad5_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad5_rde:1;
/** reg_pad5_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad5_rue:1;
/** reg_pad5_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad5_mux_sel:1;
/** reg_pad5_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad5_fun_sel:2;
/** reg_pad5_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad5_slp_sel:1;
/** reg_pad5_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad5_slp_ie:1;
/** reg_pad5_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad5_slp_oe:1;
/** reg_pad5_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad5_fun_ie:1;
/** reg_pad5_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad5_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad5_reg_t;
/** Group: pad6 */
/** Type of pad6 register
* Reserved
*/
typedef union {
struct {
/** reg_pad6_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad6_drv:2;
/** reg_pad6_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad6_rde:1;
/** reg_pad6_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad6_rue:1;
/** reg_pad6_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad6_mux_sel:1;
/** reg_pad6_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad6_fun_sel:2;
/** reg_pad6_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad6_slp_sel:1;
/** reg_pad6_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad6_slp_ie:1;
/** reg_pad6_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad6_slp_oe:1;
/** reg_pad6_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad6_fun_ie:1;
/** reg_pad6_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad6_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad6_reg_t;
/** Group: pad7 */
/** Type of pad7 register
* Reserved
*/
typedef union {
struct {
/** reg_pad7_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad7_drv:2;
/** reg_pad7_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad7_rde:1;
/** reg_pad7_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad7_rue:1;
/** reg_pad7_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad7_mux_sel:1;
/** reg_pad7_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad7_fun_sel:2;
/** reg_pad7_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad7_slp_sel:1;
/** reg_pad7_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad7_slp_ie:1;
/** reg_pad7_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad7_slp_oe:1;
/** reg_pad7_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad7_fun_ie:1;
/** reg_pad7_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad7_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad7_reg_t;
/** Group: pad8 */
/** Type of pad8 register
* Reserved
*/
typedef union {
struct {
/** reg_pad8_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad8_drv:2;
/** reg_pad8_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad8_rde:1;
/** reg_pad8_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad8_rue:1;
/** reg_pad8_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad8_mux_sel:1;
/** reg_pad8_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad8_fun_sel:2;
/** reg_pad8_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad8_slp_sel:1;
/** reg_pad8_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad8_slp_ie:1;
/** reg_pad8_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad8_slp_oe:1;
/** reg_pad8_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad8_fun_ie:1;
/** reg_pad8_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad8_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad8_reg_t;
/** Group: pad9 */
/** Type of pad9 register
* Reserved
*/
typedef union {
struct {
/** reg_pad9_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad9_drv:2;
/** reg_pad9_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad9_rde:1;
/** reg_pad9_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad9_rue:1;
/** reg_pad9_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad9_mux_sel:1;
/** reg_pad9_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad9_fun_sel:2;
/** reg_pad9_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad9_slp_sel:1;
/** reg_pad9_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad9_slp_ie:1;
/** reg_pad9_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad9_slp_oe:1;
/** reg_pad9_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad9_fun_ie:1;
/** reg_pad9_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad9_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad9_reg_t;
/** Group: pad10 */
/** Type of pad10 register
* Reserved
*/
typedef union {
struct {
/** reg_pad10_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad10_drv:2;
/** reg_pad10_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad10_rde:1;
/** reg_pad10_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad10_rue:1;
/** reg_pad10_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad10_mux_sel:1;
/** reg_pad10_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad10_fun_sel:2;
/** reg_pad10_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad10_slp_sel:1;
/** reg_pad10_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad10_slp_ie:1;
/** reg_pad10_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad10_slp_oe:1;
/** reg_pad10_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad10_fun_ie:1;
/** reg_pad10_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad10_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad10_reg_t;
/** Group: pad11 */
/** Type of pad11 register
* Reserved
*/
typedef union {
struct {
/** reg_pad11_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad11_drv:2;
/** reg_pad11_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad11_rde:1;
/** reg_pad11_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad11_rue:1;
/** reg_pad11_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad11_mux_sel:1;
/** reg_pad11_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad11_fun_sel:2;
/** reg_pad11_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad11_slp_sel:1;
/** reg_pad11_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad11_slp_ie:1;
/** reg_pad11_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad11_slp_oe:1;
/** reg_pad11_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad11_fun_ie:1;
/** reg_pad11_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad11_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad11_reg_t;
/** Group: pad12 */
/** Type of pad120 register
* Reserved
*/
typedef union {
struct {
/** reg_pad12_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad12_drv:2;
/** reg_pad12_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad12_rde:1;
/** reg_pad12_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad12_rue:1;
/** reg_pad12_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad12_mux_sel:1;
/** reg_pad12_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad12_fun_sel:2;
/** reg_pad12_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad12_slp_sel:1;
/** reg_pad12_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad12_slp_ie:1;
/** reg_pad12_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad12_slp_oe:1;
/** reg_pad12_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad12_fun_ie:1;
/** reg_pad12_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad12_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad120_reg_t;
/** Group: pad13 */
/** Type of pad13 register
* Reserved
*/
typedef union {
struct {
/** reg_pad13_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad13_drv:2;
/** reg_pad13_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad13_rde:1;
/** reg_pad13_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad13_rue:1;
/** reg_pad13_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad13_mux_sel:1;
/** reg_pad13_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad13_fun_sel:2;
/** reg_pad13_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad13_slp_sel:1;
/** reg_pad13_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad13_slp_ie:1;
/** reg_pad13_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad13_slp_oe:1;
/** reg_pad13_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad13_fun_ie:1;
/** reg_pad13_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad13_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad13_reg_t;
/** Group: pad14 */
/** Type of pad14 register
* Reserved
*/
typedef union {
struct {
/** reg_pad14_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad14_drv:2;
/** reg_pad14_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad14_rde:1;
/** reg_pad14_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad14_rue:1;
/** reg_pad14_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad14_mux_sel:1;
/** reg_pad14_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad14_fun_sel:2;
/** reg_pad14_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad14_slp_sel:1;
/** reg_pad14_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad14_slp_ie:1;
/** reg_pad14_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad14_slp_oe:1;
/** reg_pad14_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad14_fun_ie:1;
/** reg_pad14_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad14_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad14_reg_t;
/** Group: pad15 */
/** Type of pad15 register
* Reserved
*/
typedef union {
struct {
/** reg_pad15_drv : R/W; bitpos: [1:0]; default: 2;
* Reserved
*/
uint32_t reg_pad15_drv:2;
/** reg_pad15_rde : R/W; bitpos: [2]; default: 0;
* Reserved
*/
uint32_t reg_pad15_rde:1;
/** reg_pad15_rue : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t reg_pad15_rue:1;
/** reg_pad15_mux_sel : R/W; bitpos: [4]; default: 0;
* 1:use LP GPIO,0: use digital GPIO
*/
uint32_t reg_pad15_mux_sel:1;
/** reg_pad15_fun_sel : R/W; bitpos: [6:5]; default: 0;
* function sel
*/
uint32_t reg_pad15_fun_sel:2;
/** reg_pad15_slp_sel : R/W; bitpos: [7]; default: 0;
* 1: enable sleep mode during sleep,0: no sleep mode
*/
uint32_t reg_pad15_slp_sel:1;
/** reg_pad15_slp_ie : R/W; bitpos: [8]; default: 0;
* input enable in sleep mode
*/
uint32_t reg_pad15_slp_ie:1;
/** reg_pad15_slp_oe : R/W; bitpos: [9]; default: 0;
* output enable in sleep mode
*/
uint32_t reg_pad15_slp_oe:1;
/** reg_pad15_fun_ie : R/W; bitpos: [10]; default: 0;
* input enable in work mode
*/
uint32_t reg_pad15_fun_ie:1;
/** reg_pad15_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t reg_pad15_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_iomux_pad15_reg_t;
} lp_iomux_pad_reg_t;
/** Group: ext_wakeup0_sel */
@ -929,22 +149,7 @@ typedef union {
typedef struct lp_iomux_dev_t {
volatile lp_iomux_clk_en_reg_t clk_en;
volatile lp_iomux_ver_date_reg_t ver_date;
volatile lp_iomux_pad0_reg_t pad0;
volatile lp_iomux_pad1_reg_t pad1;
volatile lp_iomux_pad2_reg_t pad2;
volatile lp_iomux_pad3_reg_t pad3;
volatile lp_iomux_pad4_reg_t pad4;
volatile lp_iomux_pad5_reg_t pad5;
volatile lp_iomux_pad6_reg_t pad6;
volatile lp_iomux_pad7_reg_t pad7;
volatile lp_iomux_pad8_reg_t pad8;
volatile lp_iomux_pad9_reg_t pad9;
volatile lp_iomux_pad10_reg_t pad10;
volatile lp_iomux_pad11_reg_t pad11;
volatile lp_iomux_pad120_reg_t pad120;
volatile lp_iomux_pad13_reg_t pad13;
volatile lp_iomux_pad14_reg_t pad14;
volatile lp_iomux_pad15_reg_t pad15;
volatile lp_iomux_pad_reg_t pad[16];
volatile lp_iomux_ext_wakeup0_sel_reg_t ext_wakeup0_sel;
volatile lp_iomux_lp_pad_hold_reg_t lp_pad_hold;
volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys;

56
components/soc/esp32p4/include/soc/rtc_io_channel.h Normal file
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@ -0,0 +1,56 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 2
#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 3
#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 4
#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 5
#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6
#define RTCIO_CHANNEL_6_GPIO_NUM 6
#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7
#define RTCIO_CHANNEL_7_GPIO_NUM 7
#define RTCIO_GPIO8_CHANNEL 8 //RTCIO_CHANNEL_8
#define RTCIO_CHANNEL_8_GPIO_NUM 8
#define RTCIO_GPIO9_CHANNEL 9 //RTCIO_CHANNEL_9
#define RTCIO_CHANNEL_9_GPIO_NUM 9
#define RTCIO_GPIO10_CHANNEL 10 //RTCIO_CHANNEL_10
#define RTCIO_CHANNEL_10_GPIO_NUM 10
#define RTCIO_GPIO11_CHANNEL 11 //RTCIO_CHANNEL_11
#define RTCIO_CHANNEL_11_GPIO_NUM 11
#define RTCIO_GPIO12_CHANNEL 12 //RTCIO_CHANNEL_12
#define RTCIO_CHANNEL_12_GPIO_NUM 12
#define RTCIO_GPIO13_CHANNEL 13 //RTCIO_CHANNEL_13
#define RTCIO_CHANNEL_13_GPIO_NUM 13
#define RTCIO_GPIO14_CHANNEL 14 //RTCIO_CHANNEL_14
#define RTCIO_CHANNEL_14_GPIO_NUM 14
#define RTCIO_GPIO15_CHANNEL 15 //RTCIO_CHANNEL_15
#define RTCIO_CHANNEL_15_GPIO_NUM 15

15
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -71,6 +71,8 @@
// #define SOC_PMU_SUPPORTED 1 //TODO: IDF-7531
// #define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531
// #define SOC_LP_TIMER_SUPPORTED 1 //TODO: IDF-7532
#define SOC_LP_GPIO_MATRIX_SUPPORTED 1
#define SOC_LP_PERIPHERALS_SUPPORTED 1
#define SOC_SPIRAM_SUPPORTED 1
// #define SOC_ULP_SUPPORTED 1 //TODO: IDF-7534
// #define SOC_SDMMC_HOST_SUPPORTED 1 //TODO: IDF-6502
@ -189,7 +191,7 @@
// On ESP32-P4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// GPIO0~15 on ESP32P4 can support chip deep sleep wakeup
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // TODO: IDF-7480
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_VALID_GPIO_MASK (0x01FFFFFFFFFFFFFF)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
@ -204,10 +206,13 @@
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
// #define SOC_RTCIO_PIN_COUNT 16 //TODO: IDF-7480
// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 //TODO: IDF-7480
// #define SOC_RTCIO_HOLD_SUPPORTED 1 //TODO: IDF-7480
// #define SOC_RTCIO_WAKE_SUPPORTED 1 //TODO: IDF-7480
#define SOC_RTCIO_PIN_COUNT 16
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
* so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
* when the pins are switched to RTC function.
*/
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */

67
components/soc/esp32p4/rtc_io_periph.c Normal file
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@ -0,0 +1,67 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/rtc_periph.h"
const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO0_CHANNEL, //GPIO0
RTCIO_GPIO1_CHANNEL, //GPIO1
RTCIO_GPIO2_CHANNEL, //GPIO2
RTCIO_GPIO3_CHANNEL, //GPIO3
RTCIO_GPIO4_CHANNEL, //GPIO4
RTCIO_GPIO5_CHANNEL, //GPIO5
RTCIO_GPIO6_CHANNEL, //GPIO6
RTCIO_GPIO7_CHANNEL, //GPIO7
RTCIO_GPIO8_CHANNEL, //GPIO8
RTCIO_GPIO9_CHANNEL, //GPIO9
RTCIO_GPIO10_CHANNEL, //GPIO10
RTCIO_GPIO11_CHANNEL, //GPIO11
RTCIO_GPIO12_CHANNEL, //GPIO12
RTCIO_GPIO13_CHANNEL, //GPIO13
RTCIO_GPIO14_CHANNEL, //GPIO14
RTCIO_GPIO15_CHANNEL, //GPIO15
-1,//GPIO16
-1,//GPIO17
-1,//GPIO18
-1,//GPIO19
-1,//GPIO20
-1,//GPIO21
-1,//GPIO22
-1,//GPIO23
-1,//GPIO24
-1,//GPIO25
-1,//GPIO26
-1,//GPIO27
-1,//GPIO28
-1,//GPIO29
-1,//GPIO30
-1,//GPIO31
-1,//GPIO32
-1,//GPIO33
-1,//GPIO34
-1,//GPIO35
-1,//GPIO36
-1,//GPIO37
-1,//GPIO38
-1,//GPIO39
-1,//GPIO40
-1,//GPIO41
-1,//GPIO42
-1,//GPIO43
-1,//GPIO44
-1,//GPIO45
-1,//GPIO46
-1,//GPIO47
-1,//GPIO48
-1,//GPIO49
-1,//GPIO50
-1,//GPIO51
-1,//GPIO52
-1,//GPIO53
-1,//GPIO54
-1,//GPIO55
-1,//GPIO56
};

1
components/soc/esp32s2/rtc_io_periph.c
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@ -5,6 +5,7 @@
*/
#include "soc/rtc_periph.h"
#include "soc/rtc_io_reg.h"
const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO0_CHANNEL, //GPIO0

1
components/soc/esp32s3/rtc_io_periph.c
View File

@ -5,6 +5,7 @@
*/
#include "soc/rtc_periph.h"
#include "soc/rtc_io_reg.h"
const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO0_CHANNEL, //GPIO0

4
components/soc/include/soc/rtc_io_periph.h
View File

@ -13,10 +13,6 @@
#if SOC_RTCIO_PIN_COUNT > 0
#include "soc/rtc_io_channel.h"
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#include "soc/rtc_io_reg.h"
#include "soc/rtc_io_struct.h"
#endif
#endif
#if SOC_ADC_RTC_CTRL_SUPPORTED

7
components/ulp/lp_core/lp_core/include/ulp_lp_core_gpio.h
View File

@ -13,6 +13,9 @@ extern "C" {
#include "hal/gpio_types.h"
#include "hal/rtc_io_ll.h"
#define RTCIO_OUTPUT_NORMAL _Pragma ("GCC warning \"'RTCIO_OUTPUT_NORMAL' macro is deprecated\"") RTCIO_LL_OUTPUT_NORMAL
#define RTCIO_OUTPUT_OD _Pragma ("GCC warning \"'RTCIO_OUTPUT_OD' macro is deprecated\"") RTCIO_LL_OUTPUT_OD
typedef enum {
LP_IO_NUM_0 = 0, /*!< GPIO0, input and output */
LP_IO_NUM_1 = 1, /*!< GPIO1, input and output */
@ -31,7 +34,7 @@ typedef enum {
*/
static inline void ulp_lp_core_gpio_init(lp_io_num_t lp_io_num)
{
rtcio_ll_function_select(lp_io_num, RTCIO_FUNC_RTC);
rtcio_ll_function_select(lp_io_num, RTCIO_LL_FUNC_RTC);
}
/**
@ -99,7 +102,7 @@ static inline uint32_t ulp_lp_core_gpio_get_level(lp_io_num_t lp_io_num)
* @brief Set rtcio output mode
*
* @param lp_io_num The rtc io pin to set the output mode for
* @param mode RTCIO_OUTPUT_NORMAL: normal, RTCIO_OUTPUT_OD: open drain
* @param mode RTCIO_LL_OUTPUT_NORMAL: normal, RTCIO_LL_OUTPUT_OD: open drain
*/
static inline void ulp_lp_core_gpio_set_output_mode(lp_io_num_t lp_io_num, rtcio_ll_out_mode_t mode)
{

9
docs/en/api-reference/peripherals/gpio.rst
View File

@ -13,13 +13,20 @@ GPIO Summary
.. only:: SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
.. only:: not SOC_LP_PERIPHERALS_SUPPORTED
There is also separate "RTC GPIO" support, which functions when GPIOs are routed to the "RTC" low-power and analog subsystem. These pin functions can be used when:
.. only:: SOC_LP_PERIPHERALS_SUPPORTED
There is also separate "RTC GPIO" support, which functions when GPIOs are routed to the "RTC" low-power, analog subsystem, and Low-Power(LP) peripherals. These pin functions can be used when:
.. list::
- In Deep-sleep mode
:SOC_ULP_SUPPORTED and not esp32c6: - The :doc:`Ultra Low Power co-processor <../../api-reference/system/ulp>` is running
- Analog functions such as ADC/DAC/etc are in use.
- Analog functions such as ADC/DAC/etc are in use
:SOC_LP_PERIPHERALS_SUPPORTED: - LP peripherals, such as LP_UART, LP_I2C, are in use
.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER or SOC_GPIO_FLEX_GLITCH_FILTER_NUM

7
docs/zh_CN/api-reference/peripherals/gpio.rst
View File

@ -13,13 +13,20 @@ GPIO 汇总
.. only:: SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
.. only:: not SOC_LP_PERIPHERALS_SUPPORTED
当 GPIO 连接到 RTC 低功耗和模拟子系统时，{IDF_TARGET_NAME} 芯片还单独支持 RTC GPIO。可在以下情况时使用这些管脚功能：
.. only:: SOC_LP_PERIPHERALS_SUPPORTED
当 GPIO 连接到 RTC 低功耗、模拟子系统、低功耗外设时，{IDF_TARGET_NAME} 芯片还单独支持 RTC GPIO。可在以下情况时使用这些管脚功能：
.. list::
- 处于 Deep-sleep 模式时
:SOC_ULP_SUPPORTED and not esp32c6: - :doc:`超低功耗协处理器 (ULP) <../../api-reference/system/ulp>` 运行时
- 使用 ADC/DAC 等模拟功能时
:SOC_LP_PERIPHERALS_SUPPORTED: - 使用低功耗外设时，例如： LP_UART ， LP_I2C 等
.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER or SOC_GPIO_FLEX_GLITCH_FILTER_NUM